[linux-2.6-block.git] / arch / powerpc / include / asm / imc-pmu.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __ASM_POWERPC_IMC_PMU_H
#define __ASM_POWERPC_IMC_PMU_H

/*
 * IMC Nest Performance Monitor counter support.
 *
 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
 *           (C) 2017 Anju T Sudhakar, IBM Corporation.
 *           (C) 2017 Hemant K Shaw, IBM Corporation.
 */

#include <linux/perf_event.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/io.h>
#include <asm/opal.h>

/*
 * Compatibility macros for IMC devices
 */
#define IMC_DTB_COMPAT			"ibm,opal-in-memory-counters"
#define IMC_DTB_UNIT_COMPAT		"ibm,imc-counters"


/*
 * LDBAR: Counter address and Enable/Disable macro.
 * perf/imc-pmu.c has the LDBAR layout information.
 */
#define THREAD_IMC_LDBAR_MASK           0x0003ffffffffe000ULL
#define THREAD_IMC_ENABLE               0x8000000000000000ULL
#define TRACE_IMC_ENABLE		0x4000000000000000ULL

/*
 * For debugfs interface for imc-mode and imc-command
 */
#define IMC_CNTL_BLK_OFFSET		0x3FC00
#define IMC_CNTL_BLK_CMD_OFFSET		8
#define IMC_CNTL_BLK_MODE_OFFSET	32

/*
 * Structure to hold memory address information for imc units.
 */
struct imc_mem_info {
	u64 *vbase;
	u32 id;
};

/*
 * Place holder for nest pmu events and values.
 */
struct imc_events {
	u32 value;
	char *name;
	char *unit;
	char *scale;
};

/*
 * Trace IMC hardware updates a 64bytes record on
 * Core Performance Monitoring Counter (CPMC)
 * overflow. Here is the layout for the trace imc record
 *
 * DW 0 : Timebase
 * DW 1 : Program Counter
 * DW 2 : PIDR information
 * DW 3 : CPMC1
 * DW 4 : CPMC2
 * DW 5 : CPMC3
 * Dw 6 : CPMC4
 * DW 7 : Timebase
 * .....
 *
 * The following is the data structure to hold trace imc data.
 */
struct trace_imc_data {
	u64 tb1;
	u64 ip;
	u64 val;
	u64 cpmc1;
	u64 cpmc2;
	u64 cpmc3;
	u64 cpmc4;
	u64 tb2;
};

/* Event attribute array index */
#define IMC_FORMAT_ATTR		0
#define IMC_EVENT_ATTR		1
#define IMC_CPUMASK_ATTR	2
#define IMC_NULL_ATTR		3

/* PMU Format attribute macros */
#define IMC_EVENT_OFFSET_MASK	0xffffffffULL

/*
 * Macro to mask bits 0:21 of first double word(which is the timebase) to
 * compare with 8th double word (timebase) of trace imc record data.
 */
#define IMC_TRACE_RECORD_TB1_MASK      0x3ffffffffffULL


/*
 * Device tree parser code detects IMC pmu support and
 * registers new IMC pmus. This structure will hold the
 * pmu functions, events, counter memory information
 * and attrs for each imc pmu and will be referenced at
 * the time of pmu registration.
 */
struct imc_pmu {
	struct pmu pmu;
	struct imc_mem_info *mem_info;
	struct imc_events *events;
	/*
	 * Attribute groups for the PMU. Slot 0 used for
	 * format attribute, slot 1 used for cpusmask attribute,
	 * slot 2 used for event attribute. Slot 3 keep as
	 * NULL.
	 */
	const struct attribute_group *attr_groups[4];
	u32 counter_mem_size;
	int domain;
	/*
	 * flag to notify whether the memory is mmaped
	 * or allocated by kernel.
	 */
	bool imc_counter_mmaped;
};

/*
 * Structure to hold id, lock and reference count for the imc events which
 * are inited.
 */
struct imc_pmu_ref {
	struct mutex lock;
	unsigned int id;
	int refc;
};

/*
 * In-Memory Collection Counters type.
 * Data comes from Device tree.
 * Three device type are supported.
 */

enum {
	IMC_TYPE_THREAD		= 0x1,
	IMC_TYPE_TRACE		= 0x2,
	IMC_TYPE_CORE		= 0x4,
	IMC_TYPE_CHIP           = 0x10,
};

/*
 * Domains for IMC PMUs
 */
#define IMC_DOMAIN_NEST		1
#define IMC_DOMAIN_CORE		2
#define IMC_DOMAIN_THREAD	3
/* For trace-imc the domain is still thread but it operates in trace-mode */
#define IMC_DOMAIN_TRACE	4

extern int init_imc_pmu(struct device_node *parent,
				struct imc_pmu *pmu_ptr, int pmu_id);
extern void thread_imc_disable(void);
extern int get_max_nest_dev(void);
extern void unregister_thread_imc(void);
#endif /* __ASM_POWERPC_IMC_PMU_H */
Commit	Line	Data
f4344b19	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
8f95faaa MS	2	#ifndef __ASM_POWERPC_IMC_PMU_H
	3	#define __ASM_POWERPC_IMC_PMU_H
	4
	5	/*
	6	* IMC Nest Performance Monitor counter support.
	7	*
	8	* Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
	9	* (C) 2017 Anju T Sudhakar, IBM Corporation.
	10	* (C) 2017 Hemant K Shaw, IBM Corporation.
8f95faaa MS	11	*/
	12
	13	#include <linux/perf_event.h>
	14	#include <linux/slab.h>
	15	#include <linux/of.h>
	16	#include <linux/io.h>
	17	#include <asm/opal.h>
	18
8f95faaa MS	19	/*
	20	* Compatibility macros for IMC devices
	21	*/
	22	#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters"
	23	#define IMC_DTB_UNIT_COMPAT "ibm,imc-counters"
	24
	25
	26	/*
	27	* LDBAR: Counter address and Enable/Disable macro.
	28	* perf/imc-pmu.c has the LDBAR layout information.
	29	*/
	30	#define THREAD_IMC_LDBAR_MASK 0x0003ffffffffe000ULL
	31	#define THREAD_IMC_ENABLE 0x8000000000000000ULL
d1720adf	32	#define TRACE_IMC_ENABLE 0x4000000000000000ULL
8f95faaa	33
684d9840 AS	34	/*
	35	* For debugfs interface for imc-mode and imc-command
	36	*/
	37	#define IMC_CNTL_BLK_OFFSET 0x3FC00
	38	#define IMC_CNTL_BLK_CMD_OFFSET 8
	39	#define IMC_CNTL_BLK_MODE_OFFSET 32
	40
8f95faaa MS	41	/*
	42	* Structure to hold memory address information for imc units.
	43	*/
	44	struct imc_mem_info {
	45	u64 *vbase;
	46	u32 id;
	47	};
	48
	49	/*
	50	* Place holder for nest pmu events and values.
	51	*/
	52	struct imc_events {
	53	u32 value;
	54	char *name;
	55	char *unit;
	56	char *scale;
	57	};
	58
d1720adf AS	59	/*
	60	* Trace IMC hardware updates a 64bytes record on
	61	* Core Performance Monitoring Counter (CPMC)
	62	* overflow. Here is the layout for the trace imc record
	63	*
	64	* DW 0 : Timebase
	65	* DW 1 : Program Counter
	66	* DW 2 : PIDR information
	67	* DW 3 : CPMC1
	68	* DW 4 : CPMC2
	69	* DW 5 : CPMC3
	70	* Dw 6 : CPMC4
	71	* DW 7 : Timebase
	72	* .....
	73	*
	74	* The following is the data structure to hold trace imc data.
	75	*/
	76	struct trace_imc_data {
	77	u64 tb1;
	78	u64 ip;
	79	u64 val;
	80	u64 cpmc1;
	81	u64 cpmc2;
	82	u64 cpmc3;
	83	u64 cpmc4;
	84	u64 tb2;
	85	};
	86
8f95faaa MS	87	/* Event attribute array index */
	88	#define IMC_FORMAT_ATTR 0
	89	#define IMC_EVENT_ATTR 1
	90	#define IMC_CPUMASK_ATTR 2
	91	#define IMC_NULL_ATTR 3
	92
	93	/* PMU Format attribute macros */
	94	#define IMC_EVENT_OFFSET_MASK 0xffffffffULL
	95
d1720adf AS	96	/*
	97	* Macro to mask bits 0:21 of first double word(which is the timebase) to
	98	* compare with 8th double word (timebase) of trace imc record data.
	99	*/
	100	#define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL
	101
	102
8f95faaa MS	103	/*
	104	* Device tree parser code detects IMC pmu support and
	105	* registers new IMC pmus. This structure will hold the
	106	* pmu functions, events, counter memory information
	107	* and attrs for each imc pmu and will be referenced at
	108	* the time of pmu registration.
	109	*/
	110	struct imc_pmu {
	111	struct pmu pmu;
	112	struct imc_mem_info *mem_info;
8b4e6dea	113	struct imc_events *events;
8f95faaa MS	114	/*
	115	* Attribute groups for the PMU. Slot 0 used for
	116	* format attribute, slot 1 used for cpusmask attribute,
	117	* slot 2 used for event attribute. Slot 3 keep as
	118	* NULL.
	119	*/
	120	const struct attribute_group *attr_groups[4];
	121	u32 counter_mem_size;
	122	int domain;
	123	/*
	124	* flag to notify whether the memory is mmaped
	125	* or allocated by kernel.
	126	*/
	127	bool imc_counter_mmaped;
	128	};
	129
	130	/*
	131	* Structure to hold id, lock and reference count for the imc events which
	132	* are inited.
	133	*/
	134	struct imc_pmu_ref {
	135	struct mutex lock;
	136	unsigned int id;
	137	int refc;
	138	};
	139
	140	/*
	141	* In-Memory Collection Counters type.
	142	* Data comes from Device tree.
	143	* Three device type are supported.
	144	*/
	145
	146	enum {
	147	IMC_TYPE_THREAD = 0x1,
d1720adf	148	IMC_TYPE_TRACE = 0x2,
8f95faaa MS	149	IMC_TYPE_CORE = 0x4,
	150	IMC_TYPE_CHIP = 0x10,
	151	};
	152
	153	/*
	154	* Domains for IMC PMUs
	155	*/
	156	#define IMC_DOMAIN_NEST 1
	157	#define IMC_DOMAIN_CORE 2
	158	#define IMC_DOMAIN_THREAD 3
d1720adf AS	159	/* For trace-imc the domain is still thread but it operates in trace-mode */
d1720adf AS	160	#define IMC_DOMAIN_TRACE 4
8f95faaa MS	161
	162	extern int init_imc_pmu(struct device_node *parent,
	163	struct imc_pmu *pmu_ptr, int pmu_id);
	164	extern void thread_imc_disable(void);
73ce9aec	165	extern int get_max_nest_dev(void);
25af86b2	166	extern void unregister_thread_imc(void);
8f95faaa	167	#endif /* __ASM_POWERPC_IMC_PMU_H */