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6d779079 GS |
1 | #ifndef _ASM_POWERPC_HUGETLB_H |
2 | #define _ASM_POWERPC_HUGETLB_H | |
3 | ||
41151e77 | 4 | #ifdef CONFIG_HUGETLB_PAGE |
6d779079 | 5 | #include <asm/page.h> |
106c992a | 6 | #include <asm-generic/hugetlb.h> |
6d779079 | 7 | |
41151e77 | 8 | extern struct kmem_cache *hugepte_cache; |
41151e77 | 9 | |
cf9427b8 | 10 | #ifdef CONFIG_PPC_BOOK3S_64 |
48483760 AK |
11 | |
12 | #include <asm/book3s/64/hugetlb-radix.h> | |
cf9427b8 AK |
13 | /* |
14 | * This should work for other subarchs too. But right now we use the | |
15 | * new format only for 64bit book3s | |
16 | */ | |
17 | static inline pte_t *hugepd_page(hugepd_t hpd) | |
18 | { | |
19 | BUG_ON(!hugepd_ok(hpd)); | |
20 | /* | |
21 | * We have only four bits to encode, MMU page size | |
22 | */ | |
23 | BUILD_BUG_ON((MMU_PAGE_COUNT - 1) > 0xf); | |
c61a8843 | 24 | return __va(hpd.pd & HUGEPD_ADDR_MASK); |
cf9427b8 AK |
25 | } |
26 | ||
27 | static inline unsigned int hugepd_mmu_psize(hugepd_t hpd) | |
28 | { | |
29 | return (hpd.pd & HUGEPD_SHIFT_MASK) >> 2; | |
30 | } | |
31 | ||
32 | static inline unsigned int hugepd_shift(hugepd_t hpd) | |
33 | { | |
34 | return mmu_psize_to_shift(hugepd_mmu_psize(hpd)); | |
35 | } | |
48483760 AK |
36 | static inline void flush_hugetlb_page(struct vm_area_struct *vma, |
37 | unsigned long vmaddr) | |
38 | { | |
39 | if (radix_enabled()) | |
40 | return radix__flush_hugetlb_page(vma, vmaddr); | |
41 | } | |
cf9427b8 | 42 | |
48483760 AK |
43 | static inline void __local_flush_hugetlb_page(struct vm_area_struct *vma, |
44 | unsigned long vmaddr) | |
45 | { | |
46 | if (radix_enabled()) | |
47 | return radix__local_flush_hugetlb_page(vma, vmaddr); | |
48 | } | |
cf9427b8 AK |
49 | #else |
50 | ||
41151e77 BB |
51 | static inline pte_t *hugepd_page(hugepd_t hpd) |
52 | { | |
53 | BUG_ON(!hugepd_ok(hpd)); | |
54 | return (pte_t *)((hpd.pd & ~HUGEPD_SHIFT_MASK) | PD_HUGE); | |
55 | } | |
56 | ||
57 | static inline unsigned int hugepd_shift(hugepd_t hpd) | |
58 | { | |
59 | return hpd.pd & HUGEPD_SHIFT_MASK; | |
60 | } | |
61 | ||
cf9427b8 AK |
62 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
63 | ||
64 | ||
b30e7590 | 65 | static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr, |
41151e77 BB |
66 | unsigned pdshift) |
67 | { | |
68 | /* | |
881fde1d BB |
69 | * On FSL BookE, we have multiple higher-level table entries that |
70 | * point to the same hugepte. Just use the first one since they're all | |
41151e77 BB |
71 | * identical. So for that case, idx=0. |
72 | */ | |
73 | unsigned long idx = 0; | |
74 | ||
b30e7590 | 75 | pte_t *dir = hugepd_page(hpd); |
881fde1d | 76 | #ifndef CONFIG_PPC_FSL_BOOK3E |
b30e7590 | 77 | idx = (addr & ((1UL << pdshift) - 1)) >> hugepd_shift(hpd); |
41151e77 BB |
78 | #endif |
79 | ||
80 | return dir + idx; | |
81 | } | |
82 | ||
883a3e52 DG |
83 | pte_t *huge_pte_offset_and_shift(struct mm_struct *mm, |
84 | unsigned long addr, unsigned *shift); | |
85 | ||
0895ecda DG |
86 | void flush_dcache_icache_hugepage(struct page *page); |
87 | ||
ca5f1d16 | 88 | #if defined(CONFIG_PPC_MM_SLICES) |
6d779079 GS |
89 | int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr, |
90 | unsigned long len); | |
41151e77 BB |
91 | #else |
92 | static inline int is_hugepage_only_range(struct mm_struct *mm, | |
93 | unsigned long addr, | |
94 | unsigned long len) | |
95 | { | |
96 | return 0; | |
97 | } | |
98 | #endif | |
99 | ||
d93e4d7d BB |
100 | void book3e_hugetlb_preload(struct vm_area_struct *vma, unsigned long ea, |
101 | pte_t pte); | |
41151e77 | 102 | void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr); |
6d779079 | 103 | |
42b77728 | 104 | void hugetlb_free_pgd_range(struct mmu_gather *tlb, unsigned long addr, |
6d779079 GS |
105 | unsigned long end, unsigned long floor, |
106 | unsigned long ceiling); | |
107 | ||
3340289d MG |
108 | /* |
109 | * The version of vma_mmu_pagesize() in arch/powerpc/mm/hugetlbpage.c needs | |
110 | * to override the version in mm/hugetlb.c | |
111 | */ | |
112 | #define vma_mmu_pagesize vma_mmu_pagesize | |
113 | ||
6d779079 GS |
114 | /* |
115 | * If the arch doesn't supply something else, assume that hugepage | |
116 | * size aligned regions are ok without further preparation. | |
117 | */ | |
a5516438 AK |
118 | static inline int prepare_hugepage_range(struct file *file, |
119 | unsigned long addr, unsigned long len) | |
6d779079 | 120 | { |
0d9ea754 JT |
121 | struct hstate *h = hstate_file(file); |
122 | if (len & ~huge_page_mask(h)) | |
6d779079 | 123 | return -EINVAL; |
0d9ea754 | 124 | if (addr & ~huge_page_mask(h)) |
6d779079 GS |
125 | return -EINVAL; |
126 | return 0; | |
127 | } | |
128 | ||
0895ecda DG |
129 | static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, |
130 | pte_t *ptep, pte_t pte) | |
131 | { | |
132 | set_pte_at(mm, addr, ptep, pte); | |
133 | } | |
134 | ||
135 | static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm, | |
136 | unsigned long addr, pte_t *ptep) | |
137 | { | |
41151e77 | 138 | #ifdef CONFIG_PPC64 |
88247e8d | 139 | return __pte(pte_update(mm, addr, ptep, ~0UL, 0, 1)); |
41151e77 BB |
140 | #else |
141 | return __pte(pte_update(ptep, ~0UL, 0)); | |
142 | #endif | |
0895ecda DG |
143 | } |
144 | ||
8fe627ec GS |
145 | static inline void huge_ptep_clear_flush(struct vm_area_struct *vma, |
146 | unsigned long addr, pte_t *ptep) | |
147 | { | |
0895ecda DG |
148 | pte_t pte; |
149 | pte = huge_ptep_get_and_clear(vma->vm_mm, addr, ptep); | |
13dce033 | 150 | flush_hugetlb_page(vma, addr); |
8fe627ec GS |
151 | } |
152 | ||
7f2e9525 GS |
153 | static inline int huge_pte_none(pte_t pte) |
154 | { | |
155 | return pte_none(pte); | |
156 | } | |
157 | ||
158 | static inline pte_t huge_pte_wrprotect(pte_t pte) | |
159 | { | |
160 | return pte_wrprotect(pte); | |
161 | } | |
162 | ||
7f2e9525 GS |
163 | static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma, |
164 | unsigned long addr, pte_t *ptep, | |
165 | pte_t pte, int dirty) | |
166 | { | |
1f6820b4 | 167 | #ifdef HUGETLB_NEED_PRELOAD |
97632e6f BB |
168 | /* |
169 | * The "return 1" forces a call of update_mmu_cache, which will write a | |
170 | * TLB entry. Without this, platforms that don't do a write of the TLB | |
171 | * entry in the TLB miss handler asm will fault ad infinitum. | |
172 | */ | |
173 | ptep_set_access_flags(vma, addr, ptep, pte, dirty); | |
174 | return 1; | |
175 | #else | |
7f2e9525 | 176 | return ptep_set_access_flags(vma, addr, ptep, pte, dirty); |
97632e6f | 177 | #endif |
7f2e9525 GS |
178 | } |
179 | ||
180 | static inline pte_t huge_ptep_get(pte_t *ptep) | |
181 | { | |
182 | return *ptep; | |
183 | } | |
184 | ||
5d3a551c WD |
185 | static inline void arch_clear_hugepage_flags(struct page *page) |
186 | { | |
187 | } | |
188 | ||
41151e77 | 189 | #else /* ! CONFIG_HUGETLB_PAGE */ |
41151e77 BB |
190 | static inline void flush_hugetlb_page(struct vm_area_struct *vma, |
191 | unsigned long vmaddr) | |
192 | { | |
193 | } | |
a6146888 | 194 | |
29409997 | 195 | #define hugepd_shift(x) 0 |
b30e7590 | 196 | static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr, |
29409997 AK |
197 | unsigned pdshift) |
198 | { | |
199 | return 0; | |
200 | } | |
201 | #endif /* CONFIG_HUGETLB_PAGE */ | |
a6146888 BB |
202 | |
203 | /* | |
204 | * FSL Book3E platforms require special gpage handling - the gpages | |
205 | * are reserved early in the boot process by memblock instead of via | |
206 | * the .dts as on IBM platforms. | |
207 | */ | |
208 | #if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_FSL_BOOK3E) | |
209 | extern void __init reserve_hugetlb_gpages(void); | |
210 | #else | |
211 | static inline void reserve_hugetlb_gpages(void) | |
212 | { | |
213 | } | |
41151e77 BB |
214 | #endif |
215 | ||
6d779079 | 216 | #endif /* _ASM_POWERPC_HUGETLB_H */ |