[linux-2.6-block.git] / arch / powerpc / include / asm / exception.h

#ifndef _ASM_POWERPC_EXCEPTION_H
#define _ASM_POWERPC_EXCEPTION_H
/*
 * Extracted from head_64.S
 *
 *  PowerPC version
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
 *  Adapted for Power Macintosh by Paul Mackerras.
 *  Low-level exception handlers and MMU support
 *  rewritten by Paul Mackerras.
 *    Copyright (C) 1996 Paul Mackerras.
 *
 *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
 *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
 *
 *  This file contains the low-level support and setup for the
 *  PowerPC-64 platform, including trap and interrupt dispatch.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */
/*
 * The following macros define the code that appears as
 * the prologue to each of the exception handlers.  They
 * are split into two parts to allow a single kernel binary
 * to be used for pSeries and iSeries.
 *
 * We make as much of the exception code common between native
 * exception handlers (including pSeries LPAR) and iSeries LPAR
 * implementations as possible.
 */

#define EX_R9		0
#define EX_R10		8
#define EX_R11		16
#define EX_R12		24
#define EX_R13		32
#define EX_SRR0		40
#define EX_DAR		48
#define EX_DSISR	56
#define EX_CCR		60
#define EX_R3		64
#define EX_LR		72

/*
 * We're short on space and time in the exception prolog, so we can't
 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
 * low halfword of the address, but for Kdump we need the whole low
 * word.
 */
#ifdef CONFIG_CRASH_DUMP
#define LOAD_HANDLER(reg, label)					\
	oris	reg,reg,(label)@h;	/* virt addr of handler ... */	\
	ori	reg,reg,(label)@l;	/* .. and the rest */
#else
#define LOAD_HANDLER(reg, label)					\
	ori	reg,reg,(label)@l;	/* virt addr of handler ... */
#endif

#define EXCEPTION_PROLOG_1(area)				\
	mfspr	r13,SPRN_SPRG3;		/* get paca address into r13 */	\
	std	r9,area+EX_R9(r13);	/* save r9 - r12 */		\
	std	r10,area+EX_R10(r13);					\
	std	r11,area+EX_R11(r13);					\
	std	r12,area+EX_R12(r13);					\
	mfspr	r9,SPRN_SPRG1;						\
	std	r9,area+EX_R13(r13);					\
	mfcr	r9

/*
 * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
 * The firmware calls the registered system_reset_fwnmi and
 * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
 * a 32bit application at the time of the event.
 * This firmware bug is present on POWER4 and JS20.
 */
#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label)		\
	EXCEPTION_PROLOG_1(area);					\
	clrrdi	r12,r13,32;		/* get high part of &label */	\
	mfmsr	r10;							\
	/* force 64bit mode */						\
	li	r11,5;			/* MSR_SF_LG|MSR_ISF_LG */	\
	rldimi	r10,r11,61,0;		/* insert into top 3 bits */	\
	/* done 64bit mode */						\
	mfspr	r11,SPRN_SRR0;		/* save SRR0 */			\
	LOAD_HANDLER(r12,label)						\
	ori	r10,r10,MSR_IR|MSR_DR|MSR_RI;				\
	mtspr	SPRN_SRR0,r12;						\
	mfspr	r12,SPRN_SRR1;		/* and SRR1 */			\
	mtspr	SPRN_SRR1,r10;						\
	rfid;								\
	b	.	/* prevent speculative execution */

#define EXCEPTION_PROLOG_PSERIES(area, label)				\
	EXCEPTION_PROLOG_1(area);					\
	clrrdi	r12,r13,32;		/* get high part of &label */	\
	mfmsr	r10;							\
	mfspr	r11,SPRN_SRR0;		/* save SRR0 */			\
	LOAD_HANDLER(r12,label)						\
	ori	r10,r10,MSR_IR|MSR_DR|MSR_RI;				\
	mtspr	SPRN_SRR0,r12;						\
	mfspr	r12,SPRN_SRR1;		/* and SRR1 */			\
	mtspr	SPRN_SRR1,r10;						\
	rfid;								\
	b	.	/* prevent speculative execution */

/*
 * The common exception prolog is used for all except a few exceptions
 * such as a segment miss on a kernel address.  We have to be prepared
 * to take another exception from the point where we first touch the
 * kernel stack onwards.
 *
 * On entry r13 points to the paca, r9-r13 are saved in the paca,
 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
 * SRR1, and relocation is on.
 */
#define EXCEPTION_PROLOG_COMMON(n, area)				   \
	andi.	r10,r12,MSR_PR;		/* See if coming from user	*/ \
	mr	r10,r1;			/* Save r1			*/ \
	subi	r1,r1,INT_FRAME_SIZE;	/* alloc frame on kernel stack	*/ \
	beq-	1f;							   \
	ld	r1,PACAKSAVE(r13);	/* kernel stack to use		*/ \
1:	cmpdi	cr1,r1,0;		/* check if r1 is in userspace	*/ \
	bge-	cr1,2f;			/* abort if it is		*/ \
	b	3f;							   \
2:	li	r1,(n);			/* will be reloaded later	*/ \
	sth	r1,PACA_TRAP_SAVE(r13);					   \
	b	bad_stack;						   \
3:	std	r9,_CCR(r1);		/* save CR in stackframe	*/ \
	std	r11,_NIP(r1);		/* save SRR0 in stackframe	*/ \
	std	r12,_MSR(r1);		/* save SRR1 in stackframe	*/ \
	std	r10,0(r1);		/* make stack chain pointer	*/ \
	std	r0,GPR0(r1);		/* save r0 in stackframe	*/ \
	std	r10,GPR1(r1);		/* save r1 in stackframe	*/ \
	ACCOUNT_CPU_USER_ENTRY(r9, r10);				   \
	std	r2,GPR2(r1);		/* save r2 in stackframe	*/ \
	SAVE_4GPRS(3, r1);		/* save r3 - r6 in stackframe	*/ \
	SAVE_2GPRS(7, r1);		/* save r7, r8 in stackframe	*/ \
	ld	r9,area+EX_R9(r13);	/* move r9, r10 to stackframe	*/ \
	ld	r10,area+EX_R10(r13);					   \
	std	r9,GPR9(r1);						   \
	std	r10,GPR10(r1);						   \
	ld	r9,area+EX_R11(r13);	/* move r11 - r13 to stackframe	*/ \
	ld	r10,area+EX_R12(r13);					   \
	ld	r11,area+EX_R13(r13);					   \
	std	r9,GPR11(r1);						   \
	std	r10,GPR12(r1);						   \
	std	r11,GPR13(r1);						   \
	ld	r2,PACATOC(r13);	/* get kernel TOC into r2	*/ \
	mflr	r9;			/* save LR in stackframe	*/ \
	std	r9,_LINK(r1);						   \
	mfctr	r10;			/* save CTR in stackframe	*/ \
	std	r10,_CTR(r1);						   \
	lbz	r10,PACASOFTIRQEN(r13);				   \
	mfspr	r11,SPRN_XER;		/* save XER in stackframe	*/ \
	std	r10,SOFTE(r1);						   \
	std	r11,_XER(r1);						   \
	li	r9,(n)+1;						   \
	std	r9,_TRAP(r1);		/* set trap number		*/ \
	li	r10,0;							   \
	ld	r11,exception_marker@toc(r2);				   \
	std	r10,RESULT(r1);		/* clear regs->result		*/ \
	std	r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame	*/

/*
 * Exception vectors.
 */
#define STD_EXCEPTION_PSERIES(n, label)			\
	. = n;						\
	.globl label##_pSeries;				\
label##_pSeries:					\
	HMT_MEDIUM;					\
	mtspr	SPRN_SPRG1,r13;		/* save r13 */	\
	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)

#define HSTD_EXCEPTION_PSERIES(n, label)		\
	. = n;						\
	.globl label##_pSeries;				\
label##_pSeries:					\
	HMT_MEDIUM;					\
	mtspr	SPRN_SPRG1,r20;		/* save r20 */	\
	mfspr	r20,SPRN_HSRR0;		/* copy HSRR0 to SRR0 */ \
	mtspr	SPRN_SRR0,r20;				\
	mfspr	r20,SPRN_HSRR1;		/* copy HSRR0 to SRR0 */ \
	mtspr	SPRN_SRR1,r20;				\
	mfspr	r20,SPRN_SPRG1;		/* restore r20 */ \
	mtspr	SPRN_SPRG1,r13;		/* save r13 */	\
	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)


#define MASKABLE_EXCEPTION_PSERIES(n, label)				\
	. = n;								\
	.globl label##_pSeries;						\
label##_pSeries:							\
	HMT_MEDIUM;							\
	mtspr	SPRN_SPRG1,r13;		/* save r13 */			\
	mfspr	r13,SPRN_SPRG3;		/* get paca address into r13 */	\
	std	r9,PACA_EXGEN+EX_R9(r13);	/* save r9, r10 */	\
	std	r10,PACA_EXGEN+EX_R10(r13);				\
	lbz	r10,PACASOFTIRQEN(r13);					\
	mfcr	r9;							\
	cmpwi	r10,0;							\
	beq	masked_interrupt;					\
	mfspr	r10,SPRN_SPRG1;						\
	std	r10,PACA_EXGEN+EX_R13(r13);				\
	std	r11,PACA_EXGEN+EX_R11(r13);				\
	std	r12,PACA_EXGEN+EX_R12(r13);				\
	clrrdi	r12,r13,32;		/* get high part of &label */	\
	mfmsr	r10;							\
	mfspr	r11,SPRN_SRR0;		/* save SRR0 */			\
	LOAD_HANDLER(r12,label##_common)				\
	ori	r10,r10,MSR_IR|MSR_DR|MSR_RI;				\
	mtspr	SPRN_SRR0,r12;						\
	mfspr	r12,SPRN_SRR1;		/* and SRR1 */			\
	mtspr	SPRN_SRR1,r10;						\
	rfid;								\
	b	.	/* prevent speculative execution */

#ifdef CONFIG_PPC_ISERIES
#define DISABLE_INTS				\
	li	r11,0;				\
	stb	r11,PACASOFTIRQEN(r13);		\
BEGIN_FW_FTR_SECTION;				\
	stb	r11,PACAHARDIRQEN(r13);		\
END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);	\
	TRACE_DISABLE_INTS;			\
BEGIN_FW_FTR_SECTION;				\
	mfmsr	r10;				\
	ori	r10,r10,MSR_EE;			\
	mtmsrd	r10,1;				\
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
#else
#define DISABLE_INTS				\
	li	r11,0;				\
	stb	r11,PACASOFTIRQEN(r13);		\
	stb	r11,PACAHARDIRQEN(r13);		\
	TRACE_DISABLE_INTS
#endif /* CONFIG_PPC_ISERIES */

#define ENABLE_INTS				\
	ld	r12,_MSR(r1);			\
	mfmsr	r11;				\
	rlwimi	r11,r12,0,MSR_EE;		\
	mtmsrd	r11,1

#define STD_EXCEPTION_COMMON(trap, label, hdlr)		\
	.align	7;					\
	.globl label##_common;				\
label##_common:						\
	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);	\
	DISABLE_INTS;					\
	bl	.save_nvgprs;				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
	bl	hdlr;					\
	b	.ret_from_except

/*
 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
 * in the idle task and therefore need the special idle handling.
 */
#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr)	\
	.align	7;					\
	.globl label##_common;				\
label##_common:						\
	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);	\
	FINISH_NAP;					\
	DISABLE_INTS;					\
	bl	.save_nvgprs;				\
	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
	bl	hdlr;					\
	b	.ret_from_except

#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr)	\
	.align	7;					\
	.globl label##_common;				\
label##_common:						\
	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);	\
	FINISH_NAP;					\
	DISABLE_INTS;					\
BEGIN_FTR_SECTION					\
	bl	.ppc64_runlatch_on;			\
END_FTR_SECTION_IFSET(CPU_FTR_CTRL)			\
	addi	r3,r1,STACK_FRAME_OVERHEAD;		\
	bl	hdlr;					\
	b	.ret_from_except_lite

/*
 * When the idle code in power4_idle puts the CPU into NAP mode,
 * it has to do so in a loop, and relies on the external interrupt
 * and decrementer interrupt entry code to get it out of the loop.
 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
 * to signal that it is in the loop and needs help to get out.
 */
#ifdef CONFIG_PPC_970_NAP
#define FINISH_NAP				\
BEGIN_FTR_SECTION				\
	clrrdi	r11,r1,THREAD_SHIFT;		\
	ld	r9,TI_LOCAL_FLAGS(r11);		\
	andi.	r10,r9,_TLF_NAPPING;		\
	bnel	power4_fixup_nap;		\
END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
#else
#define FINISH_NAP
#endif

#endif	/* _ASM_POWERPC_EXCEPTION_H */
Commit	Line	Data
f9ff0f30 SR	1	#ifndef _ASM_POWERPC_EXCEPTION_H
	2	#define _ASM_POWERPC_EXCEPTION_H
	3	/*
	4	* Extracted from head_64.S
	5	*
	6	* PowerPC version
	7	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	8	*
	9	* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
	10	* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
	11	* Adapted for Power Macintosh by Paul Mackerras.
	12	* Low-level exception handlers and MMU support
	13	* rewritten by Paul Mackerras.
	14	* Copyright (C) 1996 Paul Mackerras.
	15	*
	16	* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
	17	* Mike Corrigan {engebret\|bergner\|mikejc}@us.ibm.com
	18	*
	19	* This file contains the low-level support and setup for the
	20	* PowerPC-64 platform, including trap and interrupt dispatch.
	21	*
	22	* This program is free software; you can redistribute it and/or
	23	* modify it under the terms of the GNU General Public License
	24	* as published by the Free Software Foundation; either version
	25	* 2 of the License, or (at your option) any later version.
	26	*/
	27	/*
	28	* The following macros define the code that appears as
	29	* the prologue to each of the exception handlers. They
	30	* are split into two parts to allow a single kernel binary
	31	* to be used for pSeries and iSeries.
	32	*
	33	* We make as much of the exception code common between native
	34	* exception handlers (including pSeries LPAR) and iSeries LPAR
	35	* implementations as possible.
	36	*/
	37
	38	#define EX_R9 0
	39	#define EX_R10 8
	40	#define EX_R11 16
	41	#define EX_R12 24
	42	#define EX_R13 32
	43	#define EX_SRR0 40
	44	#define EX_DAR 48
	45	#define EX_DSISR 56
	46	#define EX_CCR 60
	47	#define EX_R3 64
	48	#define EX_LR 72
	49
	50	/*
	51	* We're short on space and time in the exception prolog, so we can't
	52	* use the normal SET_REG_IMMEDIATE macro. Normally we just need the
	53	* low halfword of the address, but for Kdump we need the whole low
	54	* word.
	55	*/
	56	#ifdef CONFIG_CRASH_DUMP
	57	#define LOAD_HANDLER(reg, label) \
	58	oris reg,reg,(label)@h; /* virt addr of handler ... */ \
	59	ori reg,reg,(label)@l; /* .. and the rest */
	60	#else
	61	#define LOAD_HANDLER(reg, label) \
	62	ori reg,reg,(label)@l; /* virt addr of handler ... */
	63	#endif
	64
7180e3e6 SR	65	#define EXCEPTION_PROLOG_1(area) \
	66	mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
	67	std r9,area+EX_R9(r13); /* save r9 - r12 */ \
	68	std r10,area+EX_R10(r13); \
	69	std r11,area+EX_R11(r13); \
	70	std r12,area+EX_R12(r13); \
	71	mfspr r9,SPRN_SPRG1; \
	72	std r9,area+EX_R13(r13); \
	73	mfcr r9
	74
f9ff0f30 SR	75	/*
	76	* Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
	77	* The firmware calls the registered system_reset_fwnmi and
	78	* machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
	79	* a 32bit application at the time of the event.
	80	* This firmware bug is present on POWER4 and JS20.
	81	*/
	82	#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \
7180e3e6	83	EXCEPTION_PROLOG_1(area); \
f9ff0f30 SR	84	clrrdi r12,r13,32; /* get high part of &label */ \
	85	mfmsr r10; \
	86	/* force 64bit mode */ \
	87	li r11,5; /* MSR_SF_LG\|MSR_ISF_LG */ \
	88	rldimi r10,r11,61,0; /* insert into top 3 bits */ \
	89	/* done 64bit mode */ \
	90	mfspr r11,SPRN_SRR0; /* save SRR0 */ \
	91	LOAD_HANDLER(r12,label) \
	92	ori r10,r10,MSR_IR\|MSR_DR\|MSR_RI; \
	93	mtspr SPRN_SRR0,r12; \
	94	mfspr r12,SPRN_SRR1; /* and SRR1 */ \
	95	mtspr SPRN_SRR1,r10; \
	96	rfid; \
	97	b . /* prevent speculative execution */
	98
	99	#define EXCEPTION_PROLOG_PSERIES(area, label) \
7180e3e6	100	EXCEPTION_PROLOG_1(area); \
f9ff0f30 SR	101	clrrdi r12,r13,32; /* get high part of &label */ \
	102	mfmsr r10; \
	103	mfspr r11,SPRN_SRR0; /* save SRR0 */ \
	104	LOAD_HANDLER(r12,label) \
	105	ori r10,r10,MSR_IR\|MSR_DR\|MSR_RI; \
	106	mtspr SPRN_SRR0,r12; \
	107	mfspr r12,SPRN_SRR1; /* and SRR1 */ \
	108	mtspr SPRN_SRR1,r10; \
	109	rfid; \
	110	b . /* prevent speculative execution */
	111
f9ff0f30 SR	112	/*
	113	* The common exception prolog is used for all except a few exceptions
	114	* such as a segment miss on a kernel address. We have to be prepared
	115	* to take another exception from the point where we first touch the
	116	* kernel stack onwards.
	117	*
	118	* On entry r13 points to the paca, r9-r13 are saved in the paca,
	119	* r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
	120	* SRR1, and relocation is on.
	121	*/
	122	#define EXCEPTION_PROLOG_COMMON(n, area) \
	123	andi. r10,r12,MSR_PR; /* See if coming from user */ \
	124	mr r10,r1; /* Save r1 */ \
	125	subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
	126	beq- 1f; \
	127	ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
	128	1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
	129	bge- cr1,2f; /* abort if it is */ \
	130	b 3f; \
	131	2: li r1,(n); /* will be reloaded later */ \
	132	sth r1,PACA_TRAP_SAVE(r13); \
	133	b bad_stack; \
	134	3: std r9,_CCR(r1); /* save CR in stackframe */ \
	135	std r11,_NIP(r1); /* save SRR0 in stackframe */ \
	136	std r12,_MSR(r1); /* save SRR1 in stackframe */ \
	137	std r10,0(r1); /* make stack chain pointer */ \
	138	std r0,GPR0(r1); /* save r0 in stackframe */ \
	139	std r10,GPR1(r1); /* save r1 in stackframe */ \
	140	ACCOUNT_CPU_USER_ENTRY(r9, r10); \
	141	std r2,GPR2(r1); /* save r2 in stackframe */ \
	142	SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
	143	SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
	144	ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
	145	ld r10,area+EX_R10(r13); \
	146	std r9,GPR9(r1); \
	147	std r10,GPR10(r1); \
	148	ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
	149	ld r10,area+EX_R12(r13); \
	150	ld r11,area+EX_R13(r13); \
	151	std r9,GPR11(r1); \
	152	std r10,GPR12(r1); \
	153	std r11,GPR13(r1); \
	154	ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
	155	mflr r9; /* save LR in stackframe */ \
	156	std r9,_LINK(r1); \
	157	mfctr r10; /* save CTR in stackframe */ \
	158	std r10,_CTR(r1); \
	159	lbz r10,PACASOFTIRQEN(r13); \
	160	mfspr r11,SPRN_XER; /* save XER in stackframe */ \
	161	std r10,SOFTE(r1); \
	162	std r11,_XER(r1); \
	163	li r9,(n)+1; \
	164	std r9,_TRAP(r1); /* set trap number */ \
	165	li r10,0; \
	166	ld r11,exception_marker@toc(r2); \
	167	std r10,RESULT(r1); /* clear regs->result */ \
	168	std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
	169
	170	/*
	171	* Exception vectors.
	172	*/
	173	#define STD_EXCEPTION_PSERIES(n, label) \
	174	. = n; \
	175	.globl label##_pSeries; \
176	label##_pSeries: \
177	HMT_MEDIUM; \
178	mtspr SPRN_SPRG1,r13; /* save r13 */ \
179	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
180
181	#define HSTD_EXCEPTION_PSERIES(n, label) \
182	. = n; \
183	.globl label##_pSeries; \
184	label##_pSeries: \
185	HMT_MEDIUM; \
186	mtspr SPRN_SPRG1,r20; /* save r20 */ \
187	mfspr r20,SPRN_HSRR0; /* copy HSRR0 to SRR0 */ \
188	mtspr SPRN_SRR0,r20; \
189	mfspr r20,SPRN_HSRR1; /* copy HSRR0 to SRR0 */ \
190	mtspr SPRN_SRR1,r20; \
191	mfspr r20,SPRN_SPRG1; /* restore r20 */ \
192	mtspr SPRN_SPRG1,r13; /* save r13 */ \
193	EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
194
195
196	#define MASKABLE_EXCEPTION_PSERIES(n, label) \
197	. = n; \
198	.globl label##_pSeries; \
199	label##_pSeries: \
200	HMT_MEDIUM; \
201	mtspr SPRN_SPRG1,r13; /* save r13 */ \
202	mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
203	std r9,PACA_EXGEN+EX_R9(r13); /* save r9, r10 */ \
204	std r10,PACA_EXGEN+EX_R10(r13); \
205	lbz r10,PACASOFTIRQEN(r13); \
206	mfcr r9; \
207	cmpwi r10,0; \
208	beq masked_interrupt; \
209	mfspr r10,SPRN_SPRG1; \
210	std r10,PACA_EXGEN+EX_R13(r13); \
211	std r11,PACA_EXGEN+EX_R11(r13); \
212	std r12,PACA_EXGEN+EX_R12(r13); \
213	clrrdi r12,r13,32; /* get high part of &label */ \
214	mfmsr r10; \
215	mfspr r11,SPRN_SRR0; /* save SRR0 */ \
216	LOAD_HANDLER(r12,label##_common) \
217	ori r10,r10,MSR_IR\|MSR_DR\|MSR_RI; \
218	mtspr SPRN_SRR0,r12; \
219	mfspr r12,SPRN_SRR1; /* and SRR1 */ \
220	mtspr SPRN_SRR1,r10; \
221	rfid; \
222	b . /* prevent speculative execution */
223
f9ff0f30 SR	224	#ifdef CONFIG_PPC_ISERIES
	225	#define DISABLE_INTS \
	226	li r11,0; \
	227	stb r11,PACASOFTIRQEN(r13); \
	228	BEGIN_FW_FTR_SECTION; \
	229	stb r11,PACAHARDIRQEN(r13); \
	230	END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES); \
945feb17	231	TRACE_DISABLE_INTS; \
f9ff0f30 SR	232	BEGIN_FW_FTR_SECTION; \
	233	mfmsr r10; \
	234	ori r10,r10,MSR_EE; \
	235	mtmsrd r10,1; \
	236	END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
f9ff0f30 SR	237	#else
	238	#define DISABLE_INTS \
	239	li r11,0; \
	240	stb r11,PACASOFTIRQEN(r13); \
945feb17 BH	241	stb r11,PACAHARDIRQEN(r13); \
945feb17 BH	242	TRACE_DISABLE_INTS
f9ff0f30 SR	243	#endif /* CONFIG_PPC_ISERIES */
	244
	245	#define ENABLE_INTS \
	246	ld r12,_MSR(r1); \
	247	mfmsr r11; \
	248	rlwimi r11,r12,0,MSR_EE; \
	249	mtmsrd r11,1
	250
	251	#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
	252	.align 7; \
	253	.globl label##_common; \
	254	label##_common: \
	255	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
	256	DISABLE_INTS; \
	257	bl .save_nvgprs; \
	258	addi r3,r1,STACK_FRAME_OVERHEAD; \
	259	bl hdlr; \
	260	b .ret_from_except
	261
	262	/*
	263	* Like STD_EXCEPTION_COMMON, but for exceptions that can occur
	264	* in the idle task and therefore need the special idle handling.
	265	*/
	266	#define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr) \
	267	.align 7; \
	268	.globl label##_common; \
	269	label##_common: \
	270	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
	271	FINISH_NAP; \
	272	DISABLE_INTS; \
	273	bl .save_nvgprs; \
	274	addi r3,r1,STACK_FRAME_OVERHEAD; \
	275	bl hdlr; \
	276	b .ret_from_except
	277
	278	#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
	279	.align 7; \
	280	.globl label##_common; \
	281	label##_common: \
	282	EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
	283	FINISH_NAP; \
	284	DISABLE_INTS; \
a416561b	285	BEGIN_FTR_SECTION \
f9ff0f30	286	bl .ppc64_runlatch_on; \
a416561b	287	END_FTR_SECTION_IFSET(CPU_FTR_CTRL) \
f9ff0f30 SR	288	addi r3,r1,STACK_FRAME_OVERHEAD; \
	289	bl hdlr; \
	290	b .ret_from_except_lite
	291
	292	/*
	293	* When the idle code in power4_idle puts the CPU into NAP mode,
	294	* it has to do so in a loop, and relies on the external interrupt
	295	* and decrementer interrupt entry code to get it out of the loop.
	296	* It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
	297	* to signal that it is in the loop and needs help to get out.
	298	*/
	299	#ifdef CONFIG_PPC_970_NAP
	300	#define FINISH_NAP \
	301	BEGIN_FTR_SECTION \
	302	clrrdi r11,r1,THREAD_SHIFT; \
	303	ld r9,TI_LOCAL_FLAGS(r11); \
	304	andi. r10,r9,_TLF_NAPPING; \
	305	bnel power4_fixup_nap; \
	306	END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
	307	#else
	308	#define FINISH_NAP
	309	#endif
	310
	311	#endif /* _ASM_POWERPC_EXCEPTION_H */