[linux-2.6-block.git] / arch / powerpc / include / asm / exception-64s.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef _ASM_POWERPC_EXCEPTION_H
#define _ASM_POWERPC_EXCEPTION_H
/*
 * Extracted from head_64.S
 *
 *  PowerPC version
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
 *  Adapted for Power Macintosh by Paul Mackerras.
 *  Low-level exception handlers and MMU support
 *  rewritten by Paul Mackerras.
 *    Copyright (C) 1996 Paul Mackerras.
 *
 *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
 *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
 *
 *  This file contains the low-level support and setup for the
 *  PowerPC-64 platform, including trap and interrupt dispatch.
 */
/*
 * The following macros define the code that appears as
 * the prologue to each of the exception handlers.  They
 * are split into two parts to allow a single kernel binary
 * to be used for pSeries and iSeries.
 *
 * We make as much of the exception code common between native
 * exception handlers (including pSeries LPAR) and iSeries LPAR
 * implementations as possible.
 */
#include <asm/feature-fixups.h>

/* PACA save area size in u64 units (exgen, exmc, etc) */
#define EX_SIZE		10

/* PACA save area offsets */
#define EX_R9		0
#define EX_R10		8
#define EX_R11		16
#define EX_R12		24
#define EX_R13		32
#define EX_DAR		40
#define EX_DSISR	48
#define EX_CCR		52
#define EX_CFAR		56
#define EX_PPR		64
#define EX_CTR		72

/*
 * maximum recursive depth of MCE exceptions
 */
#define MAX_MCE_DEPTH	4

#ifdef __ASSEMBLY__

#define STF_ENTRY_BARRIER_SLOT						\
	STF_ENTRY_BARRIER_FIXUP_SECTION;				\
	nop;								\
	nop;								\
	nop

#define STF_EXIT_BARRIER_SLOT						\
	STF_EXIT_BARRIER_FIXUP_SECTION;					\
	nop;								\
	nop;								\
	nop;								\
	nop;								\
	nop;								\
	nop

#define ENTRY_FLUSH_SLOT						\
	ENTRY_FLUSH_FIXUP_SECTION;					\
	nop;								\
	nop;								\
	nop;

#define SCV_ENTRY_FLUSH_SLOT						\
	SCV_ENTRY_FLUSH_FIXUP_SECTION;					\
	nop;								\
	nop;								\
	nop;

/*
 * r10 must be free to use, r13 must be paca
 */
#define INTERRUPT_TO_KERNEL						\
	STF_ENTRY_BARRIER_SLOT;						\
	ENTRY_FLUSH_SLOT

/*
 * r10, ctr must be free to use, r13 must be paca
 */
#define SCV_INTERRUPT_TO_KERNEL						\
	STF_ENTRY_BARRIER_SLOT;						\
	SCV_ENTRY_FLUSH_SLOT

/*
 * Macros for annotating the expected destination of (h)rfid
 *
 * The nop instructions allow us to insert one or more instructions to flush the
 * L1-D cache when returning to userspace or a guest.
 *
 * powerpc relies on return from interrupt/syscall being context synchronising
 * (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE
 * without additional synchronisation instructions.
 *
 * soft-masked interrupt replay does not include a context-synchronising rfid,
 * but those always return to kernel, the sync is only required when returning
 * to user.
 */
#define RFI_FLUSH_SLOT							\
	RFI_FLUSH_FIXUP_SECTION;					\
	nop;								\
	nop;								\
	nop

#define RFI_TO_KERNEL							\
	rfid

#define RFI_TO_USER							\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	rfid;								\
	b	rfi_flush_fallback

#define RFI_TO_USER_OR_KERNEL						\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	rfid;								\
	b	rfi_flush_fallback

#define RFI_TO_GUEST							\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	rfid;								\
	b	rfi_flush_fallback

#define HRFI_TO_KERNEL							\
	hrfid

#define HRFI_TO_USER							\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	hrfid;								\
	b	hrfi_flush_fallback

#define HRFI_TO_USER_OR_KERNEL						\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	hrfid;								\
	b	hrfi_flush_fallback

#define HRFI_TO_GUEST							\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	hrfid;								\
	b	hrfi_flush_fallback

#define HRFI_TO_UNKNOWN							\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	hrfid;								\
	b	hrfi_flush_fallback

#define RFSCV_TO_USER							\
	STF_EXIT_BARRIER_SLOT;						\
	RFI_FLUSH_SLOT;							\
	RFSCV;								\
	b	rfscv_flush_fallback

#else /* __ASSEMBLY__ */
/* Prototype for function defined in exceptions-64s.S */
void do_uaccess_flush(void);
#endif /* __ASSEMBLY__ */

#endif	/* _ASM_POWERPC_EXCEPTION_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
f9ff0f30 SR	2	#ifndef _ASM_POWERPC_EXCEPTION_H
	3	#define _ASM_POWERPC_EXCEPTION_H
	4	/*
	5	* Extracted from head_64.S
	6	*
	7	* PowerPC version
	8	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	9	*
	10	* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
	11	* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
	12	* Adapted for Power Macintosh by Paul Mackerras.
	13	* Low-level exception handlers and MMU support
	14	* rewritten by Paul Mackerras.
	15	* Copyright (C) 1996 Paul Mackerras.
	16	*
	17	* Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
	18	* Mike Corrigan {engebret\|bergner\|mikejc}@us.ibm.com
	19	*
	20	* This file contains the low-level support and setup for the
	21	* PowerPC-64 platform, including trap and interrupt dispatch.
f9ff0f30 SR	22	*/
	23	/*
	24	* The following macros define the code that appears as
	25	* the prologue to each of the exception handlers. They
	26	* are split into two parts to allow a single kernel binary
	27	* to be used for pSeries and iSeries.
	28	*
	29	* We make as much of the exception code common between native
	30	* exception handlers (including pSeries LPAR) and iSeries LPAR
	31	* implementations as possible.
	32	*/
2c86cd18	33	#include <asm/feature-fixups.h>
f9ff0f30	34
15820091	35	/* PACA save area size in u64 units (exgen, exmc, etc) */
15820091	36	#define EX_SIZE 10
dbeea1d6	37
04ece7b6 NP	38	/* PACA save area offsets */
	39	#define EX_R9 0
	40	#define EX_R10 8
	41	#define EX_R11 16
	42	#define EX_R12 24
	43	#define EX_R13 32
	44	#define EX_DAR 40
	45	#define EX_DSISR 48
	46	#define EX_CCR 52
	47	#define EX_CFAR 56
	48	#define EX_PPR 64
	49	#define EX_CTR 72
	50
ba41e1e1 BS	51	/*
	52	* maximum recursive depth of MCE exceptions
	53	*/
	54	#define MAX_MCE_DEPTH 4
	55
4508a74a	56	#ifdef __ASSEMBLY__
635942ae	57
a048a07d NP	58	#define STF_ENTRY_BARRIER_SLOT \
	59	STF_ENTRY_BARRIER_FIXUP_SECTION; \
	60	nop; \
	61	nop; \
	62	nop
	63
	64	#define STF_EXIT_BARRIER_SLOT \
	65	STF_EXIT_BARRIER_FIXUP_SECTION; \
	66	nop; \
	67	nop; \
	68	nop; \
	69	nop; \
	70	nop; \
	71	nop
	72
f7964378 NP	73	#define ENTRY_FLUSH_SLOT \
	74	ENTRY_FLUSH_FIXUP_SECTION; \
	75	nop; \
	76	nop; \
	77	nop;
	78
08685be7 NP	79	#define SCV_ENTRY_FLUSH_SLOT \
	80	SCV_ENTRY_FLUSH_FIXUP_SECTION; \
	81	nop; \
	82	nop; \
	83	nop;
	84
a048a07d NP	85	/*
	86	* r10 must be free to use, r13 must be paca
	87	*/
	88	#define INTERRUPT_TO_KERNEL \
f7964378 NP	89	STF_ENTRY_BARRIER_SLOT; \
f7964378 NP	90	ENTRY_FLUSH_SLOT
a048a07d	91
08685be7 NP	92	/*
	93	* r10, ctr must be free to use, r13 must be paca
	94	*/
	95	#define SCV_INTERRUPT_TO_KERNEL \
	96	STF_ENTRY_BARRIER_SLOT; \
	97	SCV_ENTRY_FLUSH_SLOT
	98
aa8a5e00 ME	99	/*
	100	* Macros for annotating the expected destination of (h)rfid
	101	*
	102	* The nop instructions allow us to insert one or more instructions to flush the
	103	* L1-D cache when returning to userspace or a guest.
2384b36f NP	104	*
	105	* powerpc relies on return from interrupt/syscall being context synchronising
	106	* (which hrfid, rfid, and rfscv are) to support ARCH_HAS_MEMBARRIER_SYNC_CORE
	107	* without additional synchronisation instructions.
	108	*
	109	* soft-masked interrupt replay does not include a context-synchronising rfid,
	110	* but those always return to kernel, the sync is only required when returning
	111	* to user.
aa8a5e00 ME	112	*/
	113	#define RFI_FLUSH_SLOT \
	114	RFI_FLUSH_FIXUP_SECTION; \
	115	nop; \
	116	nop; \
	117	nop
50e51c13 NP	118
	119	#define RFI_TO_KERNEL \
	120	rfid
	121
	122	#define RFI_TO_USER \
a048a07d	123	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	124	RFI_FLUSH_SLOT; \
	125	rfid; \
	126	b rfi_flush_fallback
50e51c13 NP	127
50e51c13 NP	128	#define RFI_TO_USER_OR_KERNEL \
a048a07d	129	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	130	RFI_FLUSH_SLOT; \
	131	rfid; \
	132	b rfi_flush_fallback
50e51c13 NP	133
50e51c13 NP	134	#define RFI_TO_GUEST \
a048a07d	135	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	136	RFI_FLUSH_SLOT; \
	137	rfid; \
	138	b rfi_flush_fallback
50e51c13 NP	139
	140	#define HRFI_TO_KERNEL \
	141	hrfid
	142
	143	#define HRFI_TO_USER \
a048a07d	144	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	145	RFI_FLUSH_SLOT; \
	146	hrfid; \
	147	b hrfi_flush_fallback
50e51c13 NP	148
50e51c13 NP	149	#define HRFI_TO_USER_OR_KERNEL \
a048a07d	150	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	151	RFI_FLUSH_SLOT; \
	152	hrfid; \
	153	b hrfi_flush_fallback
50e51c13 NP	154
50e51c13 NP	155	#define HRFI_TO_GUEST \
a048a07d	156	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	157	RFI_FLUSH_SLOT; \
	158	hrfid; \
	159	b hrfi_flush_fallback
50e51c13 NP	160
50e51c13 NP	161	#define HRFI_TO_UNKNOWN \
a048a07d	162	STF_EXIT_BARRIER_SLOT; \
aa8a5e00 ME	163	RFI_FLUSH_SLOT; \
	164	hrfid; \
	165	b hrfi_flush_fallback
50e51c13	166
7fa95f9a NP	167	#define RFSCV_TO_USER \
	168	STF_EXIT_BARRIER_SLOT; \
	169	RFI_FLUSH_SLOT; \
	170	RFSCV; \
	171	b rfscv_flush_fallback
	172
9a32a7e7 NP	173	#else /* __ASSEMBLY__ */
	174	/* Prototype for function defined in exceptions-64s.S */
	175	void do_uaccess_flush(void);
4508a74a	176	#endif /* __ASSEMBLY__ */
f9ff0f30 SR	177
f9ff0f30 SR	178	#endif /* _ASM_POWERPC_EXCEPTION_H */