powerpc/mm: Fixup tlbie vs mtpidr/mtlpidr ordering issue on POWER9
[linux-2.6-block.git] / arch / powerpc / include / asm / exception-64s.h
CommitLineData
2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
f9ff0f30
SR
2#ifndef _ASM_POWERPC_EXCEPTION_H
3#define _ASM_POWERPC_EXCEPTION_H
4/*
5 * Extracted from head_64.S
6 *
7 * PowerPC version
8 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 *
10 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
11 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
12 * Adapted for Power Macintosh by Paul Mackerras.
13 * Low-level exception handlers and MMU support
14 * rewritten by Paul Mackerras.
15 * Copyright (C) 1996 Paul Mackerras.
16 *
17 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
18 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
19 *
20 * This file contains the low-level support and setup for the
21 * PowerPC-64 platform, including trap and interrupt dispatch.
f9ff0f30
SR
22 */
23/*
24 * The following macros define the code that appears as
25 * the prologue to each of the exception handlers. They
26 * are split into two parts to allow a single kernel binary
27 * to be used for pSeries and iSeries.
28 *
29 * We make as much of the exception code common between native
30 * exception handlers (including pSeries LPAR) and iSeries LPAR
31 * implementations as possible.
32 */
2c86cd18 33#include <asm/feature-fixups.h>
f9ff0f30 34
15820091 35/* PACA save area size in u64 units (exgen, exmc, etc) */
8568f1e0 36#if defined(CONFIG_RELOCATABLE)
15820091 37#define EX_SIZE 10
8568f1e0 38#else
15820091 39#define EX_SIZE 9
8568f1e0 40#endif
dbeea1d6 41
ba41e1e1
BS
42/*
43 * maximum recursive depth of MCE exceptions
44 */
45#define MAX_MCE_DEPTH 4
46
4508a74a 47#ifdef __ASSEMBLY__
635942ae 48
a048a07d
NP
49#define STF_ENTRY_BARRIER_SLOT \
50 STF_ENTRY_BARRIER_FIXUP_SECTION; \
51 nop; \
52 nop; \
53 nop
54
55#define STF_EXIT_BARRIER_SLOT \
56 STF_EXIT_BARRIER_FIXUP_SECTION; \
57 nop; \
58 nop; \
59 nop; \
60 nop; \
61 nop; \
62 nop
63
64/*
65 * r10 must be free to use, r13 must be paca
66 */
67#define INTERRUPT_TO_KERNEL \
68 STF_ENTRY_BARRIER_SLOT
69
aa8a5e00
ME
70/*
71 * Macros for annotating the expected destination of (h)rfid
72 *
73 * The nop instructions allow us to insert one or more instructions to flush the
74 * L1-D cache when returning to userspace or a guest.
75 */
76#define RFI_FLUSH_SLOT \
77 RFI_FLUSH_FIXUP_SECTION; \
78 nop; \
79 nop; \
80 nop
50e51c13
NP
81
82#define RFI_TO_KERNEL \
83 rfid
84
85#define RFI_TO_USER \
a048a07d 86 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
87 RFI_FLUSH_SLOT; \
88 rfid; \
89 b rfi_flush_fallback
50e51c13
NP
90
91#define RFI_TO_USER_OR_KERNEL \
a048a07d 92 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
93 RFI_FLUSH_SLOT; \
94 rfid; \
95 b rfi_flush_fallback
50e51c13
NP
96
97#define RFI_TO_GUEST \
a048a07d 98 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
99 RFI_FLUSH_SLOT; \
100 rfid; \
101 b rfi_flush_fallback
50e51c13
NP
102
103#define HRFI_TO_KERNEL \
104 hrfid
105
106#define HRFI_TO_USER \
a048a07d 107 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
108 RFI_FLUSH_SLOT; \
109 hrfid; \
110 b hrfi_flush_fallback
50e51c13
NP
111
112#define HRFI_TO_USER_OR_KERNEL \
a048a07d 113 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
114 RFI_FLUSH_SLOT; \
115 hrfid; \
116 b hrfi_flush_fallback
50e51c13
NP
117
118#define HRFI_TO_GUEST \
a048a07d 119 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
120 RFI_FLUSH_SLOT; \
121 hrfid; \
122 b hrfi_flush_fallback
50e51c13
NP
123
124#define HRFI_TO_UNKNOWN \
a048a07d 125 STF_EXIT_BARRIER_SLOT; \
aa8a5e00
ME
126 RFI_FLUSH_SLOT; \
127 hrfid; \
128 b hrfi_flush_fallback
50e51c13 129
4508a74a 130#endif /* __ASSEMBLY__ */
f9ff0f30
SR
131
132#endif /* _ASM_POWERPC_EXCEPTION_H */