[linux-2.6-block.git] / arch / powerpc / include / asm / elf.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * ELF register definitions..
 */
#ifndef _ASM_POWERPC_ELF_H
#define _ASM_POWERPC_ELF_H

#include <linux/sched.h>	/* for task_struct */
#include <asm/page.h>
#include <asm/string.h>
#include <uapi/asm/elf.h>

/*
 * This is used to ensure we don't load something for the wrong architecture.
 */
#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
#define compat_elf_check_arch(x)	((x)->e_machine == EM_PPC)

#define CORE_DUMP_USE_REGSET
#define ELF_EXEC_PAGESIZE	PAGE_SIZE

/*
 * This is the base location for PIE (ET_DYN with INTERP) loads. On
 * 64-bit, this is raised to 4GB to leave the entire 32-bit address
 * space open for things that want to use the area for 32-bit pointers.
 */
#define ELF_ET_DYN_BASE		(is_32bit_task() ? 0x000400000UL : \
						   0x100000000UL)

#define ELF_CORE_EFLAGS (is_elf2_task() ? 2 : 0)

/*
 * Our registers are always unsigned longs, whether we're a 32 bit
 * process or 64 bit, on either a 64 bit or 32 bit kernel.
 *
 * This macro relies on elf_regs[i] having the right type to truncate to,
 * either u32 or u64.  It defines the body of the elf_core_copy_regs
 * function, either the native one with elf_gregset_t elf_regs or
 * the 32-bit one with elf_gregset_t32 elf_regs.
 */
#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
	int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
			   (size_t)ELF_NGREG);			  \
	for (i = 0; i < nregs; i++) \
		elf_regs[i] = ((unsigned long *) regs)[i]; \
	memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))

/* Common routine for both 32-bit and 64-bit native processes */
static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
					  struct pt_regs *regs)
{
	PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
}
#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);

typedef elf_vrregset_t elf_fpxregset_t;

/* ELF_HWCAP yields a mask that user programs can use to figure out what
   instruction set this cpu supports.  This could be done in userspace,
   but it's not easy, and we've already done it here.  */
# define ELF_HWCAP	(cur_cpu_spec->cpu_user_features)
# define ELF_HWCAP2	(cur_cpu_spec->cpu_user_features2)

/* This yields a string that ld.so will use to load implementation
   specific libraries for optimization.  This is more specific in
   intent than poking at uname or /proc/cpuinfo.  */

#define ELF_PLATFORM	(cur_cpu_spec->platform)

/* While ELF_PLATFORM indicates the ISA supported by the platform, it
 * may not accurately reflect the underlying behavior of the hardware
 * (as in the case of running in Power5+ compatibility mode on a
 * Power6 machine).  ELF_BASE_PLATFORM allows ld.so to load libraries
 * that are tuned for the real hardware.
 */
#define ELF_BASE_PLATFORM (powerpc_base_platform)

#ifdef __powerpc64__
# define ELF_PLAT_INIT(_r, load_addr)	do {	\
	_r->gpr[2] = load_addr; 		\
} while (0)
#endif /* __powerpc64__ */

#ifdef __powerpc64__
# define SET_PERSONALITY(ex)					\
do {								\
	if (((ex).e_flags & 0x3) == 2)				\
		set_thread_flag(TIF_ELF2ABI);			\
	else							\
		clear_thread_flag(TIF_ELF2ABI);			\
	if ((ex).e_ident[EI_CLASS] == ELFCLASS32)		\
		set_thread_flag(TIF_32BIT);			\
	else							\
		clear_thread_flag(TIF_32BIT);			\
	if (personality(current->personality) != PER_LINUX32)	\
		set_personality(PER_LINUX |			\
			(current->personality & (~PER_MASK)));	\
} while (0)
/*
 * An executable for which elf_read_implies_exec() returns TRUE will
 * have the READ_IMPLIES_EXEC personality flag set automatically. This
 * is only required to work around bugs in old 32bit toolchains. Since
 * the 64bit ABI has never had these issues dont enable the workaround
 * even if we have an executable stack.
 */
# define elf_read_implies_exec(ex, exec_stk) (is_32bit_task() ? \
		(exec_stk == EXSTACK_DEFAULT) : 0)
#else 
# define elf_read_implies_exec(ex, exec_stk) (exec_stk == EXSTACK_DEFAULT)
#endif /* __powerpc64__ */

extern int dcache_bsize;
extern int icache_bsize;
extern int ucache_bsize;

/* vDSO has arch_setup_additional_pages */
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
struct linux_binprm;
extern int arch_setup_additional_pages(struct linux_binprm *bprm,
				       int uses_interp);
#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b)

/* 1GB for 64bit, 8MB for 32bit */
#define STACK_RND_MASK (is_32bit_task() ? \
	(0x7ff >> (PAGE_SHIFT - 12)) : \
	(0x3ffff >> (PAGE_SHIFT - 12)))

#ifdef CONFIG_SPU_BASE
/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
#define NT_SPU		1

#define ARCH_HAVE_EXTRA_ELF_NOTES

#endif /* CONFIG_SPU_BASE */

#ifdef CONFIG_PPC64

#define get_cache_geometry(level) \
	(ppc64_caches.level.assoc << 16 | ppc64_caches.level.line_size)

#define ARCH_DLINFO_CACHE_GEOMETRY					\
	NEW_AUX_ENT(AT_L1I_CACHESIZE, ppc64_caches.l1i.size);		\
	NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, get_cache_geometry(l1i));	\
	NEW_AUX_ENT(AT_L1D_CACHESIZE, ppc64_caches.l1d.size);		\
	NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, get_cache_geometry(l1d));	\
	NEW_AUX_ENT(AT_L2_CACHESIZE, ppc64_caches.l2.size);		\
	NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, get_cache_geometry(l2));	\
	NEW_AUX_ENT(AT_L3_CACHESIZE, ppc64_caches.l3.size);		\
	NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, get_cache_geometry(l3))

#else
#define ARCH_DLINFO_CACHE_GEOMETRY
#endif

/*
 * The requirements here are:
 * - keep the final alignment of sp (sp & 0xf)
 * - make sure the 32-bit value at the first 16 byte aligned position of
 *   AUXV is greater than 16 for glibc compatibility.
 *   AT_IGNOREPPC is used for that.
 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
 *   even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
 * update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
 */
#define ARCH_DLINFO							\
do {									\
	/* Handle glibc compatibility. */				\
	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);			\
	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC);			\
	/* Cache size items */						\
	NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);			\
	NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);			\
	NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);			\
	VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base);	\
	ARCH_DLINFO_CACHE_GEOMETRY;					\
} while (0)

#endif /* _ASM_POWERPC_ELF_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
1da177e4 LT	3	* ELF register definitions..
1da177e4	4	*/
c3617f72 DH	5	#ifndef _ASM_POWERPC_ELF_H
c3617f72 DH	6	#define _ASM_POWERPC_ELF_H
1da177e4	7
c3617f72 DH	8	#include <linux/sched.h> /* for task_struct */
	9	#include <asm/page.h>
	10	#include <asm/string.h>
	11	#include <uapi/asm/elf.h>
1da177e4 LT	12
	13	/*
	14	* This is used to ensure we don't load something for the wrong architecture.
	15	*/
	16	#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
01e31dba	17	#define compat_elf_check_arch(x) ((x)->e_machine == EM_PPC)
1da177e4	18
81970387	19	#define CORE_DUMP_USE_REGSET
637a6ff6	20	#define ELF_EXEC_PAGESIZE PAGE_SIZE
1da177e4	21
47ebb09d KC	22	/*
	23	* This is the base location for PIE (ET_DYN with INTERP) loads. On
	24	* 64-bit, this is raised to 4GB to leave the entire 32-bit address
	25	* space open for things that want to use the area for 32-bit pointers.
	26	*/
	27	#define ELF_ET_DYN_BASE (is_32bit_task() ? 0x000400000UL : \
	28	0x100000000UL)
1da177e4	29
918d0355 RR	30	#define ELF_CORE_EFLAGS (is_elf2_task() ? 2 : 0)
918d0355 RR	31
5f149cf0 RM	32	/*
	33	* Our registers are always unsigned longs, whether we're a 32 bit
	34	* process or 64 bit, on either a 64 bit or 32 bit kernel.
	35	*
	36	* This macro relies on elf_regs[i] having the right type to truncate to,
	37	* either u32 or u64. It defines the body of the elf_core_copy_regs
	38	* function, either the native one with elf_gregset_t elf_regs or
	39	* the 32-bit one with elf_gregset_t32 elf_regs.
	40	*/
	41	#define PPC_ELF_CORE_COPY_REGS(elf_regs, regs) \
	42	int i, nregs = min(sizeof(*regs) / sizeof(unsigned long), \
	43	(size_t)ELF_NGREG); \
	44	for (i = 0; i < nregs; i++) \
	45	elf_regs[i] = ((unsigned long *) regs)[i]; \
	46	memset(&elf_regs[i], 0, (ELF_NGREG - i) * sizeof(elf_regs[0]))
	47
	48	/* Common routine for both 32-bit and 64-bit native processes */
a99eb2ef	49	static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
5f149cf0	50	struct pt_regs *regs)
1da177e4	51	{
5f149cf0	52	PPC_ELF_CORE_COPY_REGS(elf_regs, regs);
1da177e4	53	}
a99eb2ef	54	#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
1da177e4	55
1f7d6668 MN	56	typedef elf_vrregset_t elf_fpxregset_t;
1f7d6668 MN	57
a99eb2ef	58	/* ELF_HWCAP yields a mask that user programs can use to figure out what
1da177e4 LT	59	instruction set this cpu supports. This could be done in userspace,
1da177e4 LT	60	but it's not easy, and we've already done it here. */
a99eb2ef	61	# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
2171364d	62	# define ELF_HWCAP2 (cur_cpu_spec->cpu_user_features2)
1da177e4 LT	63
	64	/* This yields a string that ld.so will use to load implementation
	65	specific libraries for optimization. This is more specific in
80f15dc7	66	intent than poking at uname or /proc/cpuinfo. */
1da177e4	67
80f15dc7	68	#define ELF_PLATFORM (cur_cpu_spec->platform)
9115d134 NL	69
	70	/* While ELF_PLATFORM indicates the ISA supported by the platform, it
	71	* may not accurately reflect the underlying behavior of the hardware
	72	* (as in the case of running in Power5+ compatibility mode on a
	73	* Power6 machine). ELF_BASE_PLATFORM allows ld.so to load libraries
	74	* that are tuned for the real hardware.
	75	*/
	76	#define ELF_BASE_PLATFORM (powerpc_base_platform)
1da177e4	77
80f15dc7 PM	78	#ifdef __powerpc64__
	79	# define ELF_PLAT_INIT(_r, load_addr) do { \
	80	_r->gpr[2] = load_addr; \
	81	} while (0)
	82	#endif /* __powerpc64__ */
1da177e4	83
a99eb2ef	84	#ifdef __powerpc64__
0b592682	85	# define SET_PERSONALITY(ex) \
1da177e4	86	do { \
373c76d6 RR	87	if (((ex).e_flags & 0x3) == 2) \
373c76d6 RR	88	set_thread_flag(TIF_ELF2ABI); \
1efc5638 JB	89	else \
1efc5638 JB	90	clear_thread_flag(TIF_ELF2ABI); \
1da177e4	91	if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
94f28da8	92	set_thread_flag(TIF_32BIT); \
1da177e4	93	else \
94f28da8	94	clear_thread_flag(TIF_32BIT); \
ce10d979	95	if (personality(current->personality) != PER_LINUX32) \
a91a03ee EM	96	set_personality(PER_LINUX \| \
a91a03ee EM	97	(current->personality & (~PER_MASK))); \
1da177e4	98	} while (0)
1da177e4 LT	99	/*
1da177e4 LT	100	* An executable for which elf_read_implies_exec() returns TRUE will
a2f95a5a AB	101	* have the READ_IMPLIES_EXEC personality flag set automatically. This
	102	* is only required to work around bugs in old 32bit toolchains. Since
	103	* the 64bit ABI has never had these issues dont enable the workaround
	104	* even if we have an executable stack.
1da177e4	105	*/
cab175f9	106	# define elf_read_implies_exec(ex, exec_stk) (is_32bit_task() ? \
d89ebca2	107	(exec_stk == EXSTACK_DEFAULT) : 0)
a99eb2ef	108	#else
d89ebca2	109	# define elf_read_implies_exec(ex, exec_stk) (exec_stk == EXSTACK_DEFAULT)
a99eb2ef	110	#endif /* __powerpc64__ */
1da177e4	111
1da177e4 LT	112	extern int dcache_bsize;
	113	extern int icache_bsize;
	114	extern int ucache_bsize;
	115
a7f290da BH	116	/* vDSO has arch_setup_additional_pages */
a7f290da BH	117	#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
1da177e4	118	struct linux_binprm;
a7f290da	119	extern int arch_setup_additional_pages(struct linux_binprm *bprm,
fc5243d9	120	int uses_interp);
497888cf	121	#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b)
1da177e4	122
2dadb987 AB	123	/* 1GB for 64bit, 8MB for 32bit */
	124	#define STACK_RND_MASK (is_32bit_task() ? \
	125	(0x7ff >> (PAGE_SHIFT - 12)) : \
	126	(0x3ffff >> (PAGE_SHIFT - 12)))
	127
e055595d	128	#ifdef CONFIG_SPU_BASE
bf1ab978 DGM	129	/* Notes used in ET_CORE. Note name is "SPU/<fd>/<filename>". */
	130	#define NT_SPU 1
	131
bf1ab978	132	#define ARCH_HAVE_EXTRA_ELF_NOTES
e5501492 ME	133
e5501492 ME	134	#endif /* CONFIG_SPU_BASE */
bf1ab978	135
98a5f361 BH	136	#ifdef CONFIG_PPC64
	137
	138	#define get_cache_geometry(level) \
	139	(ppc64_caches.level.assoc << 16 \| ppc64_caches.level.line_size)
	140
	141	#define ARCH_DLINFO_CACHE_GEOMETRY \
	142	NEW_AUX_ENT(AT_L1I_CACHESIZE, ppc64_caches.l1i.size); \
	143	NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, get_cache_geometry(l1i)); \
9c7a0086 ME	144	NEW_AUX_ENT(AT_L1D_CACHESIZE, ppc64_caches.l1d.size); \
9c7a0086 ME	145	NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, get_cache_geometry(l1d)); \
98a5f361 BH	146	NEW_AUX_ENT(AT_L2_CACHESIZE, ppc64_caches.l2.size); \
	147	NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, get_cache_geometry(l2)); \
	148	NEW_AUX_ENT(AT_L3_CACHESIZE, ppc64_caches.l3.size); \
	149	NEW_AUX_ENT(AT_L3_CACHEGEOMETRY, get_cache_geometry(l3))
	150
	151	#else
	152	#define ARCH_DLINFO_CACHE_GEOMETRY
	153	#endif
	154
2a196e24 BH	155	/*
	156	* The requirements here are:
	157	* - keep the final alignment of sp (sp & 0xf)
	158	* - make sure the 32-bit value at the first 16 byte aligned position of
	159	* AUXV is greater than 16 for glibc compatibility.
	160	* AT_IGNOREPPC is used for that.
	161	* - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
	162	* even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
	163	* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes
	164	*/
	165	#define ARCH_DLINFO \
	166	do { \
	167	/* Handle glibc compatibility. */ \
	168	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
	169	NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
	170	/* Cache size items */ \
	171	NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
	172	NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
	173	NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
	174	VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base); \
98a5f361	175	ARCH_DLINFO_CACHE_GEOMETRY; \
2a196e24 BH	176	} while (0)
2a196e24 BH	177
a99eb2ef	178	#endif /* _ASM_POWERPC_ELF_H */