[linux-block.git] / arch / powerpc / include / asm / eeh.h

/*
 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
 * Copyright 2001-2012 IBM Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef _POWERPC_EEH_H
#define _POWERPC_EEH_H
#ifdef __KERNEL__

#include <linux/init.h>
#include <linux/list.h>
#include <linux/string.h>
#include <linux/time.h>

struct pci_dev;
struct pci_bus;
struct device_node;

#ifdef CONFIG_EEH

/*
 * The struct is used to trace PE related EEH functionality.
 * In theory, there will have one instance of the struct to
 * be created against particular PE. In nature, PEs corelate
 * to each other. the struct has to reflect that hierarchy in
 * order to easily pick up those affected PEs when one particular
 * PE has EEH errors.
 *
 * Also, one particular PE might be composed of PCI device, PCI
 * bus and its subordinate components. The struct also need ship
 * the information. Further more, one particular PE is only meaingful
 * in the corresponding PHB. Therefore, the root PEs should be created
 * against existing PHBs in on-to-one fashion.
 */
#define EEH_PE_INVALID	(1 << 0)	/* Invalid   */
#define EEH_PE_PHB	(1 << 1)	/* PHB PE    */
#define EEH_PE_DEVICE 	(1 << 2)	/* Device PE */
#define EEH_PE_BUS	(1 << 3)	/* Bus PE    */

#define EEH_PE_ISOLATED		(1 << 0)	/* Isolated PE		*/
#define EEH_PE_RECOVERING	(1 << 1)	/* Recovering PE	*/
#define EEH_PE_PHB_DEAD		(1 << 2)	/* Dead PHB		*/

#define EEH_PE_KEEP		(1 << 8)	/* Keep PE on hotplug	*/

struct eeh_pe {
	int type;			/* PE type: PHB/Bus/Device	*/
	int state;			/* PE EEH dependent mode	*/
	int config_addr;		/* Traditional PCI address	*/
	int addr;			/* PE configuration address	*/
	struct pci_controller *phb;	/* Associated PHB		*/
	struct pci_bus *bus;		/* Top PCI bus for bus PE	*/
	int check_count;		/* Times of ignored error	*/
	int freeze_count;		/* Times of froze up		*/
	struct timeval tstamp;		/* Time on first-time freeze	*/
	int false_positives;		/* Times of reported #ff's	*/
	struct eeh_pe *parent;		/* Parent PE			*/
	struct list_head child_list;	/* Link PE to the child list	*/
	struct list_head edevs;		/* Link list of EEH devices	*/
	struct list_head child;		/* Child PEs			*/
};

#define eeh_pe_for_each_dev(pe, edev, tmp) \
		list_for_each_entry_safe(edev, tmp, &pe->edevs, list)

/*
 * The struct is used to trace EEH state for the associated
 * PCI device node or PCI device. In future, it might
 * represent PE as well so that the EEH device to form
 * another tree except the currently existing tree of PCI
 * buses and PCI devices
 */
#define EEH_DEV_BRIDGE		(1 << 0)	/* PCI bridge		*/
#define EEH_DEV_ROOT_PORT	(1 << 1)	/* PCIe root port	*/
#define EEH_DEV_DS_PORT		(1 << 2)	/* Downstream port	*/
#define EEH_DEV_IRQ_DISABLED	(1 << 3)	/* Interrupt disabled	*/
#define EEH_DEV_DISCONNECTED	(1 << 4)	/* Removing from PE	*/

#define EEH_DEV_SYSFS		(1 << 8)	/* Sysfs created        */

struct eeh_dev {
	int mode;			/* EEH mode			*/
	int class_code;			/* Class code of the device	*/
	int config_addr;		/* Config address		*/
	int pe_config_addr;		/* PE config address		*/
	u32 config_space[16];		/* Saved PCI config space	*/
	u8 pcie_cap;			/* Saved PCIe capability	*/
	struct eeh_pe *pe;		/* Associated PE		*/
	struct list_head list;		/* Form link list in the PE	*/
	struct pci_controller *phb;	/* Associated PHB		*/
	struct device_node *dn;		/* Associated device node	*/
	struct pci_dev *pdev;		/* Associated PCI device	*/
	struct pci_bus *bus;		/* PCI bus for partial hotplug	*/
};

static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
{
	return edev ? edev->dn : NULL;
}

static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
{
	return edev ? edev->pdev : NULL;
}

/*
 * The struct is used to trace the registered EEH operation
 * callback functions. Actually, those operation callback
 * functions are heavily platform dependent. That means the
 * platform should register its own EEH operation callback
 * functions before any EEH further operations.
 */
#define EEH_OPT_DISABLE		0	/* EEH disable	*/
#define EEH_OPT_ENABLE		1	/* EEH enable	*/
#define EEH_OPT_THAW_MMIO	2	/* MMIO enable	*/
#define EEH_OPT_THAW_DMA	3	/* DMA enable	*/
#define EEH_STATE_UNAVAILABLE	(1 << 0)	/* State unavailable	*/
#define EEH_STATE_NOT_SUPPORT	(1 << 1)	/* EEH not supported	*/
#define EEH_STATE_RESET_ACTIVE	(1 << 2)	/* Active reset		*/
#define EEH_STATE_MMIO_ACTIVE	(1 << 3)	/* Active MMIO		*/
#define EEH_STATE_DMA_ACTIVE	(1 << 4)	/* Active DMA		*/
#define EEH_STATE_MMIO_ENABLED	(1 << 5)	/* MMIO enabled		*/
#define EEH_STATE_DMA_ENABLED	(1 << 6)	/* DMA enabled		*/
#define EEH_RESET_DEACTIVATE	0	/* Deactivate the PE reset	*/
#define EEH_RESET_HOT		1	/* Hot reset			*/
#define EEH_RESET_FUNDAMENTAL	3	/* Fundamental reset		*/
#define EEH_LOG_TEMP		1	/* EEH temporary error log	*/
#define EEH_LOG_PERM		2	/* EEH permanent error log	*/

struct eeh_ops {
	char *name;
	int (*init)(void);
	int (*post_init)(void);
	void* (*of_probe)(struct device_node *dn, void *flag);
	int (*dev_probe)(struct pci_dev *dev, void *flag);
	int (*set_option)(struct eeh_pe *pe, int option);
	int (*get_pe_addr)(struct eeh_pe *pe);
	int (*get_state)(struct eeh_pe *pe, int *state);
	int (*reset)(struct eeh_pe *pe, int option);
	int (*wait_state)(struct eeh_pe *pe, int max_wait);
	int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
	int (*configure_bridge)(struct eeh_pe *pe);
	int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
	int (*write_config)(struct device_node *dn, int where, int size, u32 val);
	int (*next_error)(struct eeh_pe **pe);
};

extern struct eeh_ops *eeh_ops;
extern int eeh_subsystem_enabled;
extern raw_spinlock_t confirm_error_lock;
extern int eeh_probe_mode;

#define EEH_PROBE_MODE_DEV	(1<<0)	/* From PCI device	*/
#define EEH_PROBE_MODE_DEVTREE	(1<<1)	/* From device tree	*/

static inline void eeh_probe_mode_set(int flag)
{
	eeh_probe_mode = flag;
}

static inline int eeh_probe_mode_devtree(void)
{
	return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
}

static inline int eeh_probe_mode_dev(void)
{
	return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
}

static inline void eeh_serialize_lock(unsigned long *flags)
{
	raw_spin_lock_irqsave(&confirm_error_lock, *flags);
}

static inline void eeh_serialize_unlock(unsigned long flags)
{
	raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
}

/*
 * Max number of EEH freezes allowed before we consider the device
 * to be permanently disabled.
 */
#define EEH_MAX_ALLOWED_FREEZES 5

typedef void *(*eeh_traverse_func)(void *data, void *flag);
int eeh_phb_pe_create(struct pci_controller *phb);
struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
int eeh_add_to_parent_pe(struct eeh_dev *edev);
int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
void eeh_pe_update_time_stamp(struct eeh_pe *pe);
void *eeh_pe_traverse(struct eeh_pe *root,
		eeh_traverse_func fn, void *flag);
void *eeh_pe_dev_traverse(struct eeh_pe *root,
		eeh_traverse_func fn, void *flag);
void eeh_pe_restore_bars(struct eeh_pe *pe);
struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);

void *eeh_dev_init(struct device_node *dn, void *data);
void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
int eeh_init(void);
int __init eeh_ops_register(struct eeh_ops *ops);
int __exit eeh_ops_unregister(const char *name);
unsigned long eeh_check_failure(const volatile void __iomem *token,
				unsigned long val);
int eeh_dev_check_failure(struct eeh_dev *edev);
void eeh_addr_cache_build(void);
void eeh_add_device_early(struct device_node *);
void eeh_add_device_tree_early(struct device_node *);
void eeh_add_device_late(struct pci_dev *);
void eeh_add_device_tree_late(struct pci_bus *);
void eeh_add_sysfs_files(struct pci_bus *);
void eeh_remove_device(struct pci_dev *);

/**
 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 *
 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 * which does further tests out of line.
 */
#define EEH_POSSIBLE_ERROR(val, type)	((val) == (type)~0 && eeh_subsystem_enabled)

/*
 * Reads from a device which has been isolated by EEH will return
 * all 1s.  This macro gives an all-1s value of the given size (in
 * bytes: 1, 2, or 4) for comparing with the result of a read.
 */
#define EEH_IO_ERROR_VALUE(size)	(~0U >> ((4 - (size)) * 8))

#else /* !CONFIG_EEH */

static inline int eeh_init(void)
{
	return 0;
}

static inline void *eeh_dev_init(struct device_node *dn, void *data)
{
	return NULL;
}

static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }

static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
{
	return val;
}

#define eeh_dev_check_failure(x) (0)

static inline void eeh_addr_cache_build(void) { }

static inline void eeh_add_device_early(struct device_node *dn) { }

static inline void eeh_add_device_tree_early(struct device_node *dn) { }

static inline void eeh_add_device_late(struct pci_dev *dev) { }

static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }

static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }

static inline void eeh_remove_device(struct pci_dev *dev) { }

#define EEH_POSSIBLE_ERROR(val, type) (0)
#define EEH_IO_ERROR_VALUE(size) (-1UL)
#endif /* CONFIG_EEH */

#ifdef CONFIG_PPC64
/*
 * MMIO read/write operations with EEH support.
 */
static inline u8 eeh_readb(const volatile void __iomem *addr)
{
	u8 val = in_8(addr);
	if (EEH_POSSIBLE_ERROR(val, u8))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u16 eeh_readw(const volatile void __iomem *addr)
{
	u16 val = in_le16(addr);
	if (EEH_POSSIBLE_ERROR(val, u16))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u32 eeh_readl(const volatile void __iomem *addr)
{
	u32 val = in_le32(addr);
	if (EEH_POSSIBLE_ERROR(val, u32))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u64 eeh_readq(const volatile void __iomem *addr)
{
	u64 val = in_le64(addr);
	if (EEH_POSSIBLE_ERROR(val, u64))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u16 eeh_readw_be(const volatile void __iomem *addr)
{
	u16 val = in_be16(addr);
	if (EEH_POSSIBLE_ERROR(val, u16))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u32 eeh_readl_be(const volatile void __iomem *addr)
{
	u32 val = in_be32(addr);
	if (EEH_POSSIBLE_ERROR(val, u32))
		return eeh_check_failure(addr, val);
	return val;
}

static inline u64 eeh_readq_be(const volatile void __iomem *addr)
{
	u64 val = in_be64(addr);
	if (EEH_POSSIBLE_ERROR(val, u64))
		return eeh_check_failure(addr, val);
	return val;
}

static inline void eeh_memcpy_fromio(void *dest, const
				     volatile void __iomem *src,
				     unsigned long n)
{
	_memcpy_fromio(dest, src, n);

	/* Look for ffff's here at dest[n].  Assume that at least 4 bytes
	 * were copied. Check all four bytes.
	 */
	if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
		eeh_check_failure(src, *((u32 *)(dest + n - 4)));
}

/* in-string eeh macros */
static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
			      int ns)
{
	_insb(addr, buf, ns);
	if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
		eeh_check_failure(addr, *(u8*)buf);
}

static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
			      int ns)
{
	_insw(addr, buf, ns);
	if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
		eeh_check_failure(addr, *(u16*)buf);
}

static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
			      int nl)
{
	_insl(addr, buf, nl);
	if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
		eeh_check_failure(addr, *(u32*)buf);
}

#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _POWERPC_EEH_H */
Commit	Line	Data
172ca926	1	/*
1da177e4	2	* Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
cb3bc9d0	3	* Copyright 2001-2012 IBM Corporation.
1da177e4 LT	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
172ca926	9	*
1da177e4 LT	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
172ca926	14	*
1da177e4 LT	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
8b8da358 BH	20	#ifndef _POWERPC_EEH_H
8b8da358 BH	21	#define _POWERPC_EEH_H
88ced031	22	#ifdef __KERNEL__
1da177e4	23
1da177e4 LT	24	#include <linux/init.h>
	25	#include <linux/list.h>
	26	#include <linux/string.h>
5a71978e	27	#include <linux/time.h>
1da177e4 LT	28
1da177e4 LT	29	struct pci_dev;
827c1a6c	30	struct pci_bus;
1da177e4	31	struct device_node;
1da177e4 LT	32
	33	#ifdef CONFIG_EEH
	34
968f968f GS	35	/*
	36	* The struct is used to trace PE related EEH functionality.
	37	* In theory, there will have one instance of the struct to
	38	* be created against particular PE. In nature, PEs corelate
	39	* to each other. the struct has to reflect that hierarchy in
	40	* order to easily pick up those affected PEs when one particular
	41	* PE has EEH errors.
	42	*
	43	* Also, one particular PE might be composed of PCI device, PCI
	44	* bus and its subordinate components. The struct also need ship
	45	* the information. Further more, one particular PE is only meaingful
	46	* in the corresponding PHB. Therefore, the root PEs should be created
	47	* against existing PHBs in on-to-one fashion.
	48	*/
5efc3ad7 GS	49	#define EEH_PE_INVALID (1 << 0) /* Invalid */
	50	#define EEH_PE_PHB (1 << 1) /* PHB PE */
	51	#define EEH_PE_DEVICE (1 << 2) /* Device PE */
	52	#define EEH_PE_BUS (1 << 3) /* Bus PE */
968f968f GS	53
	54	#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
	55	#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
8a6b1bc7	56	#define EEH_PE_PHB_DEAD (1 << 2) /* Dead PHB */
968f968f	57
807a827d GS	58	#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
807a827d GS	59
968f968f GS	60	struct eeh_pe {
	61	int type; /* PE type: PHB/Bus/Device */
	62	int state; /* PE EEH dependent mode */
	63	int config_addr; /* Traditional PCI address */
	64	int addr; /* PE configuration address */
	65	struct pci_controller phb; / Associated PHB */
8cdb2833	66	struct pci_bus bus; / Top PCI bus for bus PE */
968f968f GS	67	int check_count; /* Times of ignored error */
968f968f GS	68	int freeze_count; /* Times of froze up */
5a71978e	69	struct timeval tstamp; /* Time on first-time freeze */
968f968f GS	70	int false_positives; /* Times of reported #ff's */
	71	struct eeh_pe parent; / Parent PE */
	72	struct list_head child_list; /* Link PE to the child list */
	73	struct list_head edevs; /* Link list of EEH devices */
	74	struct list_head child; /* Child PEs */
	75	};
	76
9feed42e GS	77	#define eeh_pe_for_each_dev(pe, edev, tmp) \
9feed42e GS	78	list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
5b663529	79
eb740b5f GS	80	/*
	81	* The struct is used to trace EEH state for the associated
	82	* PCI device node or PCI device. In future, it might
	83	* represent PE as well so that the EEH device to form
	84	* another tree except the currently existing tree of PCI
	85	* buses and PCI devices
	86	*/
4b83bd45 GS	87	#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
	88	#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
	89	#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
	90	#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
	91	#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
eb740b5f	92
ab55d218 GS	93	#define EEH_DEV_SYSFS (1 << 8) /* Sysfs created */
ab55d218 GS	94
eb740b5f GS	95	struct eeh_dev {
	96	int mode; /* EEH mode */
	97	int class_code; /* Class code of the device */
	98	int config_addr; /* Config address */
	99	int pe_config_addr; /* PE config address */
eb740b5f	100	u32 config_space[16]; /* Saved PCI config space */
4b83bd45	101	u8 pcie_cap; /* Saved PCIe capability */
968f968f GS	102	struct eeh_pe pe; / Associated PE */
968f968f GS	103	struct list_head list; /* Form link list in the PE */
eb740b5f GS	104	struct pci_controller phb; / Associated PHB */
	105	struct device_node dn; / Associated device node */
	106	struct pci_dev pdev; / Associated PCI device */
f5c57710	107	struct pci_bus bus; / PCI bus for partial hotplug */
eb740b5f GS	108	};
	109
	110	static inline struct device_node eeh_dev_to_of_node(struct eeh_dev edev)
	111	{
2d5c1216	112	return edev ? edev->dn : NULL;
eb740b5f GS	113	}
	114
	115	static inline struct pci_dev eeh_dev_to_pci_dev(struct eeh_dev edev)
	116	{
2d5c1216	117	return edev ? edev->pdev : NULL;
eb740b5f GS	118	}
eb740b5f GS	119
aa1e6374 GS	120	/*
	121	* The struct is used to trace the registered EEH operation
	122	* callback functions. Actually, those operation callback
	123	* functions are heavily platform dependent. That means the
	124	* platform should register its own EEH operation callback
	125	* functions before any EEH further operations.
	126	*/
8fb8f709 GS	127	#define EEH_OPT_DISABLE 0 /* EEH disable */
	128	#define EEH_OPT_ENABLE 1 /* EEH enable */
	129	#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
	130	#define EEH_OPT_THAW_DMA 3 /* DMA enable */
eb594a47 GS	131	#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
	132	#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
	133	#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
	134	#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
	135	#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
	136	#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
	137	#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
2652481f GS	138	#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
	139	#define EEH_RESET_HOT 1 /* Hot reset */
	140	#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
8d633291 GS	141	#define EEH_LOG_TEMP 1 /* EEH temporary error log */
8d633291 GS	142	#define EEH_LOG_PERM 2 /* EEH permanent error log */
eb594a47	143
aa1e6374 GS	144	struct eeh_ops {
	145	char *name;
	146	int (*init)(void);
21fd21f5	147	int (*post_init)(void);
d7bb8862	148	void* (of_probe)(struct device_node dn, void *flag);
51fb5f56	149	int (dev_probe)(struct pci_dev dev, void *flag);
371a395d GS	150	int (set_option)(struct eeh_pe pe, int option);
	151	int (get_pe_addr)(struct eeh_pe pe);
	152	int (get_state)(struct eeh_pe pe, int *state);
	153	int (reset)(struct eeh_pe pe, int option);
	154	int (wait_state)(struct eeh_pe pe, int max_wait);
	155	int (get_log)(struct eeh_pe pe, int severity, char *drv_log, unsigned long len);
	156	int (configure_bridge)(struct eeh_pe pe);
3780444c GS	157	int (read_config)(struct device_node dn, int where, int size, u32 *val);
3780444c GS	158	int (write_config)(struct device_node dn, int where, int size, u32 val);
8a6b1bc7	159	int (next_error)(struct eeh_pe *pe);
aa1e6374 GS	160	};
	161
	162	extern struct eeh_ops *eeh_ops;
1e28a7dd	163	extern int eeh_subsystem_enabled;
4907581d	164	extern raw_spinlock_t confirm_error_lock;
d7bb8862 GS	165	extern int eeh_probe_mode;
	166
	167	#define EEH_PROBE_MODE_DEV (1<<0) /* From PCI device */
	168	#define EEH_PROBE_MODE_DEVTREE (1<<1) /* From device tree */
	169
	170	static inline void eeh_probe_mode_set(int flag)
	171	{
	172	eeh_probe_mode = flag;
	173	}
	174
	175	static inline int eeh_probe_mode_devtree(void)
	176	{
	177	return (eeh_probe_mode == EEH_PROBE_MODE_DEVTREE);
	178	}
	179
	180	static inline int eeh_probe_mode_dev(void)
	181	{
	182	return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
	183	}
646a8499	184
4907581d GS	185	static inline void eeh_serialize_lock(unsigned long *flags)
	186	{
	187	raw_spin_lock_irqsave(&confirm_error_lock, *flags);
	188	}
	189
	190	static inline void eeh_serialize_unlock(unsigned long flags)
	191	{
	192	raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
	193	}
	194
cb3bc9d0 GS	195	/*
	196	* Max number of EEH freezes allowed before we consider the device
	197	* to be permanently disabled.
	198	*/
172ca926 LV	199	#define EEH_MAX_ALLOWED_FREEZES 5
172ca926 LV	200
22f4ab12	201	typedef void (eeh_traverse_func)(void data, void flag);
cad5cef6	202	int eeh_phb_pe_create(struct pci_controller *phb);
9ff67433	203	struct eeh_pe eeh_phb_pe_get(struct pci_controller phb);
01566808	204	struct eeh_pe eeh_pe_get(struct eeh_dev edev);
9b84348c	205	int eeh_add_to_parent_pe(struct eeh_dev *edev);
807a827d	206	int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
5a71978e	207	void eeh_pe_update_time_stamp(struct eeh_pe *pe);
f5c57710 GS	208	void eeh_pe_traverse(struct eeh_pe root,
f5c57710 GS	209	eeh_traverse_func fn, void *flag);
9e6d2cf6 GS	210	void eeh_pe_dev_traverse(struct eeh_pe root,
	211	eeh_traverse_func fn, void *flag);
	212	void eeh_pe_restore_bars(struct eeh_pe *pe);
9b3c76f0	213	struct pci_bus eeh_pe_bus_get(struct eeh_pe pe);
55037d17	214
cad5cef6 GKH	215	void eeh_dev_init(struct device_node dn, void *data);
cad5cef6 GKH	216	void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
eeb6361f	217	int eeh_init(void);
aa1e6374 GS	218	int __init eeh_ops_register(struct eeh_ops *ops);
aa1e6374 GS	219	int __exit eeh_ops_unregister(const char *name);
1da177e4 LT	220	unsigned long eeh_check_failure(const volatile void __iomem *token,
1da177e4 LT	221	unsigned long val);
f8f7d63f	222	int eeh_dev_check_failure(struct eeh_dev *edev);
eeb6361f	223	void eeh_addr_cache_build(void);
f2856491	224	void eeh_add_device_early(struct device_node *);
e2a296ee	225	void eeh_add_device_tree_early(struct device_node *);
f2856491	226	void eeh_add_device_late(struct pci_dev *);
827c1a6c	227	void eeh_add_device_tree_late(struct pci_bus *);
6a040ce7	228	void eeh_add_sysfs_files(struct pci_bus *);
807a827d	229	void eeh_remove_device(struct pci_dev *);
e2a296ee	230
1da177e4 LT	231	/**
	232	* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
	233	*
	234	* If this macro yields TRUE, the caller relays to eeh_check_failure()
	235	* which does further tests out of line.
	236	*/
1e28a7dd	237	#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
1da177e4 LT	238
	239	/*
	240	* Reads from a device which has been isolated by EEH will return
	241	* all 1s. This macro gives an all-1s value of the given size (in
	242	* bytes: 1, 2, or 4) for comparing with the result of a read.
	243	*/
	244	#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
	245
	246	#else /* !CONFIG_EEH */
eb740b5f	247
51fb5f56 GS	248	static inline int eeh_init(void)
	249	{
	250	return 0;
	251	}
	252
eb740b5f GS	253	static inline void eeh_dev_init(struct device_node dn, void *data)
	254	{
	255	return NULL;
	256	}
	257
	258	static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
	259
1da177e4 LT	260	static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
	261	{
	262	return val;
	263	}
	264
f8f7d63f	265	#define eeh_dev_check_failure(x) (0)
1da177e4	266
3ab96a02	267	static inline void eeh_addr_cache_build(void) { }
1da177e4	268
f2856491 GS	269	static inline void eeh_add_device_early(struct device_node *dn) { }
f2856491 GS	270
022930eb HM	271	static inline void eeh_add_device_tree_early(struct device_node *dn) { }
022930eb HM	272
f2856491 GS	273	static inline void eeh_add_device_late(struct pci_dev *dev) { }
f2856491 GS	274
827c1a6c JR	275	static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
827c1a6c JR	276
6a040ce7 TLSC	277	static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
6a040ce7 TLSC	278
807a827d	279	static inline void eeh_remove_device(struct pci_dev *dev) { }
646a8499	280
1da177e4 LT	281	#define EEH_POSSIBLE_ERROR(val, type) (0)
	282	#define EEH_IO_ERROR_VALUE(size) (-1UL)
	283	#endif /* CONFIG_EEH */
	284
8b8da358	285	#ifdef CONFIG_PPC64
172ca926	286	/*
1da177e4 LT	287	* MMIO read/write operations with EEH support.
	288	*/
	289	static inline u8 eeh_readb(const volatile void __iomem *addr)
	290	{
	291	u8 val = in_8(addr);
	292	if (EEH_POSSIBLE_ERROR(val, u8))
	293	return eeh_check_failure(addr, val);
	294	return val;
	295	}
1da177e4 LT	296
	297	static inline u16 eeh_readw(const volatile void __iomem *addr)
	298	{
	299	u16 val = in_le16(addr);
	300	if (EEH_POSSIBLE_ERROR(val, u16))
	301	return eeh_check_failure(addr, val);
	302	return val;
	303	}
1da177e4 LT	304
	305	static inline u32 eeh_readl(const volatile void __iomem *addr)
	306	{
	307	u32 val = in_le32(addr);
	308	if (EEH_POSSIBLE_ERROR(val, u32))
	309	return eeh_check_failure(addr, val);
	310	return val;
	311	}
4cb3cee0 BH	312
4cb3cee0 BH	313	static inline u64 eeh_readq(const volatile void __iomem *addr)
1da177e4	314	{
4cb3cee0 BH	315	u64 val = in_le64(addr);
4cb3cee0 BH	316	if (EEH_POSSIBLE_ERROR(val, u64))
1da177e4 LT	317	return eeh_check_failure(addr, val);
	318	return val;
	319	}
1da177e4	320
4cb3cee0	321	static inline u16 eeh_readw_be(const volatile void __iomem *addr)
1da177e4	322	{
4cb3cee0 BH	323	u16 val = in_be16(addr);
4cb3cee0 BH	324	if (EEH_POSSIBLE_ERROR(val, u16))
1da177e4 LT	325	return eeh_check_failure(addr, val);
	326	return val;
	327	}
4cb3cee0 BH	328
4cb3cee0 BH	329	static inline u32 eeh_readl_be(const volatile void __iomem *addr)
1da177e4	330	{
4cb3cee0 BH	331	u32 val = in_be32(addr);
	332	if (EEH_POSSIBLE_ERROR(val, u32))
	333	return eeh_check_failure(addr, val);
	334	return val;
1da177e4	335	}
4cb3cee0 BH	336
4cb3cee0 BH	337	static inline u64 eeh_readq_be(const volatile void __iomem *addr)
1da177e4 LT	338	{
	339	u64 val = in_be64(addr);
	340	if (EEH_POSSIBLE_ERROR(val, u64))
	341	return eeh_check_failure(addr, val);
	342	return val;
	343	}
1da177e4	344
68a64357 BH	345	static inline void eeh_memcpy_fromio(void *dest, const
68a64357 BH	346	volatile void __iomem *src,
1da177e4 LT	347	unsigned long n)
1da177e4 LT	348	{
68a64357	349	_memcpy_fromio(dest, src, n);
1da177e4 LT	350
	351	/* Look for ffff's here at dest[n]. Assume that at least 4 bytes
	352	* were copied. Check all four bytes.
	353	*/
68a64357 BH	354	if (n >= 4 && EEH_POSSIBLE_ERROR(((u32 )(dest + n - 4)), u32))
68a64357 BH	355	eeh_check_failure(src, ((u32 )(dest + n - 4)));
1da177e4 LT	356	}
1da177e4 LT	357
1da177e4	358	/* in-string eeh macros */
4cb3cee0 BH	359	static inline void eeh_readsb(const volatile void __iomem addr, void buf,
4cb3cee0 BH	360	int ns)
1da177e4	361	{
4cb3cee0	362	_insb(addr, buf, ns);
1da177e4	363	if (EEH_POSSIBLE_ERROR(((((u8)buf)+ns-1)), u8))
4cb3cee0	364	eeh_check_failure(addr, (u8)buf);
1da177e4 LT	365	}
1da177e4 LT	366
4cb3cee0 BH	367	static inline void eeh_readsw(const volatile void __iomem addr, void buf,
4cb3cee0 BH	368	int ns)
1da177e4	369	{
4cb3cee0	370	_insw(addr, buf, ns);
1da177e4	371	if (EEH_POSSIBLE_ERROR(((((u16)buf)+ns-1)), u16))
4cb3cee0	372	eeh_check_failure(addr, (u16)buf);
1da177e4 LT	373	}
1da177e4 LT	374
4cb3cee0 BH	375	static inline void eeh_readsl(const volatile void __iomem addr, void buf,
4cb3cee0 BH	376	int nl)
1da177e4	377	{
4cb3cee0	378	_insl(addr, buf, nl);
1da177e4	379	if (EEH_POSSIBLE_ERROR(((((u32)buf)+nl-1)), u32))
4cb3cee0	380	eeh_check_failure(addr, (u32)buf);
1da177e4 LT	381	}
1da177e4 LT	382
8b8da358	383	#endif /* CONFIG_PPC64 */
88ced031	384	#endif /* __KERNEL__ */
8b8da358	385	#endif /* _POWERPC_EEH_H */