Commit | Line | Data |
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1da177e4 | 1 | /* |
78b09735 SR |
2 | * Copyright (C) 2004 IBM |
3 | * | |
4 | * Implements the generic device dma API for powerpc. | |
5 | * the pci and vio busses | |
1da177e4 | 6 | */ |
78b09735 SR |
7 | #ifndef _ASM_DMA_MAPPING_H |
8 | #define _ASM_DMA_MAPPING_H | |
33ff910f AB |
9 | #ifdef __KERNEL__ |
10 | ||
11 | #include <linux/types.h> | |
12 | #include <linux/cache.h> | |
13 | /* need struct page definitions */ | |
14 | #include <linux/mm.h> | |
15 | #include <linux/scatterlist.h> | |
3affedc4 | 16 | #include <linux/dma-attrs.h> |
46bab4e4 | 17 | #include <linux/dma-debug.h> |
33ff910f | 18 | #include <asm/io.h> |
ec3cf2ec | 19 | #include <asm/swiotlb.h> |
33ff910f AB |
20 | |
21 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | |
22 | ||
ec3cf2ec BB |
23 | /* Some dma direct funcs must be visible for use in other dma_ops */ |
24 | extern void *dma_direct_alloc_coherent(struct device *dev, size_t size, | |
bfbf7d61 AP |
25 | dma_addr_t *dma_handle, gfp_t flag, |
26 | struct dma_attrs *attrs); | |
ec3cf2ec | 27 | extern void dma_direct_free_coherent(struct device *dev, size_t size, |
bfbf7d61 AP |
28 | void *vaddr, dma_addr_t dma_handle, |
29 | struct dma_attrs *attrs); | |
64ccc9c0 MS |
30 | extern int dma_direct_mmap_coherent(struct device *dev, |
31 | struct vm_area_struct *vma, | |
32 | void *cpu_addr, dma_addr_t handle, | |
33 | size_t size, struct dma_attrs *attrs); | |
ec3cf2ec | 34 | |
33ff910f AB |
35 | #ifdef CONFIG_NOT_COHERENT_CACHE |
36 | /* | |
37 | * DMA-consistent mapping functions for PowerPCs that don't support | |
38 | * cache snooping. These allocate/free a region of uncached mapped | |
39 | * memory space for use with DMA devices. Alternatively, you could | |
40 | * allocate the space "normally" and use the cache management functions | |
41 | * to ensure it is consistent. | |
42 | */ | |
8b31e49d BH |
43 | struct device; |
44 | extern void *__dma_alloc_coherent(struct device *dev, size_t size, | |
45 | dma_addr_t *handle, gfp_t gfp); | |
33ff910f AB |
46 | extern void __dma_free_coherent(size_t size, void *vaddr); |
47 | extern void __dma_sync(void *vaddr, size_t size, int direction); | |
48 | extern void __dma_sync_page(struct page *page, unsigned long offset, | |
49 | size_t size, int direction); | |
6090912c | 50 | extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr); |
33ff910f AB |
51 | |
52 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ | |
53 | /* | |
54 | * Cache coherent cores. | |
55 | */ | |
56 | ||
8b31e49d | 57 | #define __dma_alloc_coherent(dev, gfp, size, handle) NULL |
33ff910f AB |
58 | #define __dma_free_coherent(size, addr) ((void)0) |
59 | #define __dma_sync(addr, size, rw) ((void)0) | |
60 | #define __dma_sync_page(pg, off, sz, rw) ((void)0) | |
61 | ||
62 | #endif /* ! CONFIG_NOT_COHERENT_CACHE */ | |
63 | ||
3a4c6f0b MN |
64 | static inline unsigned long device_to_mask(struct device *dev) |
65 | { | |
66 | if (dev->dma_mask && *dev->dma_mask) | |
67 | return *dev->dma_mask; | |
68 | /* Assume devices without mask can take 32 bit addresses */ | |
69 | return 0xfffffffful; | |
70 | } | |
71 | ||
4fc665b8 BB |
72 | /* |
73 | * Available generic sets of operations | |
74 | */ | |
75 | #ifdef CONFIG_PPC64 | |
45223c54 | 76 | extern struct dma_map_ops dma_iommu_ops; |
4fc665b8 | 77 | #endif |
45223c54 | 78 | extern struct dma_map_ops dma_direct_ops; |
4fc665b8 | 79 | |
45223c54 | 80 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) |
33ff910f AB |
81 | { |
82 | /* We don't handle the NULL dev case for ISA for now. We could | |
83 | * do it via an out of line call but it is not needed for now. The | |
84 | * only ISA DMA device we support is the floppy and we have a hack | |
85 | * in the floppy driver directly to get a device for us. | |
86 | */ | |
4ae0ff60 | 87 | if (unlikely(dev == NULL)) |
33ff910f | 88 | return NULL; |
4fc665b8 | 89 | |
33ff910f | 90 | return dev->archdata.dma_ops; |
1f62a162 ME |
91 | } |
92 | ||
45223c54 | 93 | static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops) |
1f62a162 ME |
94 | { |
95 | dev->archdata.dma_ops = ops; | |
33ff910f AB |
96 | } |
97 | ||
1cebd7a0 BB |
98 | /* |
99 | * get_dma_offset() | |
100 | * | |
101 | * Get the dma offset on configurations where the dma address can be determined | |
102 | * from the physical address by looking at a simple offset. Direct dma and | |
103 | * swiotlb use this function, but it is typically not used by implementations | |
104 | * with an iommu. | |
105 | */ | |
738ef42e | 106 | static inline dma_addr_t get_dma_offset(struct device *dev) |
1cebd7a0 BB |
107 | { |
108 | if (dev) | |
738ef42e | 109 | return dev->archdata.dma_data.dma_offset; |
1cebd7a0 BB |
110 | |
111 | return PCI_DRAM_OFFSET; | |
112 | } | |
113 | ||
738ef42e BB |
114 | static inline void set_dma_offset(struct device *dev, dma_addr_t off) |
115 | { | |
116 | if (dev) | |
117 | dev->archdata.dma_data.dma_offset = off; | |
118 | } | |
119 | ||
46bab4e4 FT |
120 | /* this will be removed soon */ |
121 | #define flush_write_buffers() | |
122 | ||
123 | #include <asm-generic/dma-mapping-common.h> | |
124 | ||
33ff910f AB |
125 | static inline int dma_supported(struct device *dev, u64 mask) |
126 | { | |
45223c54 | 127 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
33ff910f AB |
128 | |
129 | if (unlikely(dma_ops == NULL)) | |
130 | return 0; | |
131 | if (dma_ops->dma_supported == NULL) | |
132 | return 1; | |
133 | return dma_ops->dma_supported(dev, mask); | |
134 | } | |
135 | ||
5b6e9ff6 | 136 | extern int dma_set_mask(struct device *dev, u64 dma_mask); |
cd15b048 | 137 | extern int __dma_set_mask(struct device *dev, u64 dma_mask); |
33ff910f | 138 | |
bfbf7d61 AP |
139 | #define dma_alloc_coherent(d,s,h,f) dma_alloc_attrs(d,s,h,f,NULL) |
140 | ||
141 | static inline void *dma_alloc_attrs(struct device *dev, size_t size, | |
142 | dma_addr_t *dma_handle, gfp_t flag, | |
143 | struct dma_attrs *attrs) | |
33ff910f | 144 | { |
45223c54 | 145 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
80d3e8ab | 146 | void *cpu_addr; |
33ff910f AB |
147 | |
148 | BUG_ON(!dma_ops); | |
80d3e8ab | 149 | |
bfbf7d61 | 150 | cpu_addr = dma_ops->alloc(dev, size, dma_handle, flag, attrs); |
80d3e8ab FT |
151 | |
152 | debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr); | |
153 | ||
154 | return cpu_addr; | |
33ff910f AB |
155 | } |
156 | ||
bfbf7d61 AP |
157 | #define dma_free_coherent(d,s,c,h) dma_free_attrs(d,s,c,h,NULL) |
158 | ||
159 | static inline void dma_free_attrs(struct device *dev, size_t size, | |
160 | void *cpu_addr, dma_addr_t dma_handle, | |
161 | struct dma_attrs *attrs) | |
33ff910f | 162 | { |
45223c54 | 163 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
33ff910f AB |
164 | |
165 | BUG_ON(!dma_ops); | |
80d3e8ab FT |
166 | |
167 | debug_dma_free_coherent(dev, size, cpu_addr, dma_handle); | |
168 | ||
bfbf7d61 | 169 | dma_ops->free(dev, size, cpu_addr, dma_handle, attrs); |
33ff910f AB |
170 | } |
171 | ||
8d8bb39b | 172 | static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
78b09735 | 173 | { |
4a9a6bfe FT |
174 | struct dma_map_ops *dma_ops = get_dma_ops(dev); |
175 | ||
34daa88e | 176 | debug_dma_mapping_error(dev, dma_addr); |
4a9a6bfe FT |
177 | if (dma_ops->mapping_error) |
178 | return dma_ops->mapping_error(dev, dma_addr); | |
179 | ||
78b09735 SR |
180 | #ifdef CONFIG_PPC64 |
181 | return (dma_addr == DMA_ERROR_CODE); | |
182 | #else | |
183 | return 0; | |
184 | #endif | |
185 | } | |
186 | ||
9a937c91 FT |
187 | static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) |
188 | { | |
762afb73 FT |
189 | #ifdef CONFIG_SWIOTLB |
190 | struct dev_archdata *sd = &dev->archdata; | |
9a937c91 | 191 | |
762afb73 | 192 | if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr) |
9a937c91 | 193 | return 0; |
762afb73 | 194 | #endif |
9a937c91 FT |
195 | |
196 | if (!dev->dma_mask) | |
197 | return 0; | |
198 | ||
ac2b3e67 | 199 | return addr + size - 1 <= *dev->dma_mask; |
9a937c91 FT |
200 | } |
201 | ||
8d4f5339 FT |
202 | static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
203 | { | |
1cebd7a0 | 204 | return paddr + get_dma_offset(dev); |
8d4f5339 FT |
205 | } |
206 | ||
207 | static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) | |
208 | { | |
1cebd7a0 | 209 | return daddr - get_dma_offset(dev); |
8d4f5339 FT |
210 | } |
211 | ||
1da177e4 LT |
212 | #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) |
213 | #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) | |
1da177e4 | 214 | |
6090912c BH |
215 | #define ARCH_HAS_DMA_MMAP_COHERENT |
216 | ||
d3fa72e4 | 217 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
78b09735 | 218 | enum dma_data_direction direction) |
1da177e4 | 219 | { |
78b09735 | 220 | BUG_ON(direction == DMA_NONE); |
1da177e4 LT |
221 | __dma_sync(vaddr, size, (int)direction); |
222 | } | |
223 | ||
88ced031 | 224 | #endif /* __KERNEL__ */ |
78b09735 | 225 | #endif /* _ASM_DMA_MAPPING_H */ |