Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
78b09735 SR |
2 | * Copyright (C) 2004 IBM |
3 | * | |
4 | * Implements the generic device dma API for powerpc. | |
5 | * the pci and vio busses | |
1da177e4 | 6 | */ |
78b09735 SR |
7 | #ifndef _ASM_DMA_MAPPING_H |
8 | #define _ASM_DMA_MAPPING_H | |
33ff910f AB |
9 | #ifdef __KERNEL__ |
10 | ||
11 | #include <linux/types.h> | |
12 | #include <linux/cache.h> | |
13 | /* need struct page definitions */ | |
14 | #include <linux/mm.h> | |
15 | #include <linux/scatterlist.h> | |
46bab4e4 | 16 | #include <linux/dma-debug.h> |
33ff910f | 17 | #include <asm/io.h> |
ec3cf2ec | 18 | #include <asm/swiotlb.h> |
33ff910f | 19 | |
efa21e43 | 20 | #ifdef CONFIG_PPC64 |
33ff910f | 21 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) |
efa21e43 | 22 | #endif |
33ff910f | 23 | |
ec3cf2ec | 24 | /* Some dma direct funcs must be visible for use in other dma_ops */ |
817820b0 BH |
25 | extern void *__dma_direct_alloc_coherent(struct device *dev, size_t size, |
26 | dma_addr_t *dma_handle, gfp_t flag, | |
00085f1e | 27 | unsigned long attrs); |
817820b0 BH |
28 | extern void __dma_direct_free_coherent(struct device *dev, size_t size, |
29 | void *vaddr, dma_addr_t dma_handle, | |
00085f1e | 30 | unsigned long attrs); |
64ccc9c0 MS |
31 | extern int dma_direct_mmap_coherent(struct device *dev, |
32 | struct vm_area_struct *vma, | |
33 | void *cpu_addr, dma_addr_t handle, | |
00085f1e | 34 | size_t size, unsigned long attrs); |
ec3cf2ec | 35 | |
33ff910f AB |
36 | #ifdef CONFIG_NOT_COHERENT_CACHE |
37 | /* | |
38 | * DMA-consistent mapping functions for PowerPCs that don't support | |
39 | * cache snooping. These allocate/free a region of uncached mapped | |
40 | * memory space for use with DMA devices. Alternatively, you could | |
41 | * allocate the space "normally" and use the cache management functions | |
42 | * to ensure it is consistent. | |
43 | */ | |
8b31e49d BH |
44 | struct device; |
45 | extern void *__dma_alloc_coherent(struct device *dev, size_t size, | |
46 | dma_addr_t *handle, gfp_t gfp); | |
33ff910f AB |
47 | extern void __dma_free_coherent(size_t size, void *vaddr); |
48 | extern void __dma_sync(void *vaddr, size_t size, int direction); | |
49 | extern void __dma_sync_page(struct page *page, unsigned long offset, | |
50 | size_t size, int direction); | |
6090912c | 51 | extern unsigned long __dma_get_coherent_pfn(unsigned long cpu_addr); |
33ff910f AB |
52 | |
53 | #else /* ! CONFIG_NOT_COHERENT_CACHE */ | |
54 | /* | |
55 | * Cache coherent cores. | |
56 | */ | |
57 | ||
8b31e49d | 58 | #define __dma_alloc_coherent(dev, gfp, size, handle) NULL |
33ff910f AB |
59 | #define __dma_free_coherent(size, addr) ((void)0) |
60 | #define __dma_sync(addr, size, rw) ((void)0) | |
61 | #define __dma_sync_page(pg, off, sz, rw) ((void)0) | |
62 | ||
63 | #endif /* ! CONFIG_NOT_COHERENT_CACHE */ | |
64 | ||
3a4c6f0b MN |
65 | static inline unsigned long device_to_mask(struct device *dev) |
66 | { | |
67 | if (dev->dma_mask && *dev->dma_mask) | |
68 | return *dev->dma_mask; | |
69 | /* Assume devices without mask can take 32 bit addresses */ | |
70 | return 0xfffffffful; | |
71 | } | |
72 | ||
4fc665b8 BB |
73 | /* |
74 | * Available generic sets of operations | |
75 | */ | |
76 | #ifdef CONFIG_PPC64 | |
45223c54 | 77 | extern struct dma_map_ops dma_iommu_ops; |
4fc665b8 | 78 | #endif |
45223c54 | 79 | extern struct dma_map_ops dma_direct_ops; |
4fc665b8 | 80 | |
45223c54 | 81 | static inline struct dma_map_ops *get_dma_ops(struct device *dev) |
33ff910f AB |
82 | { |
83 | /* We don't handle the NULL dev case for ISA for now. We could | |
84 | * do it via an out of line call but it is not needed for now. The | |
85 | * only ISA DMA device we support is the floppy and we have a hack | |
86 | * in the floppy driver directly to get a device for us. | |
87 | */ | |
4ae0ff60 | 88 | if (unlikely(dev == NULL)) |
33ff910f | 89 | return NULL; |
4fc665b8 | 90 | |
33ff910f | 91 | return dev->archdata.dma_ops; |
1f62a162 ME |
92 | } |
93 | ||
45223c54 | 94 | static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops) |
1f62a162 ME |
95 | { |
96 | dev->archdata.dma_ops = ops; | |
33ff910f AB |
97 | } |
98 | ||
1cebd7a0 BB |
99 | /* |
100 | * get_dma_offset() | |
101 | * | |
102 | * Get the dma offset on configurations where the dma address can be determined | |
103 | * from the physical address by looking at a simple offset. Direct dma and | |
104 | * swiotlb use this function, but it is typically not used by implementations | |
105 | * with an iommu. | |
106 | */ | |
738ef42e | 107 | static inline dma_addr_t get_dma_offset(struct device *dev) |
1cebd7a0 BB |
108 | { |
109 | if (dev) | |
2db4928b | 110 | return dev->archdata.dma_offset; |
1cebd7a0 BB |
111 | |
112 | return PCI_DRAM_OFFSET; | |
113 | } | |
114 | ||
738ef42e BB |
115 | static inline void set_dma_offset(struct device *dev, dma_addr_t off) |
116 | { | |
117 | if (dev) | |
2db4928b | 118 | dev->archdata.dma_offset = off; |
738ef42e BB |
119 | } |
120 | ||
46bab4e4 FT |
121 | /* this will be removed soon */ |
122 | #define flush_write_buffers() | |
123 | ||
452e06af CH |
124 | #define HAVE_ARCH_DMA_SET_MASK 1 |
125 | extern int dma_set_mask(struct device *dev, u64 dma_mask); | |
126 | ||
cd15b048 | 127 | extern int __dma_set_mask(struct device *dev, u64 dma_mask); |
fe7e85c6 | 128 | extern u64 __dma_get_required_mask(struct device *dev); |
33ff910f | 129 | |
9a937c91 FT |
130 | static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size) |
131 | { | |
762afb73 FT |
132 | #ifdef CONFIG_SWIOTLB |
133 | struct dev_archdata *sd = &dev->archdata; | |
9a937c91 | 134 | |
762afb73 | 135 | if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr) |
acdb6685 | 136 | return false; |
762afb73 | 137 | #endif |
9a937c91 FT |
138 | |
139 | if (!dev->dma_mask) | |
acdb6685 | 140 | return false; |
9a937c91 | 141 | |
ac2b3e67 | 142 | return addr + size - 1 <= *dev->dma_mask; |
9a937c91 FT |
143 | } |
144 | ||
8d4f5339 FT |
145 | static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
146 | { | |
1cebd7a0 | 147 | return paddr + get_dma_offset(dev); |
8d4f5339 FT |
148 | } |
149 | ||
150 | static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr) | |
151 | { | |
1cebd7a0 | 152 | return daddr - get_dma_offset(dev); |
8d4f5339 FT |
153 | } |
154 | ||
6090912c BH |
155 | #define ARCH_HAS_DMA_MMAP_COHERENT |
156 | ||
d3fa72e4 | 157 | static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
78b09735 | 158 | enum dma_data_direction direction) |
1da177e4 | 159 | { |
78b09735 | 160 | BUG_ON(direction == DMA_NONE); |
1da177e4 LT |
161 | __dma_sync(vaddr, size, (int)direction); |
162 | } | |
163 | ||
88ced031 | 164 | #endif /* __KERNEL__ */ |
78b09735 | 165 | #endif /* _ASM_DMA_MAPPING_H */ |