projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| d94d71cb | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| c381a043 | 2 | /* |
| c381a043 HB |
3 | * |
| 4 | * Copyright IBM Corp. 2008 | |
| 5 | * | |
| 6 | * Authors: Hollis Blanchard <hollisb@us.ibm.com> | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef __ASM_PPC_DISASSEMBLE_H__ | |
| 10 | #define __ASM_PPC_DISASSEMBLE_H__ | |
| 11 | ||
| 12 | #include <linux/types.h> | |
| 13 | ||
| 14 | static inline unsigned int get_op(u32 inst) | |
| 15 | { | |
| 16 | return inst >> 26; | |
| 17 | } | |
| 18 | ||
| 19 | static inline unsigned int get_xop(u32 inst) | |
| 20 | { | |
| 21 | return (inst >> 1) & 0x3ff; | |
| 22 | } | |
| 23 | ||
| 24 | static inline unsigned int get_sprn(u32 inst) | |
| 25 | { | |
| 26 | return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); | |
| 27 | } | |
| 28 | ||
| 29 | static inline unsigned int get_dcrn(u32 inst) | |
| 30 | { | |
| 31 | return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); | |
| 32 | } | |
| 33 | ||
| 2daab50e TL |
34 | static inline unsigned int get_tmrn(u32 inst) |
| 35 | { | |
| 36 | return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0); | |
| 37 | } | |
| 38 | ||
| c381a043 HB |
39 | static inline unsigned int get_rt(u32 inst) |
| 40 | { | |
| 41 | return (inst >> 21) & 0x1f; | |
| 42 | } | |
| 43 | ||
| 44 | static inline unsigned int get_rs(u32 inst) | |
| 45 | { | |
| 46 | return (inst >> 21) & 0x1f; | |
| 47 | } | |
| 48 | ||
| 49 | static inline unsigned int get_ra(u32 inst) | |
| 50 | { | |
| 51 | return (inst >> 16) & 0x1f; | |
| 52 | } | |
| 53 | ||
| 54 | static inline unsigned int get_rb(u32 inst) | |
| 55 | { | |
| 56 | return (inst >> 11) & 0x1f; | |
| 57 | } | |
| 58 | ||
| 59 | static inline unsigned int get_rc(u32 inst) | |
| 60 | { | |
| 61 | return inst & 0x1; | |
| 62 | } | |
| 63 | ||
| 64 | static inline unsigned int get_ws(u32 inst) | |
| 65 | { | |
| 66 | return (inst >> 11) & 0x1f; | |
| 67 | } | |
| 68 | ||
| 69 | static inline unsigned int get_d(u32 inst) | |
| 70 | { | |
| 71 | return inst & 0xffff; | |
| 72 | } | |
| 73 | ||
| b12c7841 BB |
74 | static inline unsigned int get_oc(u32 inst) |
| 75 | { | |
| 76 | return (inst >> 11) & 0x7fff; | |
| 77 | } | |
| ddca156a | 78 | |
| 6f63e81b BL |
79 | static inline unsigned int get_tx_or_sx(u32 inst) |
| 80 | { | |
| 81 | return (inst) & 0x1; | |
| 82 | } | |
| 83 | ||
| ddca156a AK |
84 | #define IS_XFORM(inst) (get_op(inst) == 31) |
| 85 | #define IS_DSFORM(inst) (get_op(inst) >= 56) | |
| 86 | ||
| 87 | /* | |
| 88 | * Create a DSISR value from the instruction | |
| 89 | */ | |
| 90 | static inline unsigned make_dsisr(unsigned instr) | |
| 91 | { | |
| 92 | unsigned dsisr; | |
| 93 | ||
| 94 | ||
| 95 | /* bits 6:15 --> 22:31 */ | |
| 96 | dsisr = (instr & 0x03ff0000) >> 16; | |
| 97 | ||
| 98 | if (IS_XFORM(instr)) { | |
| 99 | /* bits 29:30 --> 15:16 */ | |
| 100 | dsisr |= (instr & 0x00000006) << 14; | |
| 101 | /* bit 25 --> 17 */ | |
| 102 | dsisr |= (instr & 0x00000040) << 8; | |
| 103 | /* bits 21:24 --> 18:21 */ | |
| 104 | dsisr |= (instr & 0x00000780) << 3; | |
| 105 | } else { | |
| 106 | /* bit 5 --> 17 */ | |
| 107 | dsisr |= (instr & 0x04000000) >> 12; | |
| 108 | /* bits 1: 4 --> 18:21 */ | |
| 109 | dsisr |= (instr & 0x78000000) >> 17; | |
| 110 | /* bits 30:31 --> 12:13 */ | |
| 111 | if (IS_DSFORM(instr)) | |
| 112 | dsisr |= (instr & 0x00000003) << 18; | |
| 113 | } | |
| 114 | ||
| 115 | return dsisr; | |
| 116 | } | |
| c381a043 | 117 | #endif /* __ASM_PPC_DISASSEMBLE_H__ */ |