[linux-block.git] / arch / powerpc / include / asm / dcr-native.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
 *                    <benh@kernel.crashing.org>
 */

#ifndef _ASM_POWERPC_DCR_NATIVE_H
#define _ASM_POWERPC_DCR_NATIVE_H
#ifdef __KERNEL__
#ifndef __ASSEMBLY__

#include <linux/spinlock.h>
#include <asm/cputable.h>
#include <asm/cpu_has_feature.h>
#include <linux/stringify.h>

typedef struct {
	unsigned int base;
} dcr_host_native_t;

static inline bool dcr_map_ok_native(dcr_host_native_t host)
{
	return true;
}

#define dcr_map_native(dev, dcr_n, dcr_c) \
	((dcr_host_native_t){ .base = (dcr_n) })
#define dcr_unmap_native(host, dcr_c)		do {} while (0)
#define dcr_read_native(host, dcr_n)		mfdcr(dcr_n + host.base)
#define dcr_write_native(host, dcr_n, value)	mtdcr(dcr_n + host.base, value)

/* Table based DCR accessors */
extern void __mtdcr(unsigned int reg, unsigned int val);
extern unsigned int __mfdcr(unsigned int reg);

/* mfdcrx/mtdcrx instruction based accessors. We hand code
 * the opcodes in order not to depend on newer binutils
 */
static inline unsigned int mfdcrx(unsigned int reg)
{
	unsigned int ret;
	asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
		     : "=r" (ret) : "r" (reg));
	return ret;
}

static inline void mtdcrx(unsigned int reg, unsigned int val)
{
	asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
		     : : "r" (val), "r" (reg));
}

#define mfdcr(rn)						\
	({unsigned int rval;					\
	if (__builtin_constant_p(rn) && rn < 1024)		\
		asm volatile("mfdcr %0," __stringify(rn)	\
		              : "=r" (rval));			\
	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))	\
		rval = mfdcrx(rn);				\
	else							\
		rval = __mfdcr(rn);				\
	rval;})

#define mtdcr(rn, v)						\
do {								\
	if (__builtin_constant_p(rn) && rn < 1024)		\
		asm volatile("mtdcr " __stringify(rn) ",%0"	\
			      : : "r" (v)); 			\
	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))	\
		mtdcrx(rn, v);					\
	else							\
		__mtdcr(rn, v);					\
} while (0)

/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
extern spinlock_t dcr_ind_lock;

static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
{
	unsigned long flags;
	unsigned int val;

	spin_lock_irqsave(&dcr_ind_lock, flags);
	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
		mtdcrx(base_addr, reg);
		val = mfdcrx(base_data);
	} else {
		__mtdcr(base_addr, reg);
		val = __mfdcr(base_data);
	}
	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	return val;
}

static inline void __mtdcri(int base_addr, int base_data, int reg,
			    unsigned val)
{
	unsigned long flags;

	spin_lock_irqsave(&dcr_ind_lock, flags);
	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
		mtdcrx(base_addr, reg);
		mtdcrx(base_data, val);
	} else {
		__mtdcr(base_addr, reg);
		__mtdcr(base_data, val);
	}
	spin_unlock_irqrestore(&dcr_ind_lock, flags);
}

static inline void __dcri_clrset(int base_addr, int base_data, int reg,
				 unsigned clr, unsigned set)
{
	unsigned long flags;
	unsigned int val;

	spin_lock_irqsave(&dcr_ind_lock, flags);
	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
		mtdcrx(base_addr, reg);
		val = (mfdcrx(base_data) & ~clr) | set;
		mtdcrx(base_data, val);
	} else {
		__mtdcr(base_addr, reg);
		val = (__mfdcr(base_data) & ~clr) | set;
		__mtdcr(base_data, val);
	}
	spin_unlock_irqrestore(&dcr_ind_lock, flags);
}

#define mfdcri(base, reg)	__mfdcri(DCRN_ ## base ## _CONFIG_ADDR,	\
					 DCRN_ ## base ## _CONFIG_DATA,	\
					 reg)

#define mtdcri(base, reg, data)	__mtdcri(DCRN_ ## base ## _CONFIG_ADDR,	\
					 DCRN_ ## base ## _CONFIG_DATA,	\
					 reg, data)

#define dcri_clrset(base, reg, clr, set)	__dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,	\
							      DCRN_ ## base ## _CONFIG_DATA,	\
							      reg, clr, set)

#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DCR_NATIVE_H */
Commit	Line	Data
1a59d1b8	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
4c75a6f4 BH	2	/*
	3	* (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
	4	* <benh@kernel.crashing.org>
4c75a6f4 BH	5	*/
	6
	7	#ifndef _ASM_POWERPC_DCR_NATIVE_H
	8	#define _ASM_POWERPC_DCR_NATIVE_H
	9	#ifdef __KERNEL__
45d8e7aa	10	#ifndef __ASSEMBLY__
4c75a6f4	11
0e6140a5	12	#include <linux/spinlock.h>
6d2170be	13	#include <asm/cputable.h>
b92a226e	14	#include <asm/cpu_has_feature.h>
5c35a02c	15	#include <linux/stringify.h>
0e6140a5	16
0b94a1ee ME	17	typedef struct {
0b94a1ee ME	18	unsigned int base;
b786af11	19	} dcr_host_native_t;
4c75a6f4	20
b786af11 SN	21	static inline bool dcr_map_ok_native(dcr_host_native_t host)
b786af11 SN	22	{
acdb6685	23	return true;
b786af11	24	}
4c75a6f4	25
b786af11 SN	26	#define dcr_map_native(dev, dcr_n, dcr_c) \
	27	((dcr_host_native_t){ .base = (dcr_n) })
	28	#define dcr_unmap_native(host, dcr_c) do {} while (0)
	29	#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
	30	#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
4c75a6f4	31
6d2170be BH	32	/* Table based DCR accessors */
	33	extern void __mtdcr(unsigned int reg, unsigned int val);
	34	extern unsigned int __mfdcr(unsigned int reg);
	35
	36	/* mfdcrx/mtdcrx instruction based accessors. We hand code
	37	* the opcodes in order not to depend on newer binutils
	38	*/
	39	static inline unsigned int mfdcrx(unsigned int reg)
	40	{
	41	unsigned int ret;
	42	asm volatile(".long 0x7c000206 \| (%0 << 21) \| (%1 << 16)"
	43	: "=r" (ret) : "r" (reg));
	44	return ret;
	45	}
	46
	47	static inline void mtdcrx(unsigned int reg, unsigned int val)
	48	{
	49	asm volatile(".long 0x7c000306 \| (%0 << 21) \| (%1 << 16)"
	50	: : "r" (val), "r" (reg));
	51	}
	52
45d8e7aa KG	53	#define mfdcr(rn) \
45d8e7aa KG	54	({unsigned int rval; \
6d2170be	55	if (__builtin_constant_p(rn) && rn < 1024) \
45d8e7aa KG	56	asm volatile("mfdcr %0," __stringify(rn) \
45d8e7aa KG	57	: "=r" (rval)); \
6d2170be BH	58	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
6d2170be BH	59	rval = mfdcrx(rn); \
45d8e7aa KG	60	else \
	61	rval = __mfdcr(rn); \
	62	rval;})
	63
	64	#define mtdcr(rn, v) \
	65	do { \
6d2170be	66	if (__builtin_constant_p(rn) && rn < 1024) \
45d8e7aa KG	67	asm volatile("mtdcr " __stringify(rn) ",%0" \
45d8e7aa KG	68	: : "r" (v)); \
6d2170be BH	69	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
6d2170be BH	70	mtdcrx(rn, v); \
45d8e7aa KG	71	else \
	72	__mtdcr(rn, v); \
	73	} while (0)
	74
	75	/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
0e6140a5 BH	76	extern spinlock_t dcr_ind_lock;
0e6140a5 BH	77
e8318d98 VB	78	static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
	79	{
	80	unsigned long flags;
	81	unsigned int val;
45d8e7aa	82
e8318d98	83	spin_lock_irqsave(&dcr_ind_lock, flags);
6d2170be BH	84	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
	85	mtdcrx(base_addr, reg);
	86	val = mfdcrx(base_data);
	87	} else {
	88	__mtdcr(base_addr, reg);
	89	val = __mfdcr(base_data);
	90	}
e8318d98 VB	91	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	92	return val;
	93	}
	94
	95	static inline void __mtdcri(int base_addr, int base_data, int reg,
	96	unsigned val)
	97	{
	98	unsigned long flags;
	99
	100	spin_lock_irqsave(&dcr_ind_lock, flags);
6d2170be BH	101	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
	102	mtdcrx(base_addr, reg);
	103	mtdcrx(base_data, val);
	104	} else {
	105	__mtdcr(base_addr, reg);
	106	__mtdcr(base_data, val);
	107	}
e8318d98 VB	108	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	109	}
	110
266d028a VB	111	static inline void __dcri_clrset(int base_addr, int base_data, int reg,
	112	unsigned clr, unsigned set)
	113	{
	114	unsigned long flags;
	115	unsigned int val;
	116
	117	spin_lock_irqsave(&dcr_ind_lock, flags);
6d2170be BH	118	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
	119	mtdcrx(base_addr, reg);
	120	val = (mfdcrx(base_data) & ~clr) \| set;
	121	mtdcrx(base_data, val);
	122	} else {
	123	__mtdcr(base_addr, reg);
	124	val = (__mfdcr(base_data) & ~clr) \| set;
	125	__mtdcr(base_data, val);
	126	}
266d028a VB	127	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	128	}
	129
e8318d98 VB	130	#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
	131	DCRN_ ## base ## _CONFIG_DATA, \
	132	reg)
	133
	134	#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
	135	DCRN_ ## base ## _CONFIG_DATA, \
	136	reg, data)
4c75a6f4	137
266d028a VB	138	#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
	139	DCRN_ ## base ## _CONFIG_DATA, \
	140	reg, clr, set)
	141
45d8e7aa	142	#endif /* __ASSEMBLY__ */
4c75a6f4 BH	143	#endif /* __KERNEL__ */
4c75a6f4 BH	144	#endif /* _ASM_POWERPC_DCR_NATIVE_H */