[linux-2.6-block.git] / arch / powerpc / include / asm / dcr-native.h

/*
 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
 *                    <benh@kernel.crashing.org>
 *
 *   This program is free software;  you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
 *   the GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program;  if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */

#ifndef _ASM_POWERPC_DCR_NATIVE_H
#define _ASM_POWERPC_DCR_NATIVE_H
#ifdef __KERNEL__
#ifndef __ASSEMBLY__

#include <linux/spinlock.h>
#include <asm/cputable.h>
#include <asm/cpu_has_feature.h>

typedef struct {
	unsigned int base;
} dcr_host_native_t;

static inline bool dcr_map_ok_native(dcr_host_native_t host)
{
	return true;
}

#define dcr_map_native(dev, dcr_n, dcr_c) \
	((dcr_host_native_t){ .base = (dcr_n) })
#define dcr_unmap_native(host, dcr_c)		do {} while (0)
#define dcr_read_native(host, dcr_n)		mfdcr(dcr_n + host.base)
#define dcr_write_native(host, dcr_n, value)	mtdcr(dcr_n + host.base, value)

/* Table based DCR accessors */
extern void __mtdcr(unsigned int reg, unsigned int val);
extern unsigned int __mfdcr(unsigned int reg);

/* mfdcrx/mtdcrx instruction based accessors. We hand code
 * the opcodes in order not to depend on newer binutils
 */
static inline unsigned int mfdcrx(unsigned int reg)
{
	unsigned int ret;
	asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
		     : "=r" (ret) : "r" (reg));
	return ret;
}

static inline void mtdcrx(unsigned int reg, unsigned int val)
{
	asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
		     : : "r" (val), "r" (reg));
}

#define mfdcr(rn)						\
	({unsigned int rval;					\
	if (__builtin_constant_p(rn) && rn < 1024)		\
		asm volatile("mfdcr %0," __stringify(rn)	\
		              : "=r" (rval));			\
	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))	\
		rval = mfdcrx(rn);				\
	else							\
		rval = __mfdcr(rn);				\
	rval;})

#define mtdcr(rn, v)						\
do {								\
	if (__builtin_constant_p(rn) && rn < 1024)		\
		asm volatile("mtdcr " __stringify(rn) ",%0"	\
			      : : "r" (v)); 			\
	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))	\
		mtdcrx(rn, v);					\
	else							\
		__mtdcr(rn, v);					\
} while (0)

/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
extern spinlock_t dcr_ind_lock;

static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
{
	unsigned long flags;
	unsigned int val;

	spin_lock_irqsave(&dcr_ind_lock, flags);
	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
		mtdcrx(base_addr, reg);
		val = mfdcrx(base_data);
	} else {
		__mtdcr(base_addr, reg);
		val = __mfdcr(base_data);
	}
	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	return val;
}

static inline void __mtdcri(int base_addr, int base_data, int reg,
			    unsigned val)
{
	unsigned long flags;

	spin_lock_irqsave(&dcr_ind_lock, flags);
	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
		mtdcrx(base_addr, reg);
		mtdcrx(base_data, val);
	} else {
		__mtdcr(base_addr, reg);
		__mtdcr(base_data, val);
	}
	spin_unlock_irqrestore(&dcr_ind_lock, flags);
}

static inline void __dcri_clrset(int base_addr, int base_data, int reg,
				 unsigned clr, unsigned set)
{
	unsigned long flags;
	unsigned int val;

	spin_lock_irqsave(&dcr_ind_lock, flags);
	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
		mtdcrx(base_addr, reg);
		val = (mfdcrx(base_data) & ~clr) | set;
		mtdcrx(base_data, val);
	} else {
		__mtdcr(base_addr, reg);
		val = (__mfdcr(base_data) & ~clr) | set;
		__mtdcr(base_data, val);
	}
	spin_unlock_irqrestore(&dcr_ind_lock, flags);
}

#define mfdcri(base, reg)	__mfdcri(DCRN_ ## base ## _CONFIG_ADDR,	\
					 DCRN_ ## base ## _CONFIG_DATA,	\
					 reg)

#define mtdcri(base, reg, data)	__mtdcri(DCRN_ ## base ## _CONFIG_ADDR,	\
					 DCRN_ ## base ## _CONFIG_DATA,	\
					 reg, data)

#define dcri_clrset(base, reg, clr, set)	__dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,	\
							      DCRN_ ## base ## _CONFIG_DATA,	\
							      reg, clr, set)

#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_DCR_NATIVE_H */
Commit	Line	Data
4c75a6f4 BH	1	/*
	2	* (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
	3	* <benh@kernel.crashing.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	13	* the GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#ifndef _ASM_POWERPC_DCR_NATIVE_H
	21	#define _ASM_POWERPC_DCR_NATIVE_H
	22	#ifdef __KERNEL__
45d8e7aa	23	#ifndef __ASSEMBLY__
4c75a6f4	24
0e6140a5	25	#include <linux/spinlock.h>
6d2170be	26	#include <asm/cputable.h>
b92a226e	27	#include <asm/cpu_has_feature.h>
0e6140a5	28
0b94a1ee ME	29	typedef struct {
0b94a1ee ME	30	unsigned int base;
b786af11	31	} dcr_host_native_t;
4c75a6f4	32
b786af11 SN	33	static inline bool dcr_map_ok_native(dcr_host_native_t host)
b786af11 SN	34	{
acdb6685	35	return true;
b786af11	36	}
4c75a6f4	37
b786af11 SN	38	#define dcr_map_native(dev, dcr_n, dcr_c) \
	39	((dcr_host_native_t){ .base = (dcr_n) })
	40	#define dcr_unmap_native(host, dcr_c) do {} while (0)
	41	#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
	42	#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
4c75a6f4	43
6d2170be BH	44	/* Table based DCR accessors */
	45	extern void __mtdcr(unsigned int reg, unsigned int val);
	46	extern unsigned int __mfdcr(unsigned int reg);
	47
	48	/* mfdcrx/mtdcrx instruction based accessors. We hand code
	49	* the opcodes in order not to depend on newer binutils
	50	*/
	51	static inline unsigned int mfdcrx(unsigned int reg)
	52	{
	53	unsigned int ret;
	54	asm volatile(".long 0x7c000206 \| (%0 << 21) \| (%1 << 16)"
	55	: "=r" (ret) : "r" (reg));
	56	return ret;
	57	}
	58
	59	static inline void mtdcrx(unsigned int reg, unsigned int val)
	60	{
	61	asm volatile(".long 0x7c000306 \| (%0 << 21) \| (%1 << 16)"
	62	: : "r" (val), "r" (reg));
	63	}
	64
45d8e7aa KG	65	#define mfdcr(rn) \
45d8e7aa KG	66	({unsigned int rval; \
6d2170be	67	if (__builtin_constant_p(rn) && rn < 1024) \
45d8e7aa KG	68	asm volatile("mfdcr %0," __stringify(rn) \
45d8e7aa KG	69	: "=r" (rval)); \
6d2170be BH	70	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
6d2170be BH	71	rval = mfdcrx(rn); \
45d8e7aa KG	72	else \
	73	rval = __mfdcr(rn); \
	74	rval;})
	75
	76	#define mtdcr(rn, v) \
	77	do { \
6d2170be	78	if (__builtin_constant_p(rn) && rn < 1024) \
45d8e7aa KG	79	asm volatile("mtdcr " __stringify(rn) ",%0" \
45d8e7aa KG	80	: : "r" (v)); \
6d2170be BH	81	else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \
6d2170be BH	82	mtdcrx(rn, v); \
45d8e7aa KG	83	else \
	84	__mtdcr(rn, v); \
	85	} while (0)
	86
	87	/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
0e6140a5 BH	88	extern spinlock_t dcr_ind_lock;
0e6140a5 BH	89
e8318d98 VB	90	static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
	91	{
	92	unsigned long flags;
	93	unsigned int val;
45d8e7aa	94
e8318d98	95	spin_lock_irqsave(&dcr_ind_lock, flags);
6d2170be BH	96	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
	97	mtdcrx(base_addr, reg);
	98	val = mfdcrx(base_data);
	99	} else {
	100	__mtdcr(base_addr, reg);
	101	val = __mfdcr(base_data);
	102	}
e8318d98 VB	103	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	104	return val;
	105	}
	106
	107	static inline void __mtdcri(int base_addr, int base_data, int reg,
	108	unsigned val)
	109	{
	110	unsigned long flags;
	111
	112	spin_lock_irqsave(&dcr_ind_lock, flags);
6d2170be BH	113	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
	114	mtdcrx(base_addr, reg);
	115	mtdcrx(base_data, val);
	116	} else {
	117	__mtdcr(base_addr, reg);
	118	__mtdcr(base_data, val);
	119	}
e8318d98 VB	120	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	121	}
	122
266d028a VB	123	static inline void __dcri_clrset(int base_addr, int base_data, int reg,
	124	unsigned clr, unsigned set)
	125	{
	126	unsigned long flags;
	127	unsigned int val;
	128
	129	spin_lock_irqsave(&dcr_ind_lock, flags);
6d2170be BH	130	if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
	131	mtdcrx(base_addr, reg);
	132	val = (mfdcrx(base_data) & ~clr) \| set;
	133	mtdcrx(base_data, val);
	134	} else {
	135	__mtdcr(base_addr, reg);
	136	val = (__mfdcr(base_data) & ~clr) \| set;
	137	__mtdcr(base_data, val);
	138	}
266d028a VB	139	spin_unlock_irqrestore(&dcr_ind_lock, flags);
	140	}
	141
e8318d98 VB	142	#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
	143	DCRN_ ## base ## _CONFIG_DATA, \
	144	reg)
	145
	146	#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
	147	DCRN_ ## base ## _CONFIG_DATA, \
	148	reg, data)
4c75a6f4	149
266d028a VB	150	#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \
	151	DCRN_ ## base ## _CONFIG_DATA, \
	152	reg, clr, set)
	153
45d8e7aa	154	#endif /* __ASSEMBLY__ */
4c75a6f4 BH	155	#endif /* __KERNEL__ */
4c75a6f4 BH	156	#endif /* _ASM_POWERPC_DCR_NATIVE_H */