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powerpc/mm: Fixup tlbie vs store ordering issue on POWER9
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
10b35d99
KG		 2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
d1cdcf22 5
6574ba95 6#include <linux/types.h>
d1cdcf22 7#include <asm/asm-compat.h>
c5157e58 8#include <asm/feature-fixups.h>
c3617f72 9#include <uapi/asm/cputable.h>
d1cdcf22 10
10b35d99
KG		 11#ifndef __ASSEMBLY__
12
13/* This structure can grow, it's real size is used by head.S code
14 * via the mkdefs mechanism.
15 */
16struct cpu_spec;
10b35d99 17
10b35d99 18typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 19typedef void (*cpu_restore_t)(void);
10b35d99 20
32a33994 21enum powerpc_oprofile_type {
7a45fb19
AW		 22 PPC_OPROFILE_INVALID = 0,
23 PPC_OPROFILE_RS64 = 1,
24 PPC_OPROFILE_POWER4 = 2,
25 PPC_OPROFILE_G4 = 3,
39aef685 26 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 27 PPC_OPROFILE_CELL = 5,
25fc530e 28 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 29};
30
1bd2e5ae
OJ		 31enum powerpc_pmc_type {
32 PPC_PMC_DEFAULT = 0,
33 PPC_PMC_IBM = 1,
34 PPC_PMC_PA6T = 2,
b950bdd0 35 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 36};
37
47c0bd1a
BH		 38struct pt_regs;
39
40extern int machine_check_generic(struct pt_regs *regs);
41extern int machine_check_4xx(struct pt_regs *regs);
42extern int machine_check_440A(struct pt_regs *regs);
fe04b112 43extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 44extern int machine_check_e500(struct pt_regs *regs);
45extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 46extern int machine_check_47x(struct pt_regs *regs);
e627f8dc 47int machine_check_8xx(struct pt_regs *regs);
47c0bd1a 48
e7affb1d 49extern void cpu_down_flush_e500v2(void);
50extern void cpu_down_flush_e500mc(void);
51extern void cpu_down_flush_e5500(void);
52extern void cpu_down_flush_e6500(void);
53
87a72f9e 54/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 55struct cpu_spec {
56 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
57 unsigned int pvr_mask;
58 unsigned int pvr_value;
59
60 char *cpu_name;
61 unsigned long cpu_features; /* Kernel features */
62 unsigned int cpu_user_features; /* Userland features */
2171364d 63 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 64 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 65
66 /* cache line sizes */
67 unsigned int icache_bsize;
68 unsigned int dcache_bsize;
69
e7affb1d 70 /* flush caches inside the current cpu */
71 void (*cpu_down_flush)(void);
72
10b35d99
KG		 73 /* number of performance monitor counters */
74 unsigned int num_pmcs;
1bd2e5ae 75 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 76
77 /* this is called to initialize various CPU bits like L1 cache,
78 * BHT, SPD, etc... from head.S before branching to identify_machine
79 */
80 cpu_setup_t cpu_setup;
f39b7a55
OJ		 81 /* Used to restore cpu setup on secondary processors and at resume */
82 cpu_restore_t cpu_restore;
10b35d99
KG		 83
84 /* Used by oprofile userspace to select the right counters */
85 char *oprofile_cpu_type;
86
87 /* Processor specific oprofile operations */
32a33994 88 enum powerpc_oprofile_type oprofile_type;
80f15dc7 89
e78dbc80
MN		 90 /* Bit locations inside the mmcra change */
91 unsigned long oprofile_mmcra_sihv;
92 unsigned long oprofile_mmcra_sipr;
93
94 /* Bits to clear during an oprofile exception */
95 unsigned long oprofile_mmcra_clear;
96
80f15dc7
PM		 97 /* Name of processor class, for the ELF AT_PLATFORM entry */
98 char *platform;
47c0bd1a
BH		 99
100 /* Processor specific machine check handling. Return negative
101 * if the error is fatal, 1 if it was fully recovered and 0 to
102 * pass up (not CPU originated) */
103 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 104
105 /*
106 * Processor specific early machine check handler which is
107 * called in real mode to handle SLB and TLB errors.
108 */
109 long (*machine_check_early)(struct pt_regs *regs);
10b35d99
KG		 110};
111
10b35d99 112extern struct cpu_spec *cur_cpu_spec;
10b35d99 113
42c4aaad
BH		 114extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
115
5a61ef74 116extern void set_cur_cpu_spec(struct cpu_spec *s);
974a76f5 117extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
5a61ef74 118extern void identify_cpu_name(unsigned int pvr);
0909c8c2
BH		 119extern void do_feature_fixups(unsigned long value, void *fixup_start,
120 void *fixup_end);
9b6b563c 121
9115d134
NL		 122extern const char *powerpc_base_platform;
123
4db73271
KH		 124#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
125extern void cpu_feature_keys_init(void);
126#else
127static inline void cpu_feature_keys_init(void) { }
128#endif
129
10b35d99
KG		 130#endif /* __ASSEMBLY__ */
131
132/* CPU kernel features */
133
134/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 135#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
136#define CPU_FTR_L2CR ASM_CONST(0x00000002)
137#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
138#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
139#define CPU_FTR_TAU ASM_CONST(0x00000010)
140#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
141#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
142#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
143#define CPU_FTR_601 ASM_CONST(0x00000100)
144#define CPU_FTR_DBELL ASM_CONST(0x00000200)
145#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
146#define CPU_FTR_L3CR ASM_CONST(0x00000800)
147#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
148#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
149#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
150#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
151#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
152#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
153#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
154#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
155#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
156#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
157#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
158#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
159#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
160#define CPU_FTR_SPE ASM_CONST(0x02000000)
161#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
162#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
163#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
164#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
165#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 166
3965f8c5
PM		 167/*
168 * Add the 64-bit processor unique features in the top half of the word;
169 * on 32-bit, make the names available but defined to be 0.
170 */
10b35d99 171#ifdef __powerpc64__
3965f8c5 172#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 173#else
3965f8c5 174#define LONG_ASM_CONST(x) 0
10b35d99
KG		 175#endif
176
1580b3b8
MN		 177#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
178#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
179#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
1de2bd4e 180#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
c3ab300e 181#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
1580b3b8
MN		 182#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
183#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
184#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
185#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
186#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
187#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
188#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
189#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
190#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
191#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
192#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
193#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
194#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
195#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
196#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
197#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
cf43d3b2 198#define CPU_FTR_PKEY LONG_ASM_CONST(0x0020000000000000)
1580b3b8
MN		 199#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
200#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
1de2bd4e 201#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
1580b3b8 202#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
79879c17 203#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
82a9f16a 204#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
68f2f0d4 205#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
a5d4b589 206#define CPU_FTR_P9_TLBIE_BUG LONG_ASM_CONST(0x2000000000000000)
7dccfbc3 207#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
3ffa9d9e 208#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x8000000000000000)
3965f8c5 209
10b35d99
KG		 210#ifndef __ASSEMBLY__
211
44ae3ab3
ME		 212#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
213
13b3d13b 214#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
10b35d99
KG		 215
216/* We only set the altivec features if the kernel was compiled with altivec
217 * support
218 */
219#ifdef CONFIG_ALTIVEC
220#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
221#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
222#else
223#define CPU_FTR_ALTIVEC_COMP 0
224#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
225#endif
226
b962ce9d
MN		 227/* We only set the VSX features if the kernel was compiled with VSX
228 * support
229 */
230#ifdef CONFIG_VSX
231#define CPU_FTR_VSX_COMP CPU_FTR_VSX
232#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
233#else
234#define CPU_FTR_VSX_COMP 0
235#define PPC_FEATURE_HAS_VSX_COMP 0
236#endif
237
5e14d21e
KG		 238/* We only set the spe features if the kernel was compiled with spe
239 * support
240 */
241#ifdef CONFIG_SPE
242#define CPU_FTR_SPE_COMP CPU_FTR_SPE
243#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
244#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
245#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
246#else
247#define CPU_FTR_SPE_COMP 0
248#define PPC_FEATURE_HAS_SPE_COMP 0
249#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
250#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
251#endif
252
6a6d541f
MN		 253/* We only set the TM feature if the kernel was compiled with TM supprt */
254#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
b4b56f9e
S		 255#define CPU_FTR_TM_COMP CPU_FTR_TM
256#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
257#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
6a6d541f 258#else
b4b56f9e
S		 259#define CPU_FTR_TM_COMP 0
260#define PPC_FEATURE2_HTM_COMP 0
261#define PPC_FEATURE2_HTM_NOSC_COMP 0
6a6d541f
MN		 262#endif
263
11af1192
SW		 264/* We need to mark all pages as being coherent if we're SMP or we have a
265 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
266 * require it for PCI "streaming/prefetch" to work properly.
c9310920 267 * This is also required by 52xx family.
10b35d99 268 */
1775dbbc 269#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 270 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
271 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 272#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
273#else
274#define CPU_FTR_COMMON 0
275#endif
276
277/* The powersave features NAP & DOZE seems to confuse BDI when
278 debugging. So if a BDI is used, disable theses
279 */
280#ifndef CONFIG_BDI_SWITCH
281#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
282#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
283#else
284#define CPU_FTR_MAYBE_CAN_DOZE 0
285#define CPU_FTR_MAYBE_CAN_NAP 0
286#endif
287
7c03d653 288#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 289 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
290#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 292 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 293#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 294 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 295#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 296 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 298#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 300 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 301 CPU_FTR_PPC_LE)
4508dc21 302#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 304 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 305 CPU_FTR_PPC_LE)
7c03d653 306#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 307#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
308#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 309#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 310#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 311#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 312 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 313 CPU_FTR_ALTIVEC_COMP | \
fab5db97 314 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 315#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 316 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 317 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 318 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 319#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 320 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 321 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 322 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 323#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 324 CPU_FTR_USE_TB | \
325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 327 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 329#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 330 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 334#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 335 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 336 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 337 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 338#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 339 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 341 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 342 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 343 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 344#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 345 CPU_FTR_USE_TB | \
346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 347 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 348 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 349#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 350 CPU_FTR_USE_TB | \
351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 353 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
354 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 355#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 356 CPU_FTR_USE_TB | \
357 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 358 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 359 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 360#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 361 CPU_FTR_USE_TB | \
362 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 363 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 364 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 365#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 366 CPU_FTR_USE_TB | \
367 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 368 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 369 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 370#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 371 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 372#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 373 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 374#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 375 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 376 CPU_FTR_COMMON)
4508dc21 377#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 378 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 379 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 380#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
5b2753fc 381#define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
8309ce72
BH		 382#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
383#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 384#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
385 CPU_FTR_INDEXED_DCR)
e7f75ad0 386#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 387#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
388 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 389 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
390 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 391#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 392 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
393 CPU_FTR_NOEXECUTE)
fc4033b2 394#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 395 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 396 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 397#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 398 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 399 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 400/*
401 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
402 * same workaround as CPU_FTR_CELL_TB_BUG.
403 */
11ed0db9
KG		 404#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
405 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 406 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 407 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
10241842
KG		 408#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
409 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
410 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 411 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 412 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
7c92943c 413#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 414
415/* 64-bit CPUs */
2d1b2027 416#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 418 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
419 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 420#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 422 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 423 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 424 CPU_FTR_HVMODE | CPU_FTR_DABRX)
2d1b2027 425#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 427 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 428 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 429 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
2d1b2027 430#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 432 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 433 CPU_FTR_COHERENT_ICACHE | \
4c198557 434 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 435 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 436 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
437 CPU_FTR_DABRX)
2d1b2027 438#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 439 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 440 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 441 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 442 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 443 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 444 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 445 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
cf43d3b2 446 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)
71e18497
MN		 447#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
449 CPU_FTR_MMCRA | CPU_FTR_SMT | \
450 CPU_FTR_COHERENT_ICACHE | \
451 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
452 CPU_FTR_DSCR | CPU_FTR_SAO | \
453 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 454 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e 455 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
cf43d3b2 456 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)
68f2f0d4 457#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
bd6ba351 458#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
c3ab300e
MN		 459#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
460 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
461 CPU_FTR_MMCRA | CPU_FTR_SMT | \
462 CPU_FTR_COHERENT_ICACHE | \
463 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
464 CPU_FTR_DSCR | CPU_FTR_SAO | \
465 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
2384d2d7 466 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
c3ab300e 467 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
cf43d3b2 468 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | \
a5d4b589 469 CPU_FTR_PKEY | CPU_FTR_P9_TLBIE_BUG)
ca80d5d0
NP		 470#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
471 (~CPU_FTR_SAO))
3ffa9d9e
ME		 472#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
473#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
2d1b2027 474#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 475 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 476 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 477 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 478 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
2d1b2027 479#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3 480 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 481 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
7c03d653 482#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 483
2406f606 484#ifdef __powerpc64__
11ed0db9 485#ifdef CONFIG_PPC_BOOK3E
90029640 486#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 487#else
7c92943c 488#define CPU_FTRS_POSSIBLE \
468a3302
ME		 489 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
490 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
3609e09f 491 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
b6b3755e 492 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | \
3ffa9d9e 493 CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1)
11ed0db9 494#endif
2406f606 495#else
7c92943c
SR		 496enum {
497 CPU_FTRS_POSSIBLE =
1e07a0a0 498#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 499 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
500 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
501 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
502 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
503 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
504 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
505 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 506 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
507 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 508#else
509 CPU_FTRS_GENERIC_32 |
510#endif
968159c0 511#ifdef CONFIG_PPC_8xx
10b35d99
KG		 512 CPU_FTRS_8XX |
513#endif
514#ifdef CONFIG_40x
515 CPU_FTRS_40X |
516#endif
517#ifdef CONFIG_44x
6d2170be 518 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 519#endif
e7f75ad0 520#ifdef CONFIG_PPC_47x
c48d0dba 521 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 522#endif
10b35d99
KG		 523#ifdef CONFIG_E200
524 CPU_FTRS_E200 |
525#endif
526#ifdef CONFIG_E500
06aae867
SW		 527 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
528#endif
529#ifdef CONFIG_PPC_E500MC
530 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 531#endif
10b35d99 532 0,
7c92943c
SR		 533};
534#endif /* __powerpc64__ */
10b35d99 535
2406f606 536#ifdef __powerpc64__
11ed0db9 537#ifdef CONFIG_PPC_BOOK3E
90029640 538#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 539#else
7c92943c 540#define CPU_FTRS_ALWAYS \
468a3302
ME		 541 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
542 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 543 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
c3ab300e
MN		 544 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
545 CPU_FTRS_POWER9)
11ed0db9 546#endif
2406f606 547#else
7c92943c
SR		 548enum {
549 CPU_FTRS_ALWAYS =
1e07a0a0 550#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 551 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
552 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
553 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
554 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
555 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
556 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
557 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 558 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
559 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 560#else
561 CPU_FTRS_GENERIC_32 &
562#endif
968159c0 563#ifdef CONFIG_PPC_8xx
10b35d99
KG		 564 CPU_FTRS_8XX &
565#endif
566#ifdef CONFIG_40x
567 CPU_FTRS_40X &
568#endif
569#ifdef CONFIG_44x
6d2170be 570 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 571#endif
572#ifdef CONFIG_E200
573 CPU_FTRS_E200 &
574#endif
575#ifdef CONFIG_E500
06aae867
SW		 576 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
577#endif
578#ifdef CONFIG_PPC_E500MC
579 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 580#endif
73196cd3 581 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 582 CPU_FTRS_POSSIBLE,
583};
7c92943c 584#endif /* __powerpc64__ */
10b35d99 585
5aae8a53 586#define HBP_NUM 1
5aae8a53 587
10b35d99
KG		 588#endif /* !__ASSEMBLY__ */
589
10b35d99 590#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)