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powerpc: Retire e200 core (mpc555x processor)
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
10b35d99
KG		 2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
d1cdcf22 5
6574ba95 6#include <linux/types.h>
c3617f72 7#include <uapi/asm/cputable.h>
ec0c464c 8#include <asm/asm-const.h>
d1cdcf22 9
10b35d99
KG		 10#ifndef __ASSEMBLY__
11
12/* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15struct cpu_spec;
10b35d99 16
10b35d99 17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 18typedef void (*cpu_restore_t)(void);
10b35d99 19
32a33994 20enum powerpc_oprofile_type {
7a45fb19
AW		 21 PPC_OPROFILE_INVALID = 0,
22 PPC_OPROFILE_RS64 = 1,
23 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_G4 = 3,
39aef685 25 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 26 PPC_OPROFILE_CELL = 5,
25fc530e 27 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 28};
29
1bd2e5ae
OJ		 30enum powerpc_pmc_type {
31 PPC_PMC_DEFAULT = 0,
32 PPC_PMC_IBM = 1,
33 PPC_PMC_PA6T = 2,
b950bdd0 34 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 35};
36
47c0bd1a
BH		 37struct pt_regs;
38
39extern int machine_check_generic(struct pt_regs *regs);
40extern int machine_check_4xx(struct pt_regs *regs);
41extern int machine_check_440A(struct pt_regs *regs);
fe04b112 42extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a 43extern int machine_check_e500(struct pt_regs *regs);
fc5e7097 44extern int machine_check_47x(struct pt_regs *regs);
e627f8dc 45int machine_check_8xx(struct pt_regs *regs);
0deae39c 46int machine_check_83xx(struct pt_regs *regs);
47c0bd1a 47
e7affb1d 48extern void cpu_down_flush_e500v2(void);
49extern void cpu_down_flush_e500mc(void);
50extern void cpu_down_flush_e5500(void);
51extern void cpu_down_flush_e6500(void);
52
87a72f9e 53/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 54struct cpu_spec {
55 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
56 unsigned int pvr_mask;
57 unsigned int pvr_value;
58
59 char *cpu_name;
60 unsigned long cpu_features; /* Kernel features */
61 unsigned int cpu_user_features; /* Userland features */
2171364d 62 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 63 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 64
65 /* cache line sizes */
66 unsigned int icache_bsize;
67 unsigned int dcache_bsize;
68
e7affb1d 69 /* flush caches inside the current cpu */
70 void (*cpu_down_flush)(void);
71
10b35d99
KG		 72 /* number of performance monitor counters */
73 unsigned int num_pmcs;
1bd2e5ae 74 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 75
76 /* this is called to initialize various CPU bits like L1 cache,
77 * BHT, SPD, etc... from head.S before branching to identify_machine
78 */
79 cpu_setup_t cpu_setup;
f39b7a55
OJ		 80 /* Used to restore cpu setup on secondary processors and at resume */
81 cpu_restore_t cpu_restore;
10b35d99
KG		 82
83 /* Used by oprofile userspace to select the right counters */
84 char *oprofile_cpu_type;
85
86 /* Processor specific oprofile operations */
32a33994 87 enum powerpc_oprofile_type oprofile_type;
80f15dc7 88
e78dbc80
MN		 89 /* Bit locations inside the mmcra change */
90 unsigned long oprofile_mmcra_sihv;
91 unsigned long oprofile_mmcra_sipr;
92
93 /* Bits to clear during an oprofile exception */
94 unsigned long oprofile_mmcra_clear;
95
80f15dc7
PM		 96 /* Name of processor class, for the ELF AT_PLATFORM entry */
97 char *platform;
47c0bd1a
BH		 98
99 /* Processor specific machine check handling. Return negative
100 * if the error is fatal, 1 if it was fully recovered and 0 to
101 * pass up (not CPU originated) */
102 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 103
104 /*
105 * Processor specific early machine check handler which is
106 * called in real mode to handle SLB and TLB errors.
107 */
108 long (*machine_check_early)(struct pt_regs *regs);
10b35d99
KG		 109};
110
10b35d99 111extern struct cpu_spec *cur_cpu_spec;
10b35d99 112
42c4aaad
BH		 113extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
114
5a61ef74 115extern void set_cur_cpu_spec(struct cpu_spec *s);
974a76f5 116extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
5a61ef74 117extern void identify_cpu_name(unsigned int pvr);
0909c8c2
BH		 118extern void do_feature_fixups(unsigned long value, void *fixup_start,
119 void *fixup_end);
9b6b563c 120
9115d134
NL		 121extern const char *powerpc_base_platform;
122
4db73271
KH		 123#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
124extern void cpu_feature_keys_init(void);
125#else
126static inline void cpu_feature_keys_init(void) { }
127#endif
128
10b35d99
KG		 129#endif /* __ASSEMBLY__ */
130
131/* CPU kernel features */
132
9bbf0b57 133/* Definitions for features that we have on both 32-bit and 64-bit chips */
cde4d494 134#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
9bbf0b57
PM		 135#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
136#define CPU_FTR_DBELL ASM_CONST(0x00000004)
137#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
138#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
7d470345 139// ASM_CONST(0x00000020) Free
9bbf0b57
PM		 140#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
141#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
142#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
143#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
144
145/* Definitions for features that only exist on 32-bit chips */
146#ifdef CONFIG_PPC32
9bbf0b57
PM		 147#define CPU_FTR_L2CR ASM_CONST(0x00002000)
148#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
149#define CPU_FTR_TAU ASM_CONST(0x00008000)
150#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
9bbf0b57
PM		 151#define CPU_FTR_L3CR ASM_CONST(0x00040000)
152#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
153#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
154#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
155#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
156#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
157#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
158#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
159#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
9bbf0b57
PM		 160#define CPU_FTR_SPE ASM_CONST(0x10000000)
161#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
162#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
163
164#else /* CONFIG_PPC32 */
165/* Define these to 0 for the sake of tests in common code */
9bbf0b57 166#define CPU_FTR_PPC_LE (0)
532ed190 167#define CPU_FTR_SPE (0)
9bbf0b57 168#endif
10b35d99 169
3965f8c5 170/*
9bbf0b57 171 * Definitions for the 64-bit processor unique features;
3965f8c5
PM		 172 * on 32-bit, make the names available but defined to be 0.
173 */
10b35d99 174#ifdef __powerpc64__
3965f8c5 175#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 176#else
3965f8c5 177#define LONG_ASM_CONST(x) 0
10b35d99
KG		 178#endif
179
9bbf0b57
PM		 180#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
181#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
9bbf0b57
PM		 182#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
183#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
184#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
185#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
186#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
187#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
188#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
189#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
190#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
191#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
192#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
12564485 194#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
9bbf0b57
PM		 195#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
196#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
197#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
198#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
199#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
200#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
a24204c3 201/* LONG_ASM_CONST(0x0000000400000000) Free */
9bbf0b57
PM		 202#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
203#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
204#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
205#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
206#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
207#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
208#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
9bbf0b57 209#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
b5af4f27
PM		 210#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
211#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
09ce98ca 212#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
81984428 213#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
047e6575 214#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
736bcdd3 215#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
3fd5836e 216#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
dc1cedca 217#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
3965f8c5 218
10b35d99
KG		 219#ifndef __ASSEMBLY__
220
7d470345 221#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE)
44ae3ab3 222
10b35d99
KG		 223/* We only set the altivec features if the kernel was compiled with altivec
224 * support
225 */
226#ifdef CONFIG_ALTIVEC
227#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
228#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
229#else
230#define CPU_FTR_ALTIVEC_COMP 0
231#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
232#endif
233
b962ce9d
MN		 234/* We only set the VSX features if the kernel was compiled with VSX
235 * support
236 */
237#ifdef CONFIG_VSX
238#define CPU_FTR_VSX_COMP CPU_FTR_VSX
239#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
240#else
241#define CPU_FTR_VSX_COMP 0
242#define PPC_FEATURE_HAS_VSX_COMP 0
243#endif
244
5e14d21e
KG		 245/* We only set the spe features if the kernel was compiled with spe
246 * support
247 */
248#ifdef CONFIG_SPE
249#define CPU_FTR_SPE_COMP CPU_FTR_SPE
250#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
251#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
252#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
253#else
254#define CPU_FTR_SPE_COMP 0
255#define PPC_FEATURE_HAS_SPE_COMP 0
256#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
257#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
258#endif
259
6a6d541f
MN		 260/* We only set the TM feature if the kernel was compiled with TM supprt */
261#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
b4b56f9e
S		 262#define CPU_FTR_TM_COMP CPU_FTR_TM
263#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
264#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
6a6d541f 265#else
b4b56f9e
S		 266#define CPU_FTR_TM_COMP 0
267#define PPC_FEATURE2_HTM_COMP 0
268#define PPC_FEATURE2_HTM_NOSC_COMP 0
6a6d541f
MN		 269#endif
270
11af1192
SW		 271/* We need to mark all pages as being coherent if we're SMP or we have a
272 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
273 * require it for PCI "streaming/prefetch" to work properly.
c9310920 274 * This is also required by 52xx family.
10b35d99 275 */
1775dbbc 276#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 277 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
278 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 279#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
280#else
281#define CPU_FTR_COMMON 0
282#endif
283
284/* The powersave features NAP & DOZE seems to confuse BDI when
285 debugging. So if a BDI is used, disable theses
286 */
287#ifndef CONFIG_BDI_SWITCH
288#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
289#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
290#else
291#define CPU_FTR_MAYBE_CAN_DOZE 0
292#define CPU_FTR_MAYBE_CAN_NAP 0
293#endif
294
c0d64cf9 295#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
385e89d5 296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
c0d64cf9 297#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
4508dc21 298#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
c0d64cf9 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 301#define CPU_FTRS_740 (CPU_FTR_COMMON | \
c0d64cf9 302 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 303 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 304 CPU_FTR_PPC_LE)
4508dc21 305#define CPU_FTRS_750 (CPU_FTR_COMMON | \
c0d64cf9 306 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 307 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 308 CPU_FTR_PPC_LE)
7c03d653 309#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 310#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
311#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 312#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 313#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 314#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
c0d64cf9 315 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 316 CPU_FTR_ALTIVEC_COMP | \
fab5db97 317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 318#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
c0d64cf9 319 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 320 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 321 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 322#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
c0d64cf9 323 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 324 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 325 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 326#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c 327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 329 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 331#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
c0d64cf9 332 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 335 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 336#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
c0d64cf9 337 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 338 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 339 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 340#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
c0d64cf9 341 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 343 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 344 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 345 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 346#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c 347 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 348 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 349 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 350#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c 351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 353 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
354 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 355#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c 356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 357 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 358 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 359#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c 360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 361 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 362 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 363#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548 364 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 365 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 366 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
385e89d5 367#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
11af1192 368#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
197493af 369 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
4508dc21 370#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 371 CPU_FTR_MAYBE_CAN_NAP | \
385e89d5 372 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
4508dc21 373#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 374 CPU_FTR_MAYBE_CAN_NAP | \
385e89d5 375 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
c0d64cf9
PM		 376#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
377#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
7d470345
CL		 378#define CPU_FTRS_40X (CPU_FTR_NOEXECUTE)
379#define CPU_FTRS_44X (CPU_FTR_NOEXECUTE)
380#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \
6d2170be 381 CPU_FTR_INDEXED_DCR)
e7f75ad0 382#define CPU_FTRS_47X (CPU_FTRS_440x6)
c0d64cf9 383#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
7d470345 384 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 385 CPU_FTR_NOEXECUTE)
c0d64cf9 386#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 387 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
7d470345
CL		 388 CPU_FTR_NOEXECUTE)
389#define CPU_FTRS_E500MC ( \
dd0efb3f 390 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 391 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 392/*
393 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
394 * same workaround as CPU_FTR_CELL_TB_BUG.
395 */
7d470345 396#define CPU_FTRS_E5500 ( \
dd0efb3f 397 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 398 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 399 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
7d470345 400#define CPU_FTRS_E6500 ( \
dd0efb3f 401 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
10241842 402 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 403 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 404 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
0b8e2e13
ME		 405
406/* 64-bit CPUs */
c0d64cf9 407#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
3735eb85 408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
2a929436 409 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 410 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 411 CPU_FTR_HVMODE | CPU_FTR_DABRX)
c0d64cf9 412#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
7c03d653 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 414 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 415 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 416 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
c0d64cf9 417#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
7c03d653 418 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 419 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 420 CPU_FTR_COHERENT_ICACHE | \
4c198557 421 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 422 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 423 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
424 CPU_FTR_DABRX)
c0d64cf9 425#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
969391c5 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 427 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 428 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 429 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 430 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 431 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 432 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
a24204c3 433 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
c0d64cf9 434#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
71e18497
MN		 435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
436 CPU_FTR_MMCRA | CPU_FTR_SMT | \
437 CPU_FTR_COHERENT_ICACHE | \
438 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 439 CPU_FTR_DSCR | CPU_FTR_SAO | \
71e18497 440 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 441 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e 442 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
a24204c3 443 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
68f2f0d4 444#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
c0d64cf9 445#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
c3ab300e
MN		 446 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
447 CPU_FTR_MMCRA | CPU_FTR_SMT | \
448 CPU_FTR_COHERENT_ICACHE | \
449 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 450 CPU_FTR_DSCR | CPU_FTR_SAO | \
c3ab300e 451 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
2384d2d7 452 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
96541531 453 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
a24204c3
AK		 454 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
455 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
736bcdd3
JN		 456#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
457#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
458 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
459 CPU_FTR_POWER9_DD2_1)
3a52f601
NP		 460#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
461 CPU_FTR_P9_TM_HV_ASSIST | \
b5af4f27 462 CPU_FTR_P9_TM_XER_SO_BUG)
a3ea40d5
AP		 463#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
464 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
465 CPU_FTR_MMCRA | CPU_FTR_SMT | \
466 CPU_FTR_COHERENT_ICACHE | \
467 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 468 CPU_FTR_DSCR | CPU_FTR_SAO | \
a3ea40d5
AP		 469 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
470 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
471 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
ec613a57 472 CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
dc1cedca 473 CPU_FTR_DAWR | CPU_FTR_DAWR1)
c0d64cf9 474#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
7c03d653 475 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 476 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 477 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 478 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
c0d64cf9 479#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
44ae3ab3 480 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 481 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
c0d64cf9 482#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
10b35d99 483
8d1eeabf 484#ifdef CONFIG_PPC64
11ed0db9 485#ifdef CONFIG_PPC_BOOK3E
90029640 486#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 487#else
db5ae1c1
NP		 488#ifdef CONFIG_CPU_LITTLE_ENDIAN
489#define CPU_FTRS_POSSIBLE \
490 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
e11b64b1 491 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
a3ea40d5 492 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
db5ae1c1 493#else
7c92943c 494#define CPU_FTRS_POSSIBLE \
471d7ff8 495 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
468a3302 496 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
e11b64b1
JS		 497 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
498 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
a3ea40d5 499 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
db5ae1c1 500#endif /* CONFIG_CPU_LITTLE_ENDIAN */
11ed0db9 501#endif
2406f606 502#else
7c92943c
SR		 503enum {
504 CPU_FTRS_POSSIBLE =
8b14e1df
CL		 505#ifdef CONFIG_PPC_BOOK3S_32
506 CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
10b35d99
KG		 507 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
508 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
509 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
510 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
511 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
512 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 513 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
514 CPU_FTRS_CLASSIC32 |
10b35d99 515#endif
968159c0 516#ifdef CONFIG_PPC_8xx
10b35d99
KG		 517 CPU_FTRS_8XX |
518#endif
519#ifdef CONFIG_40x
520 CPU_FTRS_40X |
521#endif
e7f75ad0 522#ifdef CONFIG_PPC_47x
c48d0dba 523 CPU_FTRS_47X | CPU_FTR_476_DD2 |
8b8319b1
CL		 524#elif defined(CONFIG_44x)
525 CPU_FTRS_44X | CPU_FTRS_440x6 |
e7f75ad0 526#endif
10b35d99 527#ifdef CONFIG_E500
06aae867
SW		 528 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
529#endif
530#ifdef CONFIG_PPC_E500MC
531 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 532#endif
10b35d99 533 0,
7c92943c
SR		 534};
535#endif /* __powerpc64__ */
10b35d99 536
8d1eeabf 537#ifdef CONFIG_PPC64
11ed0db9 538#ifdef CONFIG_PPC_BOOK3E
90029640 539#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 540#else
81b654c2
ME		 541
542#ifdef CONFIG_PPC_DT_CPU_FTRS
543#define CPU_FTRS_DT_CPU_BASE \
544 (CPU_FTR_LWSYNC | \
545 CPU_FTR_FPU_UNAVAILABLE | \
81b654c2
ME		 546 CPU_FTR_NOEXECUTE | \
547 CPU_FTR_COHERENT_ICACHE | \
548 CPU_FTR_STCX_CHECKS_ADDRESS | \
549 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
550 CPU_FTR_DAWR | \
551 CPU_FTR_ARCH_206 | \
552 CPU_FTR_ARCH_207S)
553#else
554#define CPU_FTRS_DT_CPU_BASE (~0ul)
555#endif
556
db5ae1c1
NP		 557#ifdef CONFIG_CPU_LITTLE_ENDIAN
558#define CPU_FTRS_ALWAYS \
559 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
ce57c661
ME		 560 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
561 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
db5ae1c1 562#else
7c92943c 563#define CPU_FTRS_ALWAYS \
471d7ff8 564 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
468a3302 565 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 566 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
ce57c661
ME		 567 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
568 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
db5ae1c1 569#endif /* CONFIG_CPU_LITTLE_ENDIAN */
11ed0db9 570#endif
2406f606 571#else
7c92943c
SR		 572enum {
573 CPU_FTRS_ALWAYS =
8b14e1df 574#ifdef CONFIG_PPC_BOOK3S_32
12c3f1fd 575 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
10b35d99
KG		 576 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
577 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
578 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
579 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
580 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
581 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 582 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
583 CPU_FTRS_CLASSIC32 &
10b35d99 584#endif
968159c0 585#ifdef CONFIG_PPC_8xx
10b35d99
KG		 586 CPU_FTRS_8XX &
587#endif
588#ifdef CONFIG_40x
589 CPU_FTRS_40X &
590#endif
8b8319b1
CL		 591#ifdef CONFIG_PPC_47x
592 CPU_FTRS_47X &
593#elif defined(CONFIG_44x)
6d2170be 594 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99 595#endif
10b35d99 596#ifdef CONFIG_E500
06aae867
SW		 597 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
598#endif
599#ifdef CONFIG_PPC_E500MC
600 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 601#endif
73196cd3 602 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 603 CPU_FTRS_POSSIBLE,
604};
7c92943c 605#endif /* __powerpc64__ */
10b35d99 606
a6ba44e8
RB		 607/*
608 * Maximum number of hw breakpoint supported on powerpc. Number of
deb2bd9b
RB		 609 * breakpoints supported by actual hw might be less than this, which
610 * is decided at run time in nr_wp_slots().
a6ba44e8 611 */
deb2bd9b 612#define HBP_NUM_MAX 2
5aae8a53 613
10b35d99
KG		 614#endif /* !__ASSEMBLY__ */
615
10b35d99 616#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)