projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
powerpc: Enable the DAWR on POWER9 DD2.3 and above
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
10b35d99
KG		 2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
d1cdcf22 5
6574ba95 6#include <linux/types.h>
c3617f72 7#include <uapi/asm/cputable.h>
ec0c464c 8#include <asm/asm-const.h>
d1cdcf22 9
10b35d99
KG		 10#ifndef __ASSEMBLY__
11
12/* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15struct cpu_spec;
10b35d99 16
10b35d99 17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 18typedef void (*cpu_restore_t)(void);
10b35d99 19
1bd2e5ae
OJ		 20enum powerpc_pmc_type {
21 PPC_PMC_DEFAULT = 0,
22 PPC_PMC_IBM = 1,
23 PPC_PMC_PA6T = 2,
b950bdd0 24 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 25};
26
47c0bd1a
BH		 27struct pt_regs;
28
29extern int machine_check_generic(struct pt_regs *regs);
30extern int machine_check_4xx(struct pt_regs *regs);
31extern int machine_check_440A(struct pt_regs *regs);
fe04b112 32extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a 33extern int machine_check_e500(struct pt_regs *regs);
fc5e7097 34extern int machine_check_47x(struct pt_regs *regs);
e627f8dc 35int machine_check_8xx(struct pt_regs *regs);
0deae39c 36int machine_check_83xx(struct pt_regs *regs);
47c0bd1a 37
e7affb1d 38extern void cpu_down_flush_e500v2(void);
39extern void cpu_down_flush_e500mc(void);
40extern void cpu_down_flush_e5500(void);
41extern void cpu_down_flush_e6500(void);
42
87a72f9e 43/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 44struct cpu_spec {
45 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
46 unsigned int pvr_mask;
47 unsigned int pvr_value;
48
49 char *cpu_name;
50 unsigned long cpu_features; /* Kernel features */
51 unsigned int cpu_user_features; /* Userland features */
2171364d 52 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 53 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 54
55 /* cache line sizes */
56 unsigned int icache_bsize;
57 unsigned int dcache_bsize;
58
e7affb1d 59 /* flush caches inside the current cpu */
60 void (*cpu_down_flush)(void);
61
10b35d99
KG		 62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
1bd2e5ae 64 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
f39b7a55
OJ		 70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
10b35d99
KG		 72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
80f15dc7
PM		 76 /* Name of processor class, for the ELF AT_PLATFORM entry */
77 char *platform;
47c0bd1a
BH		 78
79 /* Processor specific machine check handling. Return negative
80 * if the error is fatal, 1 if it was fully recovered and 0 to
81 * pass up (not CPU originated) */
82 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 83
84 /*
85 * Processor specific early machine check handler which is
86 * called in real mode to handle SLB and TLB errors.
87 */
88 long (*machine_check_early)(struct pt_regs *regs);
10b35d99
KG		 89};
90
10b35d99 91extern struct cpu_spec *cur_cpu_spec;
10b35d99 92
42c4aaad
BH		 93extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
94
5a61ef74 95extern void set_cur_cpu_spec(struct cpu_spec *s);
974a76f5 96extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
5a61ef74 97extern void identify_cpu_name(unsigned int pvr);
0909c8c2
BH		 98extern void do_feature_fixups(unsigned long value, void *fixup_start,
99 void *fixup_end);
9b6b563c 100
9115d134
NL		 101extern const char *powerpc_base_platform;
102
4db73271
KH		 103#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
104extern void cpu_feature_keys_init(void);
105#else
106static inline void cpu_feature_keys_init(void) { }
107#endif
108
10b35d99
KG		 109#endif /* __ASSEMBLY__ */
110
111/* CPU kernel features */
112
9bbf0b57 113/* Definitions for features that we have on both 32-bit and 64-bit chips */
cde4d494 114#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
9bbf0b57
PM		 115#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
116#define CPU_FTR_DBELL ASM_CONST(0x00000004)
117#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
118#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
7d470345 119// ASM_CONST(0x00000020) Free
9bbf0b57
PM		 120#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
121#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
122#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
123#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
124
125/* Definitions for features that only exist on 32-bit chips */
126#ifdef CONFIG_PPC32
9bbf0b57
PM		 127#define CPU_FTR_L2CR ASM_CONST(0x00002000)
128#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
129#define CPU_FTR_TAU ASM_CONST(0x00008000)
130#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
9bbf0b57
PM		 131#define CPU_FTR_L3CR ASM_CONST(0x00040000)
132#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
133#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
134#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
135#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
136#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
137#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
138#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
139#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
9bbf0b57
PM		 140#define CPU_FTR_SPE ASM_CONST(0x10000000)
141#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
142#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
143
144#else /* CONFIG_PPC32 */
145/* Define these to 0 for the sake of tests in common code */
9bbf0b57 146#define CPU_FTR_PPC_LE (0)
532ed190 147#define CPU_FTR_SPE (0)
9bbf0b57 148#endif
10b35d99 149
3965f8c5 150/*
9bbf0b57 151 * Definitions for the 64-bit processor unique features;
3965f8c5
PM		 152 * on 32-bit, make the names available but defined to be 0.
153 */
10b35d99 154#ifdef __powerpc64__
3965f8c5 155#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 156#else
3965f8c5 157#define LONG_ASM_CONST(x) 0
10b35d99
KG		 158#endif
159
9bbf0b57
PM		 160#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
161#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
9bbf0b57
PM		 162#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
163#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
164#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
165#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
166#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
167#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
168#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
169#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
170#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
171#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
172#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
173#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
12564485 174#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
9bbf0b57
PM		 175#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
176#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
177#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
178#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
179#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
180#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
a24204c3 181/* LONG_ASM_CONST(0x0000000400000000) Free */
9bbf0b57
PM		 182#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
183#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
184#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
185#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
186#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
187#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
188#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
9bbf0b57 189#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
b5af4f27
PM		 190#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
191#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
09ce98ca 192#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
81984428 193#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
047e6575 194#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
736bcdd3 195#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
3fd5836e 196#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
dc1cedca 197#define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
3965f8c5 198
10b35d99
KG		 199#ifndef __ASSEMBLY__
200
7d470345 201#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE)
44ae3ab3 202
10b35d99
KG		 203/* We only set the altivec features if the kernel was compiled with altivec
204 * support
205 */
206#ifdef CONFIG_ALTIVEC
207#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
208#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
209#else
210#define CPU_FTR_ALTIVEC_COMP 0
211#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
212#endif
213
b962ce9d
MN		 214/* We only set the VSX features if the kernel was compiled with VSX
215 * support
216 */
217#ifdef CONFIG_VSX
218#define CPU_FTR_VSX_COMP CPU_FTR_VSX
219#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
220#else
221#define CPU_FTR_VSX_COMP 0
222#define PPC_FEATURE_HAS_VSX_COMP 0
223#endif
224
5e14d21e
KG		 225/* We only set the spe features if the kernel was compiled with spe
226 * support
227 */
228#ifdef CONFIG_SPE
229#define CPU_FTR_SPE_COMP CPU_FTR_SPE
230#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
231#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
232#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
233#else
234#define CPU_FTR_SPE_COMP 0
235#define PPC_FEATURE_HAS_SPE_COMP 0
236#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
237#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
238#endif
239
6a6d541f
MN		 240/* We only set the TM feature if the kernel was compiled with TM supprt */
241#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
b4b56f9e
S		 242#define CPU_FTR_TM_COMP CPU_FTR_TM
243#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
244#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
6a6d541f 245#else
b4b56f9e
S		 246#define CPU_FTR_TM_COMP 0
247#define PPC_FEATURE2_HTM_COMP 0
248#define PPC_FEATURE2_HTM_NOSC_COMP 0
6a6d541f
MN		 249#endif
250
11af1192
SW		 251/* We need to mark all pages as being coherent if we're SMP or we have a
252 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
253 * require it for PCI "streaming/prefetch" to work properly.
c9310920 254 * This is also required by 52xx family.
10b35d99 255 */
1775dbbc 256#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 257 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
258 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 259#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
260#else
261#define CPU_FTR_COMMON 0
262#endif
263
264/* The powersave features NAP & DOZE seems to confuse BDI when
265 debugging. So if a BDI is used, disable theses
266 */
267#ifndef CONFIG_BDI_SWITCH
268#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
269#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
270#else
271#define CPU_FTR_MAYBE_CAN_DOZE 0
272#define CPU_FTR_MAYBE_CAN_NAP 0
273#endif
274
c0d64cf9 275#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
385e89d5 276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
c0d64cf9 277#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
4508dc21 278#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
c0d64cf9 279 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 281#define CPU_FTRS_740 (CPU_FTR_COMMON | \
c0d64cf9 282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 283 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 284 CPU_FTR_PPC_LE)
4508dc21 285#define CPU_FTRS_750 (CPU_FTR_COMMON | \
c0d64cf9 286 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 287 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 288 CPU_FTR_PPC_LE)
7c03d653 289#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 290#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
291#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 292#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 293#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 294#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
c0d64cf9 295 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 296 CPU_FTR_ALTIVEC_COMP | \
fab5db97 297 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 298#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
c0d64cf9 299 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 300 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 302#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
c0d64cf9 303 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 304 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 305 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 306#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c 307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 308 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 311#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
c0d64cf9 312 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
c0d64cf9 317 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 318 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 319 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 320#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
c0d64cf9 321 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 323 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 324 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 325 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 326#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c 327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 330#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c 331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 333 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
334 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 335#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c 336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 338 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 339#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c 340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 341 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 342 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 343#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548 344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 345 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 346 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
385e89d5 347#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
11af1192 348#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
197493af 349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NOEXECUTE)
4508dc21 350#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 351 CPU_FTR_MAYBE_CAN_NAP | \
385e89d5 352 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
4508dc21 353#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 354 CPU_FTR_MAYBE_CAN_NAP | \
385e89d5 355 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
c0d64cf9
PM		 356#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
357#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
7d470345
CL		 358#define CPU_FTRS_40X (CPU_FTR_NOEXECUTE)
359#define CPU_FTRS_44X (CPU_FTR_NOEXECUTE)
360#define CPU_FTRS_440x6 (CPU_FTR_NOEXECUTE | \
6d2170be 361 CPU_FTR_INDEXED_DCR)
e7f75ad0 362#define CPU_FTRS_47X (CPU_FTRS_440x6)
c0d64cf9 363#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
7d470345 364 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 365 CPU_FTR_NOEXECUTE)
c0d64cf9 366#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 367 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
7d470345
CL		 368 CPU_FTR_NOEXECUTE)
369#define CPU_FTRS_E500MC ( \
dd0efb3f 370 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 371 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 372/*
373 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
374 * same workaround as CPU_FTR_CELL_TB_BUG.
375 */
7d470345 376#define CPU_FTRS_E5500 ( \
dd0efb3f 377 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 378 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 379 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
7d470345 380#define CPU_FTRS_E6500 ( \
dd0efb3f 381 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
10241842 382 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 383 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 384 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
0b8e2e13
ME		 385
386/* 64-bit CPUs */
c0d64cf9 387#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
3735eb85 388 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
2a929436 389 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 390 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 391 CPU_FTR_HVMODE | CPU_FTR_DABRX)
c0d64cf9 392#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
7c03d653 393 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 395 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 396 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
c0d64cf9 397#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
7c03d653 398 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 399 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 400 CPU_FTR_COHERENT_ICACHE | \
4c198557 401 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 402 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 403 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
404 CPU_FTR_DABRX)
c0d64cf9 405#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
969391c5 406 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 407 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 408 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 409 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 410 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 411 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 412 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
a24204c3 413 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
c0d64cf9 414#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
71e18497
MN		 415 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
416 CPU_FTR_MMCRA | CPU_FTR_SMT | \
417 CPU_FTR_COHERENT_ICACHE | \
418 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 419 CPU_FTR_DSCR | CPU_FTR_SAO | \
71e18497 420 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 421 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e 422 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
a24204c3 423 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
68f2f0d4 424#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
c0d64cf9 425#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
c3ab300e
MN		 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
427 CPU_FTR_MMCRA | CPU_FTR_SMT | \
428 CPU_FTR_COHERENT_ICACHE | \
429 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 430 CPU_FTR_DSCR | CPU_FTR_SAO | \
c3ab300e 431 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
2384d2d7 432 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
96541531 433 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
a24204c3
AK		 434 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
435 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
736bcdd3
JN		 436#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
437#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
438 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
439 CPU_FTR_POWER9_DD2_1)
3a52f601
NP		 440#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
441 CPU_FTR_P9_TM_HV_ASSIST | \
b5af4f27 442 CPU_FTR_P9_TM_XER_SO_BUG)
26b78c81
RA		 443#define CPU_FTRS_POWER9_DD2_3 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
444 CPU_FTR_P9_TM_HV_ASSIST | \
445 CPU_FTR_P9_TM_XER_SO_BUG | \
446 CPU_FTR_DAWR)
a3ea40d5
AP		 447#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
449 CPU_FTR_MMCRA | CPU_FTR_SMT | \
450 CPU_FTR_COHERENT_ICACHE | \
451 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
12564485 452 CPU_FTR_DSCR | CPU_FTR_SAO | \
a3ea40d5
AP		 453 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
454 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
455 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
ec613a57 456 CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
dc1cedca 457 CPU_FTR_DAWR | CPU_FTR_DAWR1)
c0d64cf9 458#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
7c03d653 459 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 460 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 461 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 462 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
c0d64cf9 463#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
44ae3ab3 464 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 465 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
c0d64cf9 466#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
10b35d99 467
8d1eeabf 468#ifdef CONFIG_PPC64
11ed0db9 469#ifdef CONFIG_PPC_BOOK3E
90029640 470#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 471#else
db5ae1c1
NP		 472#ifdef CONFIG_CPU_LITTLE_ENDIAN
473#define CPU_FTRS_POSSIBLE \
474 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
e11b64b1 475 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
26b78c81
RA		 476 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \
477 CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10)
db5ae1c1 478#else
7c92943c 479#define CPU_FTRS_POSSIBLE \
471d7ff8 480 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
468a3302 481 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
e11b64b1
JS		 482 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
483 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
26b78c81
RA		 484 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | \
485 CPU_FTRS_POWER9_DD2_3 | CPU_FTRS_POWER10)
db5ae1c1 486#endif /* CONFIG_CPU_LITTLE_ENDIAN */
11ed0db9 487#endif
2406f606 488#else
7c92943c
SR		 489enum {
490 CPU_FTRS_POSSIBLE =
44e9754d 491#ifdef CONFIG_PPC_BOOK3S_604
ad510e37 492 CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
10b35d99
KG		 493 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
494 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
495 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
496 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
497 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
ad510e37 498 CPU_FTRS_7447 | CPU_FTRS_7447A |
aa42c69c 499 CPU_FTRS_CLASSIC32 |
44e9754d
CL		 500#endif
501#ifdef CONFIG_PPC_BOOK3S_603
ad510e37
CL		 502 CPU_FTRS_603 | CPU_FTRS_82XX |
503 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
10b35d99 504#endif
968159c0 505#ifdef CONFIG_PPC_8xx
10b35d99
KG		 506 CPU_FTRS_8XX |
507#endif
508#ifdef CONFIG_40x
509 CPU_FTRS_40X |
510#endif
e7f75ad0 511#ifdef CONFIG_PPC_47x
c48d0dba 512 CPU_FTRS_47X | CPU_FTR_476_DD2 |
8b8319b1
CL		 513#elif defined(CONFIG_44x)
514 CPU_FTRS_44X | CPU_FTRS_440x6 |
e7f75ad0 515#endif
10b35d99 516#ifdef CONFIG_E500
06aae867
SW		 517 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
518#endif
519#ifdef CONFIG_PPC_E500MC
520 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 521#endif
10b35d99 522 0,
7c92943c
SR		 523};
524#endif /* __powerpc64__ */
10b35d99 525
8d1eeabf 526#ifdef CONFIG_PPC64
11ed0db9 527#ifdef CONFIG_PPC_BOOK3E
90029640 528#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 529#else
81b654c2
ME		 530
531#ifdef CONFIG_PPC_DT_CPU_FTRS
532#define CPU_FTRS_DT_CPU_BASE \
533 (CPU_FTR_LWSYNC | \
534 CPU_FTR_FPU_UNAVAILABLE | \
81b654c2
ME		 535 CPU_FTR_NOEXECUTE | \
536 CPU_FTR_COHERENT_ICACHE | \
537 CPU_FTR_STCX_CHECKS_ADDRESS | \
538 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
539 CPU_FTR_DAWR | \
540 CPU_FTR_ARCH_206 | \
541 CPU_FTR_ARCH_207S)
542#else
543#define CPU_FTRS_DT_CPU_BASE (~0ul)
544#endif
545
db5ae1c1
NP		 546#ifdef CONFIG_CPU_LITTLE_ENDIAN
547#define CPU_FTRS_ALWAYS \
548 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
ce57c661 549 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
b4d9cc75
ME		 550 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \
551 CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE)
db5ae1c1 552#else
7c92943c 553#define CPU_FTRS_ALWAYS \
471d7ff8 554 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
468a3302 555 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 556 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
ce57c661 557 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
b4d9cc75
ME		 558 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_POWER9_DD2_2 & \
559 CPU_FTRS_POWER10 & CPU_FTRS_DT_CPU_BASE)
db5ae1c1 560#endif /* CONFIG_CPU_LITTLE_ENDIAN */
11ed0db9 561#endif
2406f606 562#else
7c92943c
SR		 563enum {
564 CPU_FTRS_ALWAYS =
44e9754d 565#ifdef CONFIG_PPC_BOOK3S_604
ad510e37 566 CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
10b35d99
KG		 567 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
568 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
569 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
570 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
571 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
ad510e37 572 CPU_FTRS_7447 & CPU_FTRS_7447A &
aa42c69c 573 CPU_FTRS_CLASSIC32 &
44e9754d
CL		 574#endif
575#ifdef CONFIG_PPC_BOOK3S_603
ad510e37
CL		 576 CPU_FTRS_603 & CPU_FTRS_82XX &
577 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
10b35d99 578#endif
968159c0 579#ifdef CONFIG_PPC_8xx
10b35d99
KG		 580 CPU_FTRS_8XX &
581#endif
582#ifdef CONFIG_40x
583 CPU_FTRS_40X &
584#endif
8b8319b1
CL		 585#ifdef CONFIG_PPC_47x
586 CPU_FTRS_47X &
587#elif defined(CONFIG_44x)
6d2170be 588 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99 589#endif
10b35d99 590#ifdef CONFIG_E500
06aae867
SW		 591 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
592#endif
593#ifdef CONFIG_PPC_E500MC
594 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 595#endif
73196cd3 596 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 597 CPU_FTRS_POSSIBLE,
598};
7c92943c 599#endif /* __powerpc64__ */
10b35d99 600
a6ba44e8
RB		 601/*
602 * Maximum number of hw breakpoint supported on powerpc. Number of
deb2bd9b
RB		 603 * breakpoints supported by actual hw might be less than this, which
604 * is decided at run time in nr_wp_slots().
a6ba44e8 605 */
deb2bd9b 606#define HBP_NUM_MAX 2
5aae8a53 607
10b35d99
KG		 608#endif /* !__ASSEMBLY__ */
609
10b35d99 610#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)