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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
33d71d26 KG |
2 | /* |
3 | * MPC8xx Communication Processor Module. | |
4 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
5 | * | |
6 | * This file contains structures and information for the communication | |
7 | * processor channels. Some CPM control and status is available | |
25985edc | 8 | * through the MPC8xx internal memory map. See immap.h for details. |
33d71d26 KG |
9 | * This file only contains what I need for the moment, not the total |
10 | * CPM capabilities. I (or someone else) will add definitions as they | |
11 | * are needed. -- Dan | |
12 | * | |
13 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 | |
14 | * bytes of the DP RAM and relocates the I2C parameter area to the | |
15 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors | |
16 | * or other use. | |
17 | */ | |
b5677d84 JF |
18 | #ifndef __CPM1__ |
19 | #define __CPM1__ | |
33d71d26 | 20 | |
af71bcfe | 21 | #include <linux/init.h> |
33d71d26 KG |
22 | #include <asm/8xx_immap.h> |
23 | #include <asm/ptrace.h> | |
15f8c604 | 24 | #include <asm/cpm.h> |
33d71d26 KG |
25 | |
26 | /* CPM Command register. | |
27 | */ | |
28 | #define CPM_CR_RST ((ushort)0x8000) | |
29 | #define CPM_CR_OPCODE ((ushort)0x0f00) | |
30 | #define CPM_CR_CHAN ((ushort)0x00f0) | |
31 | #define CPM_CR_FLG ((ushort)0x0001) | |
32 | ||
33d71d26 KG |
33 | /* Channel numbers. |
34 | */ | |
35 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) | |
36 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ | |
37 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | |
38 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ | |
39 | #define CPM_CR_CH_TIMER CPM_CR_CH_SPI | |
40 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | |
41 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ | |
42 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | |
43 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ | |
44 | ||
45 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | |
46 | ||
33d71d26 KG |
47 | /* Export the base address of the communication processor registers |
48 | * and dual port ram. | |
49 | */ | |
fb533d0c | 50 | extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */ |
15f8c604 | 51 | |
33d71d26 KG |
52 | extern void cpm_setbrg(uint brg, uint rate); |
53 | ||
af71bcfe | 54 | extern void __init cpm_load_patch(cpm8xx_t *cp); |
33d71d26 | 55 | |
49b51545 JF |
56 | extern void cpm_reset(void); |
57 | ||
33d71d26 KG |
58 | /* Parameter RAM offsets. |
59 | */ | |
60 | #define PROFF_SCC1 ((uint)0x0000) | |
61 | #define PROFF_IIC ((uint)0x0080) | |
62 | #define PROFF_SCC2 ((uint)0x0100) | |
63 | #define PROFF_SPI ((uint)0x0180) | |
64 | #define PROFF_SCC3 ((uint)0x0200) | |
65 | #define PROFF_SMC1 ((uint)0x0280) | |
1e78f723 | 66 | #define PROFF_DSP1 ((uint)0x02c0) |
33d71d26 KG |
67 | #define PROFF_SCC4 ((uint)0x0300) |
68 | #define PROFF_SMC2 ((uint)0x0380) | |
69 | ||
70 | /* Define enough so I can at least use the serial port as a UART. | |
71 | * The MBX uses SMC1 as the host serial port. | |
72 | */ | |
73 | typedef struct smc_uart { | |
74 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | |
75 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | |
76 | u_char smc_rfcr; /* Rx function code */ | |
77 | u_char smc_tfcr; /* Tx function code */ | |
78 | ushort smc_mrblr; /* Max receive buffer length */ | |
79 | uint smc_rstate; /* Internal */ | |
80 | uint smc_idp; /* Internal */ | |
81 | ushort smc_rbptr; /* Internal */ | |
82 | ushort smc_ibc; /* Internal */ | |
83 | uint smc_rxtmp; /* Internal */ | |
84 | uint smc_tstate; /* Internal */ | |
85 | uint smc_tdp; /* Internal */ | |
86 | ushort smc_tbptr; /* Internal */ | |
87 | ushort smc_tbc; /* Internal */ | |
88 | uint smc_txtmp; /* Internal */ | |
89 | ushort smc_maxidl; /* Maximum idle characters */ | |
90 | ushort smc_tmpidl; /* Temporary idle counter */ | |
91 | ushort smc_brklen; /* Last received break length */ | |
92 | ushort smc_brkec; /* rcv'd break condition counter */ | |
93 | ushort smc_brkcr; /* xmt break count register */ | |
94 | ushort smc_rmask; /* Temporary bit mask */ | |
95 | char res1[8]; /* Reserved */ | |
96 | ushort smc_rpbase; /* Relocation pointer */ | |
97 | } smc_uart_t; | |
98 | ||
99 | /* Function code bits. | |
100 | */ | |
101 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | |
102 | ||
103 | /* SMC uart mode register. | |
104 | */ | |
105 | #define SMCMR_REN ((ushort)0x0001) | |
106 | #define SMCMR_TEN ((ushort)0x0002) | |
107 | #define SMCMR_DM ((ushort)0x000c) | |
108 | #define SMCMR_SM_GCI ((ushort)0x0000) | |
109 | #define SMCMR_SM_UART ((ushort)0x0020) | |
110 | #define SMCMR_SM_TRANS ((ushort)0x0030) | |
111 | #define SMCMR_SM_MASK ((ushort)0x0030) | |
112 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | |
113 | #define SMCMR_REVD SMCMR_PM_EVEN | |
114 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | |
115 | #define SMCMR_BS SMCMR_PEN | |
116 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | |
117 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | |
118 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | |
119 | ||
120 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | |
121 | * it can only receive or transmit. The parameter ram values for | |
122 | * each direction are either unique or properly overlap, so we can | |
123 | * include them in one structure. | |
124 | */ | |
125 | typedef struct smc_centronics { | |
126 | ushort scent_rbase; | |
127 | ushort scent_tbase; | |
128 | u_char scent_cfcr; | |
129 | u_char scent_smask; | |
130 | ushort scent_mrblr; | |
131 | uint scent_rstate; | |
132 | uint scent_r_ptr; | |
133 | ushort scent_rbptr; | |
134 | ushort scent_r_cnt; | |
135 | uint scent_rtemp; | |
136 | uint scent_tstate; | |
137 | uint scent_t_ptr; | |
138 | ushort scent_tbptr; | |
139 | ushort scent_t_cnt; | |
140 | uint scent_ttemp; | |
141 | ushort scent_max_sl; | |
142 | ushort scent_sl_cnt; | |
143 | ushort scent_character1; | |
144 | ushort scent_character2; | |
145 | ushort scent_character3; | |
146 | ushort scent_character4; | |
147 | ushort scent_character5; | |
148 | ushort scent_character6; | |
149 | ushort scent_character7; | |
150 | ushort scent_character8; | |
151 | ushort scent_rccm; | |
152 | ushort scent_rccr; | |
153 | } smc_cent_t; | |
154 | ||
155 | /* Centronics Status Mask Register. | |
156 | */ | |
157 | #define SMC_CENT_F ((u_char)0x08) | |
158 | #define SMC_CENT_PE ((u_char)0x04) | |
159 | #define SMC_CENT_S ((u_char)0x02) | |
160 | ||
161 | /* SMC Event and Mask register. | |
162 | */ | |
163 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | |
164 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | |
165 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | |
166 | #define SMCM_BSY ((unsigned char)0x04) | |
167 | #define SMCM_TX ((unsigned char)0x02) | |
168 | #define SMCM_RX ((unsigned char)0x01) | |
169 | ||
170 | /* Baud rate generators. | |
171 | */ | |
172 | #define CPM_BRG_RST ((uint)0x00020000) | |
173 | #define CPM_BRG_EN ((uint)0x00010000) | |
174 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | |
175 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | |
176 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | |
177 | #define CPM_BRG_ATB ((uint)0x00002000) | |
178 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | |
179 | #define CPM_BRG_DIV16 ((uint)0x00000001) | |
180 | ||
181 | /* SI Clock Route Register | |
182 | */ | |
183 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) | |
184 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) | |
185 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) | |
186 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) | |
187 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) | |
188 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) | |
189 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) | |
190 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) | |
191 | ||
192 | /* SCCs. | |
193 | */ | |
194 | #define SCC_GSMRH_IRP ((uint)0x00040000) | |
195 | #define SCC_GSMRH_GDE ((uint)0x00010000) | |
196 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | |
197 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | |
198 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | |
199 | #define SCC_GSMRH_REVD ((uint)0x00002000) | |
200 | #define SCC_GSMRH_TRX ((uint)0x00001000) | |
201 | #define SCC_GSMRH_TTX ((uint)0x00000800) | |
202 | #define SCC_GSMRH_CDP ((uint)0x00000400) | |
203 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | |
204 | #define SCC_GSMRH_CDS ((uint)0x00000100) | |
205 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | |
206 | #define SCC_GSMRH_TFL ((uint)0x00000040) | |
207 | #define SCC_GSMRH_RFW ((uint)0x00000020) | |
208 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | |
209 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | |
210 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | |
211 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | |
212 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | |
213 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | |
214 | ||
215 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | |
216 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | |
217 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | |
218 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | |
219 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | |
220 | #define SCC_GSMRL_TCI ((uint)0x10000000) | |
221 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | |
222 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | |
223 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | |
224 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | |
225 | #define SCC_GSMRL_RINV ((uint)0x02000000) | |
226 | #define SCC_GSMRL_TINV ((uint)0x01000000) | |
227 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | |
228 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | |
229 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | |
230 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | |
231 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | |
232 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | |
233 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | |
234 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | |
235 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | |
236 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | |
237 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | |
238 | #define SCC_GSMRL_TEND ((uint)0x00040000) | |
239 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | |
240 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | |
241 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | |
242 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | |
243 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | |
244 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | |
245 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | |
246 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | |
247 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | |
248 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | |
249 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | |
250 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | |
251 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | |
252 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | |
253 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | |
254 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | |
255 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | |
256 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | |
257 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | |
258 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | |
259 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | |
260 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | |
261 | #define SCC_GSMRL_ENR ((uint)0x00000020) | |
262 | #define SCC_GSMRL_ENT ((uint)0x00000010) | |
263 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | |
264 | #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) | |
265 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | |
266 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | |
267 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | |
268 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | |
269 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | |
270 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | |
271 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | |
272 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | |
273 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | |
274 | ||
275 | #define SCC_TODR_TOD ((ushort)0x8000) | |
276 | ||
277 | /* SCC Event and Mask register. | |
278 | */ | |
279 | #define SCCM_TXE ((unsigned char)0x10) | |
280 | #define SCCM_BSY ((unsigned char)0x04) | |
281 | #define SCCM_TX ((unsigned char)0x02) | |
282 | #define SCCM_RX ((unsigned char)0x01) | |
283 | ||
284 | typedef struct scc_param { | |
285 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | |
286 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | |
287 | u_char scc_rfcr; /* Rx function code */ | |
288 | u_char scc_tfcr; /* Tx function code */ | |
289 | ushort scc_mrblr; /* Max receive buffer length */ | |
290 | uint scc_rstate; /* Internal */ | |
291 | uint scc_idp; /* Internal */ | |
292 | ushort scc_rbptr; /* Internal */ | |
293 | ushort scc_ibc; /* Internal */ | |
294 | uint scc_rxtmp; /* Internal */ | |
295 | uint scc_tstate; /* Internal */ | |
296 | uint scc_tdp; /* Internal */ | |
297 | ushort scc_tbptr; /* Internal */ | |
298 | ushort scc_tbc; /* Internal */ | |
299 | uint scc_txtmp; /* Internal */ | |
300 | uint scc_rcrc; /* Internal */ | |
301 | uint scc_tcrc; /* Internal */ | |
302 | } sccp_t; | |
303 | ||
304 | /* Function code bits. | |
305 | */ | |
306 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | |
307 | ||
308 | /* CPM Ethernet through SCCx. | |
309 | */ | |
310 | typedef struct scc_enet { | |
311 | sccp_t sen_genscc; | |
312 | uint sen_cpres; /* Preset CRC */ | |
313 | uint sen_cmask; /* Constant mask for CRC */ | |
314 | uint sen_crcec; /* CRC Error counter */ | |
315 | uint sen_alec; /* alignment error counter */ | |
316 | uint sen_disfc; /* discard frame counter */ | |
317 | ushort sen_pads; /* Tx short frame pad character */ | |
318 | ushort sen_retlim; /* Retry limit threshold */ | |
319 | ushort sen_retcnt; /* Retry limit counter */ | |
320 | ushort sen_maxflr; /* maximum frame length register */ | |
321 | ushort sen_minflr; /* minimum frame length register */ | |
322 | ushort sen_maxd1; /* maximum DMA1 length */ | |
323 | ushort sen_maxd2; /* maximum DMA2 length */ | |
324 | ushort sen_maxd; /* Rx max DMA */ | |
325 | ushort sen_dmacnt; /* Rx DMA counter */ | |
326 | ushort sen_maxb; /* Max BD byte count */ | |
327 | ushort sen_gaddr1; /* Group address filter */ | |
328 | ushort sen_gaddr2; | |
329 | ushort sen_gaddr3; | |
330 | ushort sen_gaddr4; | |
331 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | |
332 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | |
333 | uint sen_tbuf0rba; /* Internal */ | |
334 | uint sen_tbuf0crc; /* Internal */ | |
335 | ushort sen_tbuf0bcnt; /* Internal */ | |
336 | ushort sen_paddrh; /* physical address (MSB) */ | |
337 | ushort sen_paddrm; | |
338 | ushort sen_paddrl; /* physical address (LSB) */ | |
339 | ushort sen_pper; /* persistence */ | |
340 | ushort sen_rfbdptr; /* Rx first BD pointer */ | |
341 | ushort sen_tfbdptr; /* Tx first BD pointer */ | |
342 | ushort sen_tlbdptr; /* Tx last BD pointer */ | |
343 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | |
344 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | |
345 | uint sen_tbuf1rba; /* Internal */ | |
346 | uint sen_tbuf1crc; /* Internal */ | |
347 | ushort sen_tbuf1bcnt; /* Internal */ | |
348 | ushort sen_txlen; /* Tx Frame length counter */ | |
349 | ushort sen_iaddr1; /* Individual address filter */ | |
350 | ushort sen_iaddr2; | |
351 | ushort sen_iaddr3; | |
352 | ushort sen_iaddr4; | |
353 | ushort sen_boffcnt; /* Backoff counter */ | |
354 | ||
355 | /* NOTE: Some versions of the manual have the following items | |
356 | * incorrectly documented. Below is the proper order. | |
357 | */ | |
358 | ushort sen_taddrh; /* temp address (MSB) */ | |
359 | ushort sen_taddrm; | |
360 | ushort sen_taddrl; /* temp address (LSB) */ | |
361 | } scc_enet_t; | |
362 | ||
363 | /* SCC Event register as used by Ethernet. | |
364 | */ | |
365 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | |
366 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | |
367 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | |
368 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | |
369 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | |
370 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | |
371 | ||
372 | /* SCC Mode Register (PMSR) as used by Ethernet. | |
373 | */ | |
374 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | |
375 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | |
376 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | |
377 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | |
378 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | |
379 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | |
380 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | |
381 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | |
382 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | |
383 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | |
384 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | |
385 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | |
386 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | |
387 | ||
33d71d26 KG |
388 | /* SCC as UART |
389 | */ | |
390 | typedef struct scc_uart { | |
391 | sccp_t scc_genscc; | |
392 | char res1[8]; /* Reserved */ | |
393 | ushort scc_maxidl; /* Maximum idle chars */ | |
394 | ushort scc_idlc; /* temp idle counter */ | |
395 | ushort scc_brkcr; /* Break count register */ | |
396 | ushort scc_parec; /* receive parity error counter */ | |
397 | ushort scc_frmec; /* receive framing error counter */ | |
398 | ushort scc_nosec; /* receive noise counter */ | |
399 | ushort scc_brkec; /* receive break condition counter */ | |
400 | ushort scc_brkln; /* last received break length */ | |
401 | ushort scc_uaddr1; /* UART address character 1 */ | |
402 | ushort scc_uaddr2; /* UART address character 2 */ | |
403 | ushort scc_rtemp; /* Temp storage */ | |
404 | ushort scc_toseq; /* Transmit out of sequence char */ | |
405 | ushort scc_char1; /* control character 1 */ | |
406 | ushort scc_char2; /* control character 2 */ | |
407 | ushort scc_char3; /* control character 3 */ | |
408 | ushort scc_char4; /* control character 4 */ | |
409 | ushort scc_char5; /* control character 5 */ | |
410 | ushort scc_char6; /* control character 6 */ | |
411 | ushort scc_char7; /* control character 7 */ | |
412 | ushort scc_char8; /* control character 8 */ | |
413 | ushort scc_rccm; /* receive control character mask */ | |
414 | ushort scc_rccr; /* receive control character register */ | |
415 | ushort scc_rlbc; /* receive last break character */ | |
416 | } scc_uart_t; | |
417 | ||
418 | /* SCC Event and Mask registers when it is used as a UART. | |
419 | */ | |
420 | #define UART_SCCM_GLR ((ushort)0x1000) | |
421 | #define UART_SCCM_GLT ((ushort)0x0800) | |
422 | #define UART_SCCM_AB ((ushort)0x0200) | |
423 | #define UART_SCCM_IDL ((ushort)0x0100) | |
424 | #define UART_SCCM_GRA ((ushort)0x0080) | |
425 | #define UART_SCCM_BRKE ((ushort)0x0040) | |
426 | #define UART_SCCM_BRKS ((ushort)0x0020) | |
427 | #define UART_SCCM_CCR ((ushort)0x0008) | |
428 | #define UART_SCCM_BSY ((ushort)0x0004) | |
429 | #define UART_SCCM_TX ((ushort)0x0002) | |
430 | #define UART_SCCM_RX ((ushort)0x0001) | |
431 | ||
432 | /* The SCC PMSR when used as a UART. | |
433 | */ | |
434 | #define SCU_PSMR_FLC ((ushort)0x8000) | |
435 | #define SCU_PSMR_SL ((ushort)0x4000) | |
436 | #define SCU_PSMR_CL ((ushort)0x3000) | |
437 | #define SCU_PSMR_UM ((ushort)0x0c00) | |
438 | #define SCU_PSMR_FRZ ((ushort)0x0200) | |
439 | #define SCU_PSMR_RZS ((ushort)0x0100) | |
440 | #define SCU_PSMR_SYN ((ushort)0x0080) | |
441 | #define SCU_PSMR_DRT ((ushort)0x0040) | |
442 | #define SCU_PSMR_PEN ((ushort)0x0010) | |
443 | #define SCU_PSMR_RPM ((ushort)0x000c) | |
444 | #define SCU_PSMR_REVP ((ushort)0x0008) | |
445 | #define SCU_PSMR_TPM ((ushort)0x0003) | |
446 | #define SCU_PSMR_TEVP ((ushort)0x0002) | |
447 | ||
448 | /* CPM Transparent mode SCC. | |
449 | */ | |
450 | typedef struct scc_trans { | |
451 | sccp_t st_genscc; | |
452 | uint st_cpres; /* Preset CRC */ | |
453 | uint st_cmask; /* Constant mask for CRC */ | |
454 | } scc_trans_t; | |
455 | ||
33d71d26 KG |
456 | /* IIC parameter RAM. |
457 | */ | |
458 | typedef struct iic { | |
459 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | |
460 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | |
461 | u_char iic_rfcr; /* Rx function code */ | |
462 | u_char iic_tfcr; /* Tx function code */ | |
463 | ushort iic_mrblr; /* Max receive buffer length */ | |
464 | uint iic_rstate; /* Internal */ | |
465 | uint iic_rdp; /* Internal */ | |
466 | ushort iic_rbptr; /* Internal */ | |
467 | ushort iic_rbc; /* Internal */ | |
468 | uint iic_rxtmp; /* Internal */ | |
469 | uint iic_tstate; /* Internal */ | |
470 | uint iic_tdp; /* Internal */ | |
471 | ushort iic_tbptr; /* Internal */ | |
472 | ushort iic_tbc; /* Internal */ | |
473 | uint iic_txtmp; /* Internal */ | |
474 | char res1[4]; /* Reserved */ | |
475 | ushort iic_rpbase; /* Relocation pointer */ | |
476 | char res2[2]; /* Reserved */ | |
477 | } iic_t; | |
478 | ||
33d71d26 KG |
479 | /* |
480 | * RISC Controller Configuration Register definitons | |
481 | */ | |
482 | #define RCCR_TIME 0x8000 /* RISC Timer Enable */ | |
483 | #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ | |
484 | #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ | |
485 | ||
486 | /* RISC Timer Parameter RAM offset */ | |
487 | #define PROFF_RTMR ((uint)0x01B0) | |
488 | ||
489 | typedef struct risc_timer_pram { | |
490 | unsigned short tm_base; /* RISC Timer Table Base Address */ | |
491 | unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ | |
492 | unsigned short r_tmr; /* RISC Timer Mode Register */ | |
493 | unsigned short r_tmv; /* RISC Timer Valid Register */ | |
494 | unsigned long tm_cmd; /* RISC Timer Command Register */ | |
495 | unsigned long tm_cnt; /* RISC Timer Internal Count */ | |
496 | } rt_pram_t; | |
497 | ||
498 | /* Bits in RISC Timer Command Register */ | |
499 | #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ | |
500 | #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ | |
501 | #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ | |
502 | #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ | |
503 | #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ | |
504 | ||
505 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | |
506 | * channels or devices. All of these are presented to the PPC core | |
507 | * as a single interrupt. The CPM interrupt handler dispatches its | |
508 | * own handlers, in a similar fashion to the PPC core handler. We | |
509 | * use the table as defined in the manuals (i.e. no special high | |
510 | * priority and SCC1 == SCCa, etc...). | |
511 | */ | |
512 | #define CPMVEC_NR 32 | |
513 | #define CPMVEC_PIO_PC15 ((ushort)0x1f) | |
514 | #define CPMVEC_SCC1 ((ushort)0x1e) | |
515 | #define CPMVEC_SCC2 ((ushort)0x1d) | |
516 | #define CPMVEC_SCC3 ((ushort)0x1c) | |
517 | #define CPMVEC_SCC4 ((ushort)0x1b) | |
518 | #define CPMVEC_PIO_PC14 ((ushort)0x1a) | |
519 | #define CPMVEC_TIMER1 ((ushort)0x19) | |
520 | #define CPMVEC_PIO_PC13 ((ushort)0x18) | |
521 | #define CPMVEC_PIO_PC12 ((ushort)0x17) | |
522 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) | |
523 | #define CPMVEC_IDMA1 ((ushort)0x15) | |
524 | #define CPMVEC_IDMA2 ((ushort)0x14) | |
525 | #define CPMVEC_TIMER2 ((ushort)0x12) | |
526 | #define CPMVEC_RISCTIMER ((ushort)0x11) | |
527 | #define CPMVEC_I2C ((ushort)0x10) | |
528 | #define CPMVEC_PIO_PC11 ((ushort)0x0f) | |
529 | #define CPMVEC_PIO_PC10 ((ushort)0x0e) | |
530 | #define CPMVEC_TIMER3 ((ushort)0x0c) | |
531 | #define CPMVEC_PIO_PC9 ((ushort)0x0b) | |
532 | #define CPMVEC_PIO_PC8 ((ushort)0x0a) | |
533 | #define CPMVEC_PIO_PC7 ((ushort)0x09) | |
534 | #define CPMVEC_TIMER4 ((ushort)0x07) | |
535 | #define CPMVEC_PIO_PC6 ((ushort)0x06) | |
536 | #define CPMVEC_SPI ((ushort)0x05) | |
537 | #define CPMVEC_SMC1 ((ushort)0x04) | |
538 | #define CPMVEC_SMC2 ((ushort)0x03) | |
539 | #define CPMVEC_PIO_PC5 ((ushort)0x02) | |
540 | #define CPMVEC_PIO_PC4 ((ushort)0x01) | |
541 | #define CPMVEC_ERROR ((ushort)0x00) | |
542 | ||
543 | /* CPM interrupt configuration vector. | |
544 | */ | |
545 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | |
546 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | |
547 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | |
548 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | |
567e9fdd | 549 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ |
33d71d26 KG |
550 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ |
551 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | |
552 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | |
553 | ||
663edbd2 SW |
554 | #define CPM_PIN_INPUT 0 |
555 | #define CPM_PIN_OUTPUT 1 | |
556 | #define CPM_PIN_PRIMARY 0 | |
557 | #define CPM_PIN_SECONDARY 2 | |
558 | #define CPM_PIN_GPIO 4 | |
559 | #define CPM_PIN_OPENDRAIN 8 | |
726bd223 CL |
560 | #define CPM_PIN_FALLEDGE 16 |
561 | #define CPM_PIN_ANYEDGE 0 | |
663edbd2 SW |
562 | |
563 | enum cpm_port { | |
564 | CPM_PORTA, | |
565 | CPM_PORTB, | |
566 | CPM_PORTC, | |
567 | CPM_PORTD, | |
568 | CPM_PORTE, | |
569 | }; | |
570 | ||
571 | void cpm1_set_pin(enum cpm_port port, int pin, int flags); | |
572 | ||
573 | enum cpm_clk_dir { | |
574 | CPM_CLK_RX, | |
575 | CPM_CLK_TX, | |
576 | CPM_CLK_RTX | |
577 | }; | |
578 | ||
579 | enum cpm_clk_target { | |
580 | CPM_CLK_SCC1, | |
581 | CPM_CLK_SCC2, | |
582 | CPM_CLK_SCC3, | |
583 | CPM_CLK_SCC4, | |
584 | CPM_CLK_SMC1, | |
585 | CPM_CLK_SMC2, | |
586 | }; | |
587 | ||
588 | enum cpm_clk { | |
589 | CPM_BRG1, /* Baud Rate Generator 1 */ | |
590 | CPM_BRG2, /* Baud Rate Generator 2 */ | |
591 | CPM_BRG3, /* Baud Rate Generator 3 */ | |
592 | CPM_BRG4, /* Baud Rate Generator 4 */ | |
593 | CPM_CLK1, /* Clock 1 */ | |
594 | CPM_CLK2, /* Clock 2 */ | |
595 | CPM_CLK3, /* Clock 3 */ | |
596 | CPM_CLK4, /* Clock 4 */ | |
597 | CPM_CLK5, /* Clock 5 */ | |
598 | CPM_CLK6, /* Clock 6 */ | |
599 | CPM_CLK7, /* Clock 7 */ | |
600 | CPM_CLK8, /* Clock 8 */ | |
601 | }; | |
602 | ||
603 | int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); | |
c095ff93 CL |
604 | int cpm1_gpiochip_add16(struct device *dev); |
605 | int cpm1_gpiochip_add32(struct device *dev); | |
663edbd2 | 606 | |
b5677d84 | 607 | #endif /* __CPM1__ */ |