[linux-2.6-block.git] / arch / powerpc / include / asm / cache.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_CACHE_H
#define _ASM_POWERPC_CACHE_H

#ifdef __KERNEL__


/* bytes per L1 cache line */
#if defined(CONFIG_PPC_8xx) || defined(CONFIG_403GCX)
#define L1_CACHE_SHIFT		4
#define MAX_COPY_PREFETCH	1
#define IFETCH_ALIGN_SHIFT	2
#elif defined(CONFIG_PPC_E500MC)
#define L1_CACHE_SHIFT		6
#define MAX_COPY_PREFETCH	4
#define IFETCH_ALIGN_SHIFT	3
#elif defined(CONFIG_PPC32)
#define MAX_COPY_PREFETCH	4
#define IFETCH_ALIGN_SHIFT	3	/* 603 fetches 2 insn at a time */
#if defined(CONFIG_PPC_47x)
#define L1_CACHE_SHIFT		7
#else
#define L1_CACHE_SHIFT		5
#endif
#else /* CONFIG_PPC64 */
#define L1_CACHE_SHIFT		7
#define IFETCH_ALIGN_SHIFT	4 /* POWER8,9 */
#endif

#define	L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)

#define	SMP_CACHE_BYTES		L1_CACHE_BYTES

#define IFETCH_ALIGN_BYTES	(1 << IFETCH_ALIGN_SHIFT)

#if defined(__powerpc64__) && !defined(__ASSEMBLY__)

struct ppc_cache_info {
	u32 size;
	u32 line_size;
	u32 block_size;	/* L1 only */
	u32 log_block_size;
	u32 blocks_per_page;
	u32 sets;
	u32 assoc;
};

struct ppc64_caches {
	struct ppc_cache_info l1d;
	struct ppc_cache_info l1i;
	struct ppc_cache_info l2;
	struct ppc_cache_info l3;
};

extern struct ppc64_caches ppc64_caches;
#endif /* __powerpc64__ && ! __ASSEMBLY__ */

#if defined(__ASSEMBLY__)
/*
 * For a snooping icache, we still need a dummy icbi to purge all the
 * prefetched instructions from the ifetch buffers. We also need a sync
 * before the icbi to order the the actual stores to memory that might
 * have modified instructions with the icbi.
 */
#define PURGE_PREFETCHED_INS	\
	sync;			\
	icbi	0,r3;		\
	sync;			\
	isync

#else
#define __read_mostly __attribute__((__section__(".data..read_mostly")))

#ifdef CONFIG_PPC_BOOK3S_32
extern long _get_L2CR(void);
extern long _get_L3CR(void);
extern void _set_L2CR(unsigned long);
extern void _set_L3CR(unsigned long);
#else
#define _get_L2CR()	0L
#define _get_L3CR()	0L
#define _set_L2CR(val)	do { } while(0)
#define _set_L3CR(val)	do { } while(0)
#endif

static inline void dcbz(void *addr)
{
	__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
}

static inline void dcbi(void *addr)
{
	__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
}

static inline void dcbf(void *addr)
{
	__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
}

static inline void dcbst(void *addr)
{
	__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
}
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_CACHE_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
26ef5c09 DG	2	#ifndef _ASM_POWERPC_CACHE_H
	3	#define _ASM_POWERPC_CACHE_H
	4
	5	#ifdef __KERNEL__
	6
26ef5c09 DG	7
26ef5c09 DG	8	/* bytes per L1 cache line */
968159c0	9	#if defined(CONFIG_PPC_8xx) \|\| defined(CONFIG_403GCX)
26ef5c09 DG	10	#define L1_CACHE_SHIFT 4
26ef5c09 DG	11	#define MAX_COPY_PREFETCH 1
1128bb78	12	#define IFETCH_ALIGN_SHIFT 2
3dfa8773 KG	13	#elif defined(CONFIG_PPC_E500MC)
	14	#define L1_CACHE_SHIFT 6
	15	#define MAX_COPY_PREFETCH 4
1128bb78	16	#define IFETCH_ALIGN_SHIFT 3
26ef5c09	17	#elif defined(CONFIG_PPC32)
26ef5c09	18	#define MAX_COPY_PREFETCH 4
1128bb78	19	#define IFETCH_ALIGN_SHIFT 3 /* 603 fetches 2 insn at a time */
e7f75ad0 DK	20	#if defined(CONFIG_PPC_47x)
	21	#define L1_CACHE_SHIFT 7
	22	#else
	23	#define L1_CACHE_SHIFT 5
	24	#endif
26ef5c09 DG	25	#else /* CONFIG_PPC64 */
26ef5c09 DG	26	#define L1_CACHE_SHIFT 7
f4329f2e	27	#define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */
26ef5c09 DG	28	#endif
	29
	30	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
	31
	32	#define SMP_CACHE_BYTES L1_CACHE_BYTES
26ef5c09	33
f4329f2e NP	34	#define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT)
f4329f2e NP	35
26ef5c09	36	#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
e2827fe5 BH	37
	38	struct ppc_cache_info {
	39	u32 size;
	40	u32 line_size;
	41	u32 block_size; /* L1 only */
	42	u32 log_block_size;
	43	u32 blocks_per_page;
	44	u32 sets;
98a5f361	45	u32 assoc;
e2827fe5 BH	46	};
e2827fe5 BH	47
26ef5c09	48	struct ppc64_caches {
e2827fe5 BH	49	struct ppc_cache_info l1d;
e2827fe5 BH	50	struct ppc_cache_info l1i;
65e01f38 BH	51	struct ppc_cache_info l2;
65e01f38 BH	52	struct ppc_cache_info l3;
26ef5c09 DG	53	};
	54
	55	extern struct ppc64_caches ppc64_caches;
	56	#endif /* __powerpc64__ && ! __ASSEMBLY__ */
	57
0ce63670 KH	58	#if defined(__ASSEMBLY__)
	59	/*
	60	* For a snooping icache, we still need a dummy icbi to purge all the
	61	* prefetched instructions from the ifetch buffers. We also need a sync
	62	* before the icbi to order the the actual stores to memory that might
	63	* have modified instructions with the icbi.
	64	*/
	65	#define PURGE_PREFETCHED_INS \
	66	sync; \
	67	icbi 0,r3; \
	68	sync; \
	69	isync
ae3a197e	70
0ce63670	71	#else
54cb27a7	72	#define __read_mostly __attribute__((__section__(".data..read_mostly")))
ae3a197e	73
d7cceda9	74	#ifdef CONFIG_PPC_BOOK3S_32
ae3a197e DH	75	extern long _get_L2CR(void);
	76	extern long _get_L3CR(void);
	77	extern void _set_L2CR(unsigned long);
	78	extern void _set_L3CR(unsigned long);
	79	#else
	80	#define _get_L2CR() 0L
	81	#define _get_L3CR() 0L
	82	#define _set_L2CR(val) do { } while(0)
	83	#define _set_L3CR(val) do { } while(0)
bd67fcf9 TB	84	#endif
bd67fcf9 TB	85
d6bfa02f CL	86	static inline void dcbz(void *addr)
	87	{
	88	__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory");
	89	}
	90
	91	static inline void dcbi(void *addr)
	92	{
	93	__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory");
	94	}
	95
	96	static inline void dcbf(void *addr)
	97	{
	98	__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory");
	99	}
	100
	101	static inline void dcbst(void *addr)
	102	{
	103	__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory");
	104	}
ae3a197e	105	#endif /* !__ASSEMBLY__ */
26ef5c09 DG	106	#endif /* __KERNEL__ */
26ef5c09 DG	107	#endif /* _ASM_POWERPC_CACHE_H */