[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / tlbflush-hash.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H

/*
 * TLB flushing for 64-bit hash-MMU CPUs
 */

#include <linux/percpu.h>
#include <asm/page.h>

#define PPC64_TLB_BATCH_NR 192

struct ppc64_tlb_batch {
	int			active;
	unsigned long		index;
	struct mm_struct	*mm;
	real_pte_t		pte[PPC64_TLB_BATCH_NR];
	unsigned long		vpn[PPC64_TLB_BATCH_NR];
	unsigned int		psize;
	int			ssize;
};
DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);

extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);

#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE

static inline void arch_enter_lazy_mmu_mode(void)
{
	struct ppc64_tlb_batch *batch;

	if (radix_enabled())
		return;
	batch = this_cpu_ptr(&ppc64_tlb_batch);
	batch->active = 1;
}

static inline void arch_leave_lazy_mmu_mode(void)
{
	struct ppc64_tlb_batch *batch;

	if (radix_enabled())
		return;
	batch = this_cpu_ptr(&ppc64_tlb_batch);

	if (batch->index)
		__flush_tlb_pending(batch);
	batch->active = 0;
}

#define arch_flush_lazy_mmu_mode()      do {} while (0)

extern void hash__tlbiel_all(unsigned int action);

extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
			    int ssize, unsigned long flags);
extern void flush_hash_range(unsigned long number, int local);
extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
				pmd_t *pmdp, unsigned int psize, int ssize,
				unsigned long flags);
static inline void hash__local_flush_tlb_mm(struct mm_struct *mm)
{
}

static inline void hash__flush_tlb_mm(struct mm_struct *mm)
{
}

static inline void hash__local_flush_all_mm(struct mm_struct *mm)
{
	/*
	 * There's no Page Walk Cache for hash, so what is needed is
	 * the same as flush_tlb_mm(), which doesn't really make sense
	 * with hash. So the only thing we could do is flush the
	 * entire LPID! Punt for now, as it's not being used.
	 */
	WARN_ON_ONCE(1);
}

static inline void hash__flush_all_mm(struct mm_struct *mm)
{
	/*
	 * There's no Page Walk Cache for hash, so what is needed is
	 * the same as flush_tlb_mm(), which doesn't really make sense
	 * with hash. So the only thing we could do is flush the
	 * entire LPID! Punt for now, as it's not being used.
	 */
	WARN_ON_ONCE(1);
}

static inline void hash__local_flush_tlb_page(struct vm_area_struct *vma,
					  unsigned long vmaddr)
{
}

static inline void hash__flush_tlb_page(struct vm_area_struct *vma,
				    unsigned long vmaddr)
{
}

static inline void hash__flush_tlb_range(struct vm_area_struct *vma,
				     unsigned long start, unsigned long end)
{
}

static inline void hash__flush_tlb_kernel_range(unsigned long start,
					    unsigned long end)
{
}


struct mmu_gather;
extern void hash__tlb_flush(struct mmu_gather *tlb);

#ifdef CONFIG_PPC_64S_HASH_MMU
/* Private function for use by PCI IO mapping code */
extern void __flush_hash_table_range(unsigned long start, unsigned long end);
void flush_hash_table_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr);
#else
static inline void __flush_hash_table_range(unsigned long start, unsigned long end) { }
#endif
#endif /*  _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
ee3b93eb AK	2	#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
	3	#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
	4
ee3b93eb AK	5	/*
	6	* TLB flushing for 64-bit hash-MMU CPUs
	7	*/
	8
	9	#include <linux/percpu.h>
	10	#include <asm/page.h>
	11
	12	#define PPC64_TLB_BATCH_NR 192
	13
	14	struct ppc64_tlb_batch {
	15	int active;
	16	unsigned long index;
	17	struct mm_struct *mm;
	18	real_pte_t pte[PPC64_TLB_BATCH_NR];
	19	unsigned long vpn[PPC64_TLB_BATCH_NR];
	20	unsigned int psize;
	21	int ssize;
	22	};
	23	DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
	24
	25	extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
	26
	27	#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
	28
	29	static inline void arch_enter_lazy_mmu_mode(void)
	30	{
1a472c9d	31	struct ppc64_tlb_batch *batch;
ee3b93eb	32
1a472c9d AK	33	if (radix_enabled())
	34	return;
	35	batch = this_cpu_ptr(&ppc64_tlb_batch);
ee3b93eb AK	36	batch->active = 1;
	37	}
	38
	39	static inline void arch_leave_lazy_mmu_mode(void)
	40	{
1a472c9d AK	41	struct ppc64_tlb_batch *batch;
	42
	43	if (radix_enabled())
	44	return;
	45	batch = this_cpu_ptr(&ppc64_tlb_batch);
ee3b93eb AK	46
	47	if (batch->index)
	48	__flush_tlb_pending(batch);
	49	batch->active = 0;
	50	}
	51
	52	#define arch_flush_lazy_mmu_mode() do {} while (0)
	53
d4748276	54	extern void hash__tlbiel_all(unsigned int action);
ee3b93eb AK	55
	56	extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
	57	int ssize, unsigned long flags);
	58	extern void flush_hash_range(unsigned long number, int local);
	59	extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
	60	pmd_t *pmdp, unsigned int psize, int ssize,
	61	unsigned long flags);
676012a6	62	static inline void hash__local_flush_tlb_mm(struct mm_struct *mm)
ee3b93eb AK	63	{
	64	}
	65
676012a6	66	static inline void hash__flush_tlb_mm(struct mm_struct *mm)
ee3b93eb AK	67	{
	68	}
	69
6110236b FB	70	static inline void hash__local_flush_all_mm(struct mm_struct *mm)
	71	{
	72	/*
	73	* There's no Page Walk Cache for hash, so what is needed is
	74	* the same as flush_tlb_mm(), which doesn't really make sense
	75	* with hash. So the only thing we could do is flush the
	76	* entire LPID! Punt for now, as it's not being used.
	77	*/
	78	WARN_ON_ONCE(1);
	79	}
	80
	81	static inline void hash__flush_all_mm(struct mm_struct *mm)
	82	{
	83	/*
	84	* There's no Page Walk Cache for hash, so what is needed is
	85	* the same as flush_tlb_mm(), which doesn't really make sense
	86	* with hash. So the only thing we could do is flush the
	87	* entire LPID! Punt for now, as it's not being used.
	88	*/
	89	WARN_ON_ONCE(1);
	90	}
	91
676012a6 AK	92	static inline void hash__local_flush_tlb_page(struct vm_area_struct *vma,
676012a6 AK	93	unsigned long vmaddr)
ee3b93eb AK	94	{
	95	}
	96
676012a6 AK	97	static inline void hash__flush_tlb_page(struct vm_area_struct *vma,
676012a6 AK	98	unsigned long vmaddr)
ee3b93eb AK	99	{
	100	}
	101
676012a6 AK	102	static inline void hash__flush_tlb_range(struct vm_area_struct *vma,
676012a6 AK	103	unsigned long start, unsigned long end)
ee3b93eb AK	104	{
	105	}
	106
676012a6 AK	107	static inline void hash__flush_tlb_kernel_range(unsigned long start,
676012a6 AK	108	unsigned long end)
ee3b93eb AK	109	{
	110	}
	111
676012a6 AK	112
	113	struct mmu_gather;
	114	extern void hash__tlb_flush(struct mmu_gather *tlb);
387e220a NP	115
387e220a NP	116	#ifdef CONFIG_PPC_64S_HASH_MMU
ee3b93eb	117	/* Private function for use by PCI IO mapping code */
7900757c	118	extern void __flush_hash_table_range(unsigned long start, unsigned long end);
d368e0c4	119	void flush_hash_table_pmd_range(struct mm_struct mm, pmd_t pmd, unsigned long addr);
387e220a NP	120	#else
	121	static inline void __flush_hash_table_range(unsigned long start, unsigned long end) { }
	122	#endif
ee3b93eb	123	#endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */