[linux-block.git] / arch / powerpc / include / asm / book3s / 64 / radix.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_PGTABLE_RADIX_H
#define _ASM_POWERPC_PGTABLE_RADIX_H

#include <asm/asm-const.h>

#ifndef __ASSEMBLY__
#include <asm/cmpxchg.h>
#endif

#ifdef CONFIG_PPC_64K_PAGES
#include <asm/book3s/64/radix-64k.h>
#else
#include <asm/book3s/64/radix-4k.h>
#endif

#ifndef __ASSEMBLY__
#include <asm/book3s/64/tlbflush-radix.h>
#include <asm/cpu_has_feature.h>
#endif

/* An empty PTE can still have a R or C writeback */
#define RADIX_PTE_NONE_MASK		(_PAGE_DIRTY | _PAGE_ACCESSED)

/* Bits to set in a RPMD/RPUD/RPGD */
#define RADIX_PMD_VAL_BITS		(0x8000000000000000UL | RADIX_PTE_INDEX_SIZE)
#define RADIX_PUD_VAL_BITS		(0x8000000000000000UL | RADIX_PMD_INDEX_SIZE)
#define RADIX_PGD_VAL_BITS		(0x8000000000000000UL | RADIX_PUD_INDEX_SIZE)

/* Don't have anything in the reserved bits and leaf bits */
#define RADIX_PMD_BAD_BITS		0x60000000000000e0UL
#define RADIX_PUD_BAD_BITS		0x60000000000000e0UL
#define RADIX_PGD_BAD_BITS		0x60000000000000e0UL

#define RADIX_PMD_SHIFT		(PAGE_SHIFT + RADIX_PTE_INDEX_SIZE)
#define RADIX_PUD_SHIFT		(RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE)
#define RADIX_PGD_SHIFT		(RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE)
/*
 * Size of EA range mapped by our pagetables.
 */
#define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE +	\
			      RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
#define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)

/*
 * We support 52 bit address space, Use top bit for kernel
 * virtual mapping. Also make sure kernel fit in the top
 * quadrant.
 *
 *           +------------------+
 *           +------------------+  Kernel virtual map (0xc008000000000000)
 *           |                  |
 *           |                  |
 *           |                  |
 * 0b11......+------------------+  Kernel linear map (0xc....)
 *           |                  |
 *           |     2 quadrant   |
 *           |                  |
 * 0b10......+------------------+
 *           |                  |
 *           |    1 quadrant    |
 *           |                  |
 * 0b01......+------------------+
 *           |                  |
 *           |    0 quadrant    |
 *           |                  |
 * 0b00......+------------------+
 *
 *
 * 3rd quadrant expanded:
 * +------------------------------+
 * |                              |
 * |                              |
 * |                              |
 * +------------------------------+  Kernel vmemmap end (0xc010000000000000)
 * |                              |
 * |           512TB		  |
 * |                              |
 * +------------------------------+  Kernel IO map end/vmemap start
 * |                              |
 * |           512TB		  |
 * |                              |
 * +------------------------------+  Kernel vmap end/ IO map start
 * |                              |
 * |           512TB		  |
 * |                              |
 * +------------------------------+  Kernel virt start (0xc008000000000000)
 * |                              |
 * |                              |
 * |                              |
 * +------------------------------+  Kernel linear (0xc.....)
 */

#define RADIX_KERN_VIRT_START	ASM_CONST(0xc008000000000000)
/*
 * 49 =  MAX_EA_BITS_PER_CONTEXT (hash specific). To make sure we pick
 * the same value as hash.
 */
#define RADIX_KERN_MAP_SIZE	(1UL << 49)

#define RADIX_VMALLOC_START	RADIX_KERN_VIRT_START
#define RADIX_VMALLOC_SIZE	RADIX_KERN_MAP_SIZE
#define RADIX_VMALLOC_END	(RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)

#define RADIX_KERN_IO_START	RADIX_VMALLOC_END
#define RADIX_KERN_IO_SIZE	RADIX_KERN_MAP_SIZE
#define RADIX_KERN_IO_END	(RADIX_KERN_IO_START + RADIX_KERN_IO_SIZE)

#define RADIX_VMEMMAP_START	RADIX_KERN_IO_END
#define RADIX_VMEMMAP_SIZE	RADIX_KERN_MAP_SIZE
#define RADIX_VMEMMAP_END	(RADIX_VMEMMAP_START + RADIX_VMEMMAP_SIZE)

#ifndef __ASSEMBLY__
#define RADIX_PTE_TABLE_SIZE	(sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
#define RADIX_PMD_TABLE_SIZE	(sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
#define RADIX_PUD_TABLE_SIZE	(sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
#define RADIX_PGD_TABLE_SIZE	(sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)

#ifdef CONFIG_STRICT_KERNEL_RWX
extern void radix__mark_rodata_ro(void);
extern void radix__mark_initmem_nx(void);
#endif

extern void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
					 pte_t entry, unsigned long address,
					 int psize);

extern void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
					   unsigned long addr, pte_t *ptep,
					   pte_t old_pte, pte_t pte);

static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
					       unsigned long set)
{
	__be64 old_be, tmp_be;

	__asm__ __volatile__(
	"1:	ldarx	%0,0,%3		# pte_update\n"
	"	andc	%1,%0,%5	\n"
	"	or	%1,%1,%4	\n"
	"	stdcx.	%1,0,%3		\n"
	"	bne-	1b"
	: "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
	: "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
	: "cc" );

	return be64_to_cpu(old_be);
}

static inline unsigned long radix__pte_update(struct mm_struct *mm,
					unsigned long addr,
					pte_t *ptep, unsigned long clr,
					unsigned long set,
					int huge)
{
	unsigned long old_pte;

	old_pte = __radix_pte_update(ptep, clr, set);
	if (!huge)
		assert_pte_locked(mm, addr);

	return old_pte;
}

static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
						   unsigned long addr,
						   pte_t *ptep, int full)
{
	unsigned long old_pte;

	if (full) {
		old_pte = pte_val(*ptep);
		*ptep = __pte(0);
	} else
		old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);

	return __pte(old_pte);
}

static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
{
	return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
}

static inline int radix__pte_none(pte_t pte)
{
	return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
}

static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
				 pte_t *ptep, pte_t pte, int percpu)
{
	*ptep = pte;

	/*
	 * The architecture suggests a ptesync after setting the pte, which
	 * orders the store that updates the pte with subsequent page table
	 * walk accesses which may load the pte. Without this it may be
	 * possible for a subsequent access to result in spurious fault.
	 *
	 * This is not necessary for correctness, because a spurious fault
	 * is tolerated by the page fault handler, and this store will
	 * eventually be seen. In testing, there was no noticable increase
	 * in user faults on POWER9. Avoiding ptesync here is a significant
	 * win for things like fork. If a future microarchitecture benefits
	 * from ptesync, it should probably go into update_mmu_cache, rather
	 * than set_pte_at (which is used to set ptes unrelated to faults).
	 *
	 * Spurious faults to vmalloc region are not tolerated, so there is
	 * a ptesync in flush_cache_vmap.
	 */
}

static inline int radix__pmd_bad(pmd_t pmd)
{
	return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
}

static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
{
	return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
}

static inline int radix__pud_bad(pud_t pud)
{
	return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
}


static inline int radix__pgd_bad(pgd_t pgd)
{
	return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
}

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

static inline int radix__pmd_trans_huge(pmd_t pmd)
{
	return (pmd_val(pmd) & (_PAGE_PTE | _PAGE_DEVMAP)) == _PAGE_PTE;
}

static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
{
	return __pmd(pmd_val(pmd) | _PAGE_PTE);
}

extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
					  pmd_t *pmdp, unsigned long clr,
					  unsigned long set);
extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
				  unsigned long address, pmd_t *pmdp);
extern void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
					pgtable_t pgtable);
extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
				      unsigned long addr, pmd_t *pmdp);
extern int radix__has_transparent_hugepage(void);
#endif

extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
					     unsigned long page_size,
					     unsigned long phys);
extern void radix__vmemmap_remove_mapping(unsigned long start,
				    unsigned long page_size);

extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
				 pgprot_t flags, unsigned int psz);

static inline unsigned long radix__get_tree_size(void)
{
	unsigned long rts_field;
	/*
	 * We support 52 bits, hence:
	 * bits 52 - 31 = 21, 0b10101
	 * RTS encoding details
	 * bits 0 - 3 of rts -> bits 6 - 8 unsigned long
	 * bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
	 */
	rts_field = (0x5UL << 5); /* 6 - 8 bits */
	rts_field |= (0x2UL << 61);

	return rts_field;
}

#ifdef CONFIG_MEMORY_HOTPLUG
int radix__create_section_mapping(unsigned long start, unsigned long end, int nid);
int radix__remove_section_mapping(unsigned long start, unsigned long end);
#endif /* CONFIG_MEMORY_HOTPLUG */
#endif /* __ASSEMBLY__ */
#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
b0b5e9b1 AK	2	#ifndef _ASM_POWERPC_PGTABLE_RADIX_H
	3	#define _ASM_POWERPC_PGTABLE_RADIX_H
	4
ec0c464c CL	5	#include <asm/asm-const.h>
ec0c464c CL	6
b0b5e9b1 AK	7	#ifndef __ASSEMBLY__
	8	#include <asm/cmpxchg.h>
	9	#endif
	10
	11	#ifdef CONFIG_PPC_64K_PAGES
	12	#include <asm/book3s/64/radix-64k.h>
	13	#else
	14	#include <asm/book3s/64/radix-4k.h>
	15	#endif
	16
c6d1a767 AK	17	#ifndef __ASSEMBLY__
	18	#include <asm/book3s/64/tlbflush-radix.h>
	19	#include <asm/cpu_has_feature.h>
	20	#endif
	21
b0b5e9b1 AK	22	/* An empty PTE can still have a R or C writeback */
	23	#define RADIX_PTE_NONE_MASK (_PAGE_DIRTY \| _PAGE_ACCESSED)
	24
	25	/* Bits to set in a RPMD/RPUD/RPGD */
	26	#define RADIX_PMD_VAL_BITS (0x8000000000000000UL \| RADIX_PTE_INDEX_SIZE)
	27	#define RADIX_PUD_VAL_BITS (0x8000000000000000UL \| RADIX_PMD_INDEX_SIZE)
	28	#define RADIX_PGD_VAL_BITS (0x8000000000000000UL \| RADIX_PUD_INDEX_SIZE)
	29
	30	/* Don't have anything in the reserved bits and leaf bits */
	31	#define RADIX_PMD_BAD_BITS 0x60000000000000e0UL
	32	#define RADIX_PUD_BAD_BITS 0x60000000000000e0UL
	33	#define RADIX_PGD_BAD_BITS 0x60000000000000e0UL
	34
a2dc009a AK	35	#define RADIX_PMD_SHIFT (PAGE_SHIFT + RADIX_PTE_INDEX_SIZE)
	36	#define RADIX_PUD_SHIFT (RADIX_PMD_SHIFT + RADIX_PMD_INDEX_SIZE)
	37	#define RADIX_PGD_SHIFT (RADIX_PUD_SHIFT + RADIX_PUD_INDEX_SIZE)
b0b5e9b1 AK	38	/*
	39	* Size of EA range mapped by our pagetables.
	40	*/
	41	#define RADIX_PGTABLE_EADDR_SIZE (RADIX_PTE_INDEX_SIZE + RADIX_PMD_INDEX_SIZE + \
	42	RADIX_PUD_INDEX_SIZE + RADIX_PGD_INDEX_SIZE + PAGE_SHIFT)
	43	#define RADIX_PGTABLE_RANGE (ASM_CONST(1) << RADIX_PGTABLE_EADDR_SIZE)
	44
d6a9996e AK	45	/*
	46	* We support 52 bit address space, Use top bit for kernel
	47	* virtual mapping. Also make sure kernel fit in the top
	48	* quadrant.
	49	*
	50	* +------------------+
	51	* +------------------+ Kernel virtual map (0xc008000000000000)
	52	* \| \|
	53	* \| \|
	54	* \| \|
	55	* 0b11......+------------------+ Kernel linear map (0xc....)
	56	* \| \|
	57	* \| 2 quadrant \|
	58	* \| \|
	59	* 0b10......+------------------+
	60	* \| \|
	61	* \| 1 quadrant \|
	62	* \| \|
	63	* 0b01......+------------------+
	64	* \| \|
	65	* \| 0 quadrant \|
	66	* \| \|
	67	* 0b00......+------------------+
	68	*
	69	*
	70	* 3rd quadrant expanded:
	71	* +------------------------------+
	72	* \| \|
	73	* \| \|
	74	* \| \|
0034d395	75	* +------------------------------+ Kernel vmemmap end (0xc010000000000000)
d6a9996e	76	* \| \|
0034d395	77	* \| 512TB \|
d6a9996e	78	* \| \|
0034d395	79	* +------------------------------+ Kernel IO map end/vmemap start
d6a9996e	80	* \| \|
0034d395	81	* \| 512TB \|
d6a9996e	82	* \| \|
0034d395	83	* +------------------------------+ Kernel vmap end/ IO map start
d6a9996e	84	* \| \|
0034d395	85	* \| 512TB \|
d6a9996e AK	86	* \| \|
	87	* +------------------------------+ Kernel virt start (0xc008000000000000)
	88	* \| \|
	89	* \| \|
	90	* \| \|
	91	* +------------------------------+ Kernel linear (0xc.....)
	92	*/
	93
0034d395	94	#define RADIX_KERN_VIRT_START ASM_CONST(0xc008000000000000)
d6a9996e	95	/*
0034d395 AK	96	* 49 = MAX_EA_BITS_PER_CONTEXT (hash specific). To make sure we pick
0034d395 AK	97	* the same value as hash.
d6a9996e	98	*/
0034d395 AK	99	#define RADIX_KERN_MAP_SIZE (1UL << 49)
0034d395 AK	100
d6a9996e	101	#define RADIX_VMALLOC_START RADIX_KERN_VIRT_START
0034d395	102	#define RADIX_VMALLOC_SIZE RADIX_KERN_MAP_SIZE
d6a9996e	103	#define RADIX_VMALLOC_END (RADIX_VMALLOC_START + RADIX_VMALLOC_SIZE)
d6a9996e	104
0034d395 AK	105	#define RADIX_KERN_IO_START RADIX_VMALLOC_END
	106	#define RADIX_KERN_IO_SIZE RADIX_KERN_MAP_SIZE
	107	#define RADIX_KERN_IO_END (RADIX_KERN_IO_START + RADIX_KERN_IO_SIZE)
	108
	109	#define RADIX_VMEMMAP_START RADIX_KERN_IO_END
	110	#define RADIX_VMEMMAP_SIZE RADIX_KERN_MAP_SIZE
	111	#define RADIX_VMEMMAP_END (RADIX_VMEMMAP_START + RADIX_VMEMMAP_SIZE)
63ee9b2f	112
b0b5e9b1 AK	113	#ifndef __ASSEMBLY__
	114	#define RADIX_PTE_TABLE_SIZE (sizeof(pte_t) << RADIX_PTE_INDEX_SIZE)
	115	#define RADIX_PMD_TABLE_SIZE (sizeof(pmd_t) << RADIX_PMD_INDEX_SIZE)
	116	#define RADIX_PUD_TABLE_SIZE (sizeof(pud_t) << RADIX_PUD_INDEX_SIZE)
	117	#define RADIX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
	118
cd65d697 BS	119	#ifdef CONFIG_STRICT_KERNEL_RWX
cd65d697 BS	120	extern void radix__mark_rodata_ro(void);
029d9252	121	extern void radix__mark_initmem_nx(void);
cd65d697 BS	122	#endif
cd65d697 BS	123
e4c1112c AK	124	extern void radix__ptep_set_access_flags(struct vm_area_struct vma, pte_t ptep,
	125	pte_t entry, unsigned long address,
	126	int psize);
044003b5	127
5b323367 AK	128	extern void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
	129	unsigned long addr, pte_t *ptep,
	130	pte_t old_pte, pte_t pte);
	131
c6d1a767 AK	132	static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr,
c6d1a767 AK	133	unsigned long set)
b0b5e9b1	134	{
85bcfaf6 NP	135	__be64 old_be, tmp_be;
	136
	137	__asm__ __volatile__(
	138	"1: ldarx %0,0,%3 # pte_update\n"
	139	" andc %1,%0,%5 \n"
	140	" or %1,%1,%4 \n"
	141	" stdcx. %1,0,%3 \n"
	142	" bne- 1b"
	143	: "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
	144	: "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr))
	145	: "cc" );
	146
	147	return be64_to_cpu(old_be);
c6d1a767 AK	148	}
c6d1a767 AK	149
c6d1a767 AK	150	static inline unsigned long radix__pte_update(struct mm_struct *mm,
	151	unsigned long addr,
	152	pte_t *ptep, unsigned long clr,
	153	unsigned long set,
	154	int huge)
	155	{
	156	unsigned long old_pte;
	157
2bf1071a	158	old_pte = __radix_pte_update(ptep, clr, set);
b0b5e9b1 AK	159	if (!huge)
	160	assert_pte_locked(mm, addr);
	161
	162	return old_pte;
	163	}
	164
f4894b80 AK	165	static inline pte_t radix__ptep_get_and_clear_full(struct mm_struct *mm,
	166	unsigned long addr,
	167	pte_t *ptep, int full)
	168	{
	169	unsigned long old_pte;
	170
	171	if (full) {
f569bd94 NP	172	old_pte = pte_val(*ptep);
f569bd94 NP	173	*ptep = __pte(0);
f4894b80 AK	174	} else
	175	old_pte = radix__pte_update(mm, addr, ptep, ~0ul, 0, 0);
	176
	177	return __pte(old_pte);
	178	}
	179
b0b5e9b1 AK	180	static inline int radix__pte_same(pte_t pte_a, pte_t pte_b)
	181	{
	182	return ((pte_raw(pte_a) ^ pte_raw(pte_b)) == 0);
	183	}
	184
	185	static inline int radix__pte_none(pte_t pte)
	186	{
	187	return (pte_val(pte) & ~RADIX_PTE_NONE_MASK) == 0;
	188	}
	189
	190	static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
	191	pte_t *ptep, pte_t pte, int percpu)
	192	{
	193	*ptep = pte;
f1cb8f9b NP	194
	195	/*
	196	* The architecture suggests a ptesync after setting the pte, which
	197	* orders the store that updates the pte with subsequent page table
	198	* walk accesses which may load the pte. Without this it may be
	199	* possible for a subsequent access to result in spurious fault.
	200	*
	201	* This is not necessary for correctness, because a spurious fault
	202	* is tolerated by the page fault handler, and this store will
	203	* eventually be seen. In testing, there was no noticable increase
	204	* in user faults on POWER9. Avoiding ptesync here is a significant
	205	* win for things like fork. If a future microarchitecture benefits
	206	* from ptesync, it should probably go into update_mmu_cache, rather
	207	* than set_pte_at (which is used to set ptes unrelated to faults).
	208	*
	209	* Spurious faults to vmalloc region are not tolerated, so there is
	210	* a ptesync in flush_cache_vmap.
	211	*/
b0b5e9b1 AK	212	}
	213
	214	static inline int radix__pmd_bad(pmd_t pmd)
	215	{
	216	return !!(pmd_val(pmd) & RADIX_PMD_BAD_BITS);
	217	}
	218
	219	static inline int radix__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
	220	{
	221	return ((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) == 0);
	222	}
	223
	224	static inline int radix__pud_bad(pud_t pud)
	225	{
	226	return !!(pud_val(pud) & RADIX_PUD_BAD_BITS);
	227	}
	228
	229
	230	static inline int radix__pgd_bad(pgd_t pgd)
	231	{
	232	return !!(pgd_val(pgd) & RADIX_PGD_BAD_BITS);
	233	}
	234
6cc1a0ee AK	235	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	236
	237	static inline int radix__pmd_trans_huge(pmd_t pmd)
	238	{
ebd31197	239	return (pmd_val(pmd) & (_PAGE_PTE \| _PAGE_DEVMAP)) == _PAGE_PTE;
6cc1a0ee AK	240	}
6cc1a0ee AK	241
bde3eb62 AK	242	static inline pmd_t radix__pmd_mkhuge(pmd_t pmd)
	243	{
	244	return __pmd(pmd_val(pmd) \| _PAGE_PTE);
	245	}
bde3eb62 AK	246
	247	extern unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
	248	pmd_t *pmdp, unsigned long clr,
	249	unsigned long set);
	250	extern pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma,
	251	unsigned long address, pmd_t *pmdp);
	252	extern void radix__pgtable_trans_huge_deposit(struct mm_struct mm, pmd_t pmdp,
	253	pgtable_t pgtable);
	254	extern pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct mm, pmd_t pmdp);
	255	extern pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
	256	unsigned long addr, pmd_t *pmdp);
	257	extern int radix__has_transparent_hugepage(void);
6cc1a0ee AK	258	#endif
6cc1a0ee AK	259
d9225ad9 AK	260	extern int __meminit radix__vmemmap_create_mapping(unsigned long start,
	261	unsigned long page_size,
	262	unsigned long phys);
	263	extern void radix__vmemmap_remove_mapping(unsigned long start,
	264	unsigned long page_size);
	265
2bfd65e4 AK	266	extern int radix__map_kernel_page(unsigned long ea, unsigned long pa,
2bfd65e4 AK	267	pgprot_t flags, unsigned int psz);
b23d9c5b AK	268
	269	static inline unsigned long radix__get_tree_size(void)
	270	{
	271	unsigned long rts_field;
	272	/*
694c4951	273	* We support 52 bits, hence:
2bf1071a	274	* bits 52 - 31 = 21, 0b10101
b23d9c5b AK	275	* RTS encoding details
	276	* bits 0 - 3 of rts -> bits 6 - 8 unsigned long
	277	* bits 4 - 5 of rts -> bits 62 - 63 of unsigned long
	278	*/
2bf1071a NP	279	rts_field = (0x5UL << 5); /* 6 - 8 bits */
	280	rts_field \|= (0x2UL << 61);
	281
b23d9c5b AK	282	return rts_field;
b23d9c5b AK	283	}
6cc27341 RA	284
6cc27341 RA	285	#ifdef CONFIG_MEMORY_HOTPLUG
29ab6c47	286	int radix__create_section_mapping(unsigned long start, unsigned long end, int nid);
4b5d62ca	287	int radix__remove_section_mapping(unsigned long start, unsigned long end);
6cc27341	288	#endif /* CONFIG_MEMORY_HOTPLUG */
b0b5e9b1 AK	289	#endif /* __ASSEMBLY__ */
b0b5e9b1 AK	290	#endif