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powerpc/mm/book3s/64: Add proper pte access check helper
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
3dfcb315
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519 4
9849a569
KS		 5#include <asm-generic/5level-fixup.h>
6
c137a275
AK		 7#ifndef __ASSEMBLY__
8#include <linux/mmdebug.h>
ebd31197 9#include <linux/bug.h>
c137a275 10#endif
9849a569 11
2e873519
AK		 12/*
13 * Common bits between hash and Radix page table
14 */
15#define _PAGE_BIT_SWAP_TYPE 0
16
6b8cb66a 17#define _PAGE_RO 0
fd893fe5 18#define _PAGE_SHARED 0
6b8cb66a 19
2e873519
AK		 20#define _PAGE_EXEC 0x00001 /* execute permission */
21#define _PAGE_WRITE 0x00002 /* write access allowed */
22#define _PAGE_READ 0x00004 /* read access allowed */
23#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
24#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
25#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
26#define _PAGE_SAO 0x00010 /* Strong access order */
27#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
28#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
29#define _PAGE_DIRTY 0x00080 /* C: page changed */
30#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 31/*
2e873519 32 * Software bits
3dfcb315 33 */
69dfbaeb
AK		 34#define _RPAGE_SW0 0x2000000000000000UL
35#define _RPAGE_SW1 0x00800
36#define _RPAGE_SW2 0x00400
37#define _RPAGE_SW3 0x00200
049d567a
AK		 38#define _RPAGE_RSV1 0x1000000000000000UL
39#define _RPAGE_RSV2 0x0800000000000000UL
40#define _RPAGE_RSV3 0x0400000000000000UL
41#define _RPAGE_RSV4 0x0200000000000000UL
6aa59f51
AK		 42
43#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
44#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
45
46/*
47 * Top and bottom bits of RPN which can be used by hash
48 * translation mode, because we expect them to be zero
49 * otherwise.
50 */
32789d38
AK		 51#define _RPAGE_RPN0 0x01000
52#define _RPAGE_RPN1 0x02000
6aa59f51
AK		 53#define _RPAGE_RPN44 0x0100000000000000UL
54#define _RPAGE_RPN43 0x0080000000000000UL
55#define _RPAGE_RPN42 0x0040000000000000UL
56#define _RPAGE_RPN41 0x0020000000000000UL
049d567a 57
2f18d533
AK		 58/* Max physical address bit as per radix table */
59#define _RPAGE_PA_MAX 57
60
61/*
62 * Max physical address bit we will use for now.
63 *
64 * This is mostly a hardware limitation and for now Power9 has
65 * a 51 bit limit.
66 *
67 * This is different from the number of physical bit required to address
68 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
69 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
70 * number of sections we can support (SECTIONS_SHIFT).
71 *
72 * This is different from Radix page table limitation above and
73 * should always be less than that. The limit is done such that
74 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
75 * for hash linux page table specific bits.
76 *
77 * In order to be compatible with future hardware generations we keep
78 * some offsets and limit this for now to 53
79 */
80#define _PAGE_PA_MAX 53
81
69dfbaeb 82#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
69dfbaeb 83#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
ebd31197
OH		 84#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
85#define __HAVE_ARCH_PTE_DEVMAP
86
2e873519
AK		 87/*
88 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
89 * Instead of fixing all of them, add an alternate define which
90 * maps CI pte mapping.
91 */
92#define _PAGE_NO_CACHE _PAGE_TOLERANT
93/*
2f18d533
AK		 94 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
95 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
96 * and every thing below PAGE_SHIFT;
2e873519 97 */
2f18d533 98#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
2e873519
AK		 99/*
100 * set of bits not changed in pmd_modify. Even though we have hash specific bits
101 * in here, on radix we expect them to be zero.
102 */
103#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
104 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
105 _PAGE_SOFT_DIRTY)
106/*
107 * user access blocked by key
108 */
109#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
110#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
111#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
112 _PAGE_RW | _PAGE_EXEC)
113/*
114 * No page size encoding in the linux PTE
115 */
116#define _PAGE_PSIZE 0
117/*
118 * _PAGE_CHG_MASK masks of bits that are to be preserved across
119 * pgprot changes
120 */
121#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
122 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
123 _PAGE_SOFT_DIRTY)
124/*
125 * Mask of bits returned by pte_pgprot()
126 */
127#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
128 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
129 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
130 _PAGE_SOFT_DIRTY)
3dfcb315 131/*
2e873519
AK		 132 * We define 2 sets of base prot bits, one for basic pages (ie,
133 * cacheable kernel and user pages) and one for non cacheable
134 * pages. We always set _PAGE_COHERENT when SMP is enabled or
135 * the processor might need it for DMA coherency.
3dfcb315 136 */
2e873519
AK		 137#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
138#define _PAGE_BASE (_PAGE_BASE_NC)
139
140/* Permission masks used to generate the __P and __S table,
141 *
142 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
143 *
144 * Write permissions imply read permissions for now (we could make write-only
145 * pages on BookE but we don't bother for now). Execute permission control is
146 * possible on platforms that define _PAGE_EXEC
147 *
148 * Note due to the way vm flags are laid out, the bits are XWR
149 */
150#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
151#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
152#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
153#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
154#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
155#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
156#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
157
158#define __P000 PAGE_NONE
159#define __P001 PAGE_READONLY
160#define __P010 PAGE_COPY
161#define __P011 PAGE_COPY
162#define __P100 PAGE_READONLY_X
163#define __P101 PAGE_READONLY_X
164#define __P110 PAGE_COPY_X
165#define __P111 PAGE_COPY_X
166
167#define __S000 PAGE_NONE
168#define __S001 PAGE_READONLY
169#define __S010 PAGE_SHARED
170#define __S011 PAGE_SHARED
171#define __S100 PAGE_READONLY_X
172#define __S101 PAGE_READONLY_X
173#define __S110 PAGE_SHARED_X
174#define __S111 PAGE_SHARED_X
175
176/* Permission masks used for kernel mappings */
177#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
178#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
179 _PAGE_TOLERANT)
180#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
181 _PAGE_NON_IDEMPOTENT)
182#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
183#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
184#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
185
186/*
187 * Protection used for kernel text. We want the debuggers to be able to
188 * set breakpoints anywhere, so don't write protect the kernel text
189 * on platforms where such control is possible.
190 */
191#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
192 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
193#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
194#else
195#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
196#endif
197
198/* Make modules code happy. We don't set RO yet */
199#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
200#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 201
dd1842a2
AK		 202#ifndef __ASSEMBLY__
203/*
204 * page table defines
205 */
206extern unsigned long __pte_index_size;
207extern unsigned long __pmd_index_size;
208extern unsigned long __pud_index_size;
209extern unsigned long __pgd_index_size;
210extern unsigned long __pmd_cache_index;
211#define PTE_INDEX_SIZE __pte_index_size
212#define PMD_INDEX_SIZE __pmd_index_size
213#define PUD_INDEX_SIZE __pud_index_size
214#define PGD_INDEX_SIZE __pgd_index_size
215#define PMD_CACHE_INDEX __pmd_cache_index
216/*
217 * Because of use of pte fragments and THP, size of page table
218 * are not always derived out of index size above.
219 */
220extern unsigned long __pte_table_size;
221extern unsigned long __pmd_table_size;
222extern unsigned long __pud_table_size;
223extern unsigned long __pgd_table_size;
224#define PTE_TABLE_SIZE __pte_table_size
225#define PMD_TABLE_SIZE __pmd_table_size
226#define PUD_TABLE_SIZE __pud_table_size
227#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 228
229extern unsigned long __pmd_val_bits;
230extern unsigned long __pud_val_bits;
231extern unsigned long __pgd_val_bits;
232#define PMD_VAL_BITS __pmd_val_bits
233#define PUD_VAL_BITS __pud_val_bits
234#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 235
236extern unsigned long __pte_frag_nr;
237#define PTE_FRAG_NR __pte_frag_nr
238extern unsigned long __pte_frag_size_shift;
239#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
240#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2
AK		 241
242#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
243#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
244#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
245#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
246
247/* PMD_SHIFT determines what a second-level page table entry can map */
248#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
249#define PMD_SIZE (1UL << PMD_SHIFT)
250#define PMD_MASK (~(PMD_SIZE-1))
251
252/* PUD_SHIFT determines what a third-level page table entry can map */
253#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
254#define PUD_SIZE (1UL << PUD_SHIFT)
255#define PUD_MASK (~(PUD_SIZE-1))
256
257/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
258#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
259#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
260#define PGDIR_MASK (~(PGDIR_SIZE-1))
261
262/* Bits to mask out from a PMD to get to the PTE page */
263#define PMD_MASKED_BITS 0xc0000000000000ffUL
264/* Bits to mask out from a PUD to get to the PMD page */
265#define PUD_MASKED_BITS 0xc0000000000000ffUL
266/* Bits to mask out from a PGD to get to the PUD page */
267#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e
AK		 268
269extern unsigned long __vmalloc_start;
270extern unsigned long __vmalloc_end;
271#define VMALLOC_START __vmalloc_start
272#define VMALLOC_END __vmalloc_end
273
274extern unsigned long __kernel_virt_start;
275extern unsigned long __kernel_virt_size;
63ee9b2f 276extern unsigned long __kernel_io_start;
d6a9996e
AK		 277#define KERN_VIRT_START __kernel_virt_start
278#define KERN_VIRT_SIZE __kernel_virt_size
63ee9b2f 279#define KERN_IO_START __kernel_io_start
d6a9996e
AK		 280extern struct page *vmemmap;
281extern unsigned long ioremap_bot;
bfa37087 282extern unsigned long pci_io_base;
dd1842a2 283#endif /* __ASSEMBLY__ */
3dfcb315 284
ab537dca 285#include <asm/book3s/64/hash.h>
b0b5e9b1 286#include <asm/book3s/64/radix.h>
3dfcb315 287
a9252aae
AK		 288#ifdef CONFIG_PPC_64K_PAGES
289#include <asm/book3s/64/pgtable-64k.h>
290#else
291#include <asm/book3s/64/pgtable-4k.h>
292#endif
293
3dfcb315 294#include <asm/barrier.h>
3dfcb315
AK		 295/*
296 * The second half of the kernel virtual space is used for IO mappings,
297 * it's itself carved into the PIO region (ISA and PHB IO space) and
298 * the ioremap space
299 *
300 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
301 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
302 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
303 */
3dfcb315
AK		 304#define FULL_IO_SIZE 0x80000000ul
305#define ISA_IO_BASE (KERN_IO_START)
306#define ISA_IO_END (KERN_IO_START + 0x10000ul)
307#define PHB_IO_BASE (ISA_IO_END)
308#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
309#define IOREMAP_BASE (PHB_IO_END)
310#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
311
b0412ea9 312/* Advertise special mapping type for AGP */
b0412ea9
AK		 313#define HAVE_PAGE_AGP
314
315/* Advertise support for _PAGE_SPECIAL */
316#define __HAVE_ARCH_PTE_SPECIAL
317
3dfcb315
AK		 318#ifndef __ASSEMBLY__
319
320/*
321 * This is the default implementation of various PTE accessors, it's
322 * used in all cases except Book3S with 64K pages where we have a
323 * concept of sub-pages
324 */
325#ifndef __real_pte
326
3dfcb315
AK		 327#define __real_pte(e,p) ((real_pte_t){(e)})
328#define __rpte_to_pte(r) ((r).pte)
945537df 329#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 330
331#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
332 do { \
333 index = 0; \
334 shift = mmu_psize_defs[psize].shift; \
335
336#define pte_iterate_hashed_end() } while(0)
337
338/*
339 * We expect this to be called only for user addresses or kernel virtual
340 * addresses other than the linear mapping.
341 */
342#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
343
344#endif /* __real_pte */
345
ac94ac79
AK		 346static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
347 pte_t *ptep, unsigned long clr,
348 unsigned long set, int huge)
349{
350 if (radix_enabled())
351 return radix__pte_update(mm, addr, ptep, clr, set, huge);
352 return hash__pte_update(mm, addr, ptep, clr, set, huge);
353}
13f829a5
AK		 354/*
355 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
356 * We currently remove entries from the hashtable regardless of whether
357 * the entry was young or dirty.
358 *
359 * We should be more intelligent about this but for the moment we override
360 * these functions and force a tlb flush unconditionally
361 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
362 * function for both hash and radix.
363 */
364static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
365 unsigned long addr, pte_t *ptep)
366{
367 unsigned long old;
368
66c570f5 369 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 370 return 0;
371 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
372 return (old & _PAGE_ACCESSED) != 0;
373}
374
375#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
376#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
377({ \
378 int __r; \
379 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
380 __r; \
381})
382
d19469e8 383static inline int __pte_write(pte_t pte)
52c50ca7
AK		 384{
385 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
386}
387
388#ifdef CONFIG_NUMA_BALANCING
389#define pte_savedwrite pte_savedwrite
390static inline bool pte_savedwrite(pte_t pte)
391{
392 /*
393 * Saved write ptes are prot none ptes that doesn't have
394 * privileged bit sit. We mark prot none as one which has
395 * present and pviliged bit set and RWX cleared. To mark
396 * protnone which used to have _PAGE_WRITE set we clear
397 * the privileged bit.
398 */
399 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
400}
401#else
402#define pte_savedwrite pte_savedwrite
403static inline bool pte_savedwrite(pte_t pte)
404{
405 return false;
406}
407#endif
408
d19469e8
AK		 409static inline int pte_write(pte_t pte)
410{
411 return __pte_write(pte) || pte_savedwrite(pte);
412}
413
ca8afd40
CL		 414static inline int pte_read(pte_t pte)
415{
416 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
417}
418
13f829a5
AK		 419#define __HAVE_ARCH_PTEP_SET_WRPROTECT
420static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
421 pte_t *ptep)
422{
d19469e8 423 if (__pte_write(*ptep))
52c50ca7
AK		 424 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
425 else if (unlikely(pte_savedwrite(*ptep)))
426 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
13f829a5
AK		 427}
428
429static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
430 unsigned long addr, pte_t *ptep)
431{
52c50ca7
AK		 432 /*
433 * We should not find protnone for hugetlb, but this complete the
434 * interface.
435 */
d19469e8 436 if (__pte_write(*ptep))
52c50ca7
AK		 437 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
438 else if (unlikely(pte_savedwrite(*ptep)))
439 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
13f829a5
AK		 440}
441
442#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
443static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
444 unsigned long addr, pte_t *ptep)
445{
446 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
447 return __pte(old);
448}
449
f4894b80
AK		 450#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
451static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
452 unsigned long addr,
453 pte_t *ptep, int full)
454{
455 if (full && radix_enabled()) {
456 /*
457 * Let's skip the DD1 style pte update here. We know that
458 * this is a full mm pte clear and hence can be sure there is
459 * no parallel set_pte.
460 */
461 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
462 }
463 return ptep_get_and_clear(mm, addr, ptep);
464}
465
466
13f829a5
AK		 467static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
468 pte_t * ptep)
469{
470 pte_update(mm, addr, ptep, ~0UL, 0, 0);
471}
66c570f5 472
66c570f5
AK		 473static inline int pte_dirty(pte_t pte)
474{
475 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
476}
477
478static inline int pte_young(pte_t pte)
479{
480 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
481}
482
483static inline int pte_special(pte_t pte)
484{
485 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
486}
487
13f829a5
AK		 488static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
489
490#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
491static inline bool pte_soft_dirty(pte_t pte)
492{
66c570f5 493 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 494}
66c570f5 495
13f829a5
AK		 496static inline pte_t pte_mksoft_dirty(pte_t pte)
497{
498 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
499}
500
501static inline pte_t pte_clear_soft_dirty(pte_t pte)
502{
503 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
504}
505#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
506
507#ifdef CONFIG_NUMA_BALANCING
13f829a5
AK		 508static inline int pte_protnone(pte_t pte)
509{
c137a275
AK		 510 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
511 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
512}
513
514#define pte_mk_savedwrite pte_mk_savedwrite
515static inline pte_t pte_mk_savedwrite(pte_t pte)
516{
517 /*
518 * Used by Autonuma subsystem to preserve the write bit
519 * while marking the pte PROT_NONE. Only allow this
520 * on PROT_NONE pte
521 */
522 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
523 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
524 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
525}
526
527#define pte_clear_savedwrite pte_clear_savedwrite
528static inline pte_t pte_clear_savedwrite(pte_t pte)
529{
530 /*
531 * Used by KSM subsystem to make a protnone pte readonly.
532 */
533 VM_BUG_ON(!pte_protnone(pte));
534 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
535}
d19469e8
AK		 536#else
537#define pte_clear_savedwrite pte_clear_savedwrite
538static inline pte_t pte_clear_savedwrite(pte_t pte)
539{
540 VM_WARN_ON(1);
541 return __pte(pte_val(pte) & ~_PAGE_WRITE);
542}
13f829a5
AK		 543#endif /* CONFIG_NUMA_BALANCING */
544
545static inline int pte_present(pte_t pte)
546{
66c570f5 547 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
13f829a5 548}
f72a85e3
AK		 549
550#define pte_access_permitted pte_access_permitted
551static inline bool pte_access_permitted(pte_t pte, bool write)
552{
553 unsigned long pteval = pte_val(pte);
554 /* Also check for pte_user */
555 unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
556 /*
557 * _PAGE_READ is needed for any access and will be
558 * cleared for PROT_NONE
559 */
560 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
561
562 if (write)
563 need_pte_bits |= _PAGE_WRITE;
564
565 if ((pteval & need_pte_bits) != need_pte_bits)
566 return false;
567
568 if ((pteval & clear_pte_bits) == clear_pte_bits)
569 return false;
570 return true;
571}
572
13f829a5
AK		 573/*
574 * Conversion functions: convert a page and protection to a page entry,
575 * and a page entry and page directory to the page they refer to.
576 *
577 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
578 * long for now.
579 */
580static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
581{
582 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
583 pgprot_val(pgprot));
584}
585
586static inline unsigned long pte_pfn(pte_t pte)
587{
588 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
589}
590
591/* Generic modifiers for PTE bits */
592static inline pte_t pte_wrprotect(pte_t pte)
593{
d19469e8
AK		 594 if (unlikely(pte_savedwrite(pte)))
595 return pte_clear_savedwrite(pte);
13f829a5
AK		 596 return __pte(pte_val(pte) & ~_PAGE_WRITE);
597}
598
599static inline pte_t pte_mkclean(pte_t pte)
600{
601 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
602}
603
604static inline pte_t pte_mkold(pte_t pte)
605{
606 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
607}
608
609static inline pte_t pte_mkwrite(pte_t pte)
610{
611 /*
612 * write implies read, hence set both
613 */
614 return __pte(pte_val(pte) | _PAGE_RW);
615}
616
617static inline pte_t pte_mkdirty(pte_t pte)
618{
619 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
620}
621
622static inline pte_t pte_mkyoung(pte_t pte)
623{
624 return __pte(pte_val(pte) | _PAGE_ACCESSED);
625}
626
627static inline pte_t pte_mkspecial(pte_t pte)
628{
629 return __pte(pte_val(pte) | _PAGE_SPECIAL);
630}
631
632static inline pte_t pte_mkhuge(pte_t pte)
633{
634 return pte;
635}
636
ebd31197
OH		 637static inline pte_t pte_mkdevmap(pte_t pte)
638{
639 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
640}
641
c9c98bc5
OH		 642/*
643 * This is potentially called with a pmd as the argument, in which case it's not
644 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
645 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
646 * use in page directory entries (ie. non-ptes).
647 */
ebd31197
OH		 648static inline int pte_devmap(pte_t pte)
649{
c9c98bc5
OH		 650 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
651
652 return (pte_raw(pte) & mask) == mask;
ebd31197
OH		 653}
654
13f829a5
AK		 655static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
656{
657 /* FIXME!! check whether this need to be a conditional */
658 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
659}
660
34fbadd8
AK		 661static inline bool pte_user(pte_t pte)
662{
66c570f5 663 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
34fbadd8
AK		 664}
665
666/* Encode and de-code a swap entry */
667#define MAX_SWAPFILES_CHECK() do { \
668 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
669 /* \
670 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
671 * We filter HPTEFLAGS on set_pte. \
672 */ \
673 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
674 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
675 } while (0)
676/*
677 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
678 */
679#define SWP_TYPE_BITS 5
680#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
681 & ((1UL << SWP_TYPE_BITS) - 1))
682#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
683#define __swp_entry(type, offset) ((swp_entry_t) { \
684 ((type) << _PAGE_BIT_SWAP_TYPE) \
685 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
686/*
687 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
688 * swap type and offset we get from swap and convert that to pte to find a
689 * matching pte in linux page table.
690 * Clear bits not found in swap entries here.
691 */
692#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
693#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
694
695#ifdef CONFIG_MEM_SOFT_DIRTY
696#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
697#else
698#define _PAGE_SWP_SOFT_DIRTY 0UL
699#endif /* CONFIG_MEM_SOFT_DIRTY */
700
701#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
702static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
703{
704 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
705}
66c570f5 706
34fbadd8
AK		 707static inline bool pte_swp_soft_dirty(pte_t pte)
708{
66c570f5 709 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 710}
66c570f5 711
34fbadd8
AK		 712static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
713{
714 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
715}
716#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
717
718static inline bool check_pte_access(unsigned long access, unsigned long ptev)
719{
720 /*
721 * This check for _PAGE_RWX and _PAGE_PRESENT bits
722 */
723 if (access & ~ptev)
724 return false;
725 /*
726 * This check for access to privilege space
727 */
728 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
729 return false;
730
731 return true;
732}
ac94ac79
AK		 733/*
734 * Generic functions with hash/radix callbacks
735 */
736
c6d1a767 737static inline void __ptep_set_access_flags(struct mm_struct *mm,
b3603e17
AK		 738 pte_t *ptep, pte_t entry,
739 unsigned long address)
ac94ac79
AK		 740{
741 if (radix_enabled())
b3603e17 742 return radix__ptep_set_access_flags(mm, ptep, entry, address);
ac94ac79
AK		 743 return hash__ptep_set_access_flags(ptep, entry);
744}
745
746#define __HAVE_ARCH_PTE_SAME
747static inline int pte_same(pte_t pte_a, pte_t pte_b)
748{
749 if (radix_enabled())
750 return radix__pte_same(pte_a, pte_b);
751 return hash__pte_same(pte_a, pte_b);
752}
753
754static inline int pte_none(pte_t pte)
755{
756 if (radix_enabled())
757 return radix__pte_none(pte);
758 return hash__pte_none(pte);
759}
760
761static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
762 pte_t *ptep, pte_t pte, int percpu)
763{
764 if (radix_enabled())
765 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
766 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
767}
34fbadd8 768
13f829a5
AK		 769#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
770
771#define pgprot_noncached pgprot_noncached
772static inline pgprot_t pgprot_noncached(pgprot_t prot)
773{
774 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
775 _PAGE_NON_IDEMPOTENT);
776}
777
778#define pgprot_noncached_wc pgprot_noncached_wc
779static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
780{
781 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
782 _PAGE_TOLERANT);
783}
784
785#define pgprot_cached pgprot_cached
786static inline pgprot_t pgprot_cached(pgprot_t prot)
787{
788 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
789}
790
791#define pgprot_writecombine pgprot_writecombine
792static inline pgprot_t pgprot_writecombine(pgprot_t prot)
793{
794 return pgprot_noncached_wc(prot);
795}
796/*
797 * check a pte mapping have cache inhibited property
798 */
799static inline bool pte_ci(pte_t pte)
800{
801 unsigned long pte_v = pte_val(pte);
802
803 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
804 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
805 return true;
806 return false;
807}
808
f281b5d5
AK		 809static inline void pmd_set(pmd_t *pmdp, unsigned long val)
810{
811 *pmdp = __pmd(val);
812}
813
814static inline void pmd_clear(pmd_t *pmdp)
815{
816 *pmdp = __pmd(0);
817}
818
66c570f5
AK		 819static inline int pmd_none(pmd_t pmd)
820{
821 return !pmd_raw(pmd);
822}
823
824static inline int pmd_present(pmd_t pmd)
825{
826
827 return !pmd_none(pmd);
828}
3dfcb315 829
ac94ac79
AK		 830static inline int pmd_bad(pmd_t pmd)
831{
832 if (radix_enabled())
833 return radix__pmd_bad(pmd);
834 return hash__pmd_bad(pmd);
835}
836
f281b5d5
AK		 837static inline void pud_set(pud_t *pudp, unsigned long val)
838{
839 *pudp = __pud(val);
840}
841
842static inline void pud_clear(pud_t *pudp)
843{
844 *pudp = __pud(0);
845}
846
66c570f5
AK		 847static inline int pud_none(pud_t pud)
848{
849 return !pud_raw(pud);
850}
851
852static inline int pud_present(pud_t pud)
853{
854 return !pud_none(pud);
855}
3dfcb315
AK		 856
857extern struct page *pud_page(pud_t pud);
371352ca 858extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 859static inline pte_t pud_pte(pud_t pud)
860{
66c570f5 861 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 862}
863
864static inline pud_t pte_pud(pte_t pte)
865{
66c570f5 866 return __pud_raw(pte_raw(pte));
3dfcb315
AK		 867}
868#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 869
870static inline int pud_bad(pud_t pud)
871{
872 if (radix_enabled())
873 return radix__pud_bad(pud);
874 return hash__pud_bad(pud);
875}
876
f72a85e3
AK		 877#define pud_access_permitted pud_access_permitted
878static inline bool pud_access_permitted(pud_t pud, bool write)
879{
880 return pte_access_permitted(pud_pte(pud), write);
881}
ac94ac79 882
3dfcb315 883#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 884static inline void pgd_set(pgd_t *pgdp, unsigned long val)
885{
886 *pgdp = __pgd(val);
887}
3dfcb315 888
368ced78
AK		 889static inline void pgd_clear(pgd_t *pgdp)
890{
891 *pgdp = __pgd(0);
892}
893
66c570f5
AK		 894static inline int pgd_none(pgd_t pgd)
895{
896 return !pgd_raw(pgd);
897}
898
899static inline int pgd_present(pgd_t pgd)
900{
901 return !pgd_none(pgd);
902}
368ced78
AK		 903
904static inline pte_t pgd_pte(pgd_t pgd)
905{
66c570f5 906 return __pte_raw(pgd_raw(pgd));
368ced78
AK		 907}
908
909static inline pgd_t pte_pgd(pte_t pte)
910{
66c570f5 911 return __pgd_raw(pte_raw(pte));
368ced78
AK		 912}
913
ac94ac79
AK		 914static inline int pgd_bad(pgd_t pgd)
915{
916 if (radix_enabled())
917 return radix__pgd_bad(pgd);
918 return hash__pgd_bad(pgd);
919}
920
f72a85e3
AK		 921#define pgd_access_permitted pgd_access_permitted
922static inline bool pgd_access_permitted(pgd_t pgd, bool write)
923{
924 return pte_access_permitted(pgd_pte(pgd), write);
925}
926
368ced78
AK		 927extern struct page *pgd_page(pgd_t pgd);
928
aba480e1
AK		 929/* Pointers in the page table tree are physical addresses */
930#define __pgtable_ptr_val(ptr) __pa(ptr)
931
932#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
933#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
934#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
935
936#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
937#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
938#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
939#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
940
3dfcb315
AK		 941/*
942 * Find an entry in a page-table-directory. We combine the address region
943 * (the high order N bits) and the pgd portion of the address.
944 */
3dfcb315
AK		 945
946#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
947
368ced78
AK		 948#define pud_offset(pgdp, addr) \
949 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 950#define pmd_offset(pudp,addr) \
371352ca 951 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 952#define pte_offset_kernel(dir,addr) \
371352ca 953 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 954
955#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
956#define pte_unmap(pte) do { } while(0)
957
958/* to find an entry in a kernel page-table-directory */
959/* This now only contains the vmalloc pages */
960#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 961
962#define pte_ERROR(e) \
963 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
964#define pmd_ERROR(e) \
965 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 966#define pud_ERROR(e) \
967 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 968#define pgd_ERROR(e) \
969 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
970
31a14fae
AK		 971static inline int map_kernel_page(unsigned long ea, unsigned long pa,
972 unsigned long flags)
7207f436 973{
d9225ad9
AK		 974 if (radix_enabled()) {
975#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
976 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
977 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
978#endif
979 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
980 }
31a14fae 981 return hash__map_kernel_page(ea, pa, flags);
7207f436 982}
31a14fae
AK		 983
984static inline int __meminit vmemmap_create_mapping(unsigned long start,
985 unsigned long page_size,
986 unsigned long phys)
7207f436 987{
d9225ad9
AK		 988 if (radix_enabled())
989 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 990 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 991}
31a14fae
AK		 992
993#ifdef CONFIG_MEMORY_HOTPLUG
994static inline void vmemmap_remove_mapping(unsigned long start,
995 unsigned long page_size)
7207f436 996{
d9225ad9
AK		 997 if (radix_enabled())
998 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 999 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 1000}
31a14fae 1001#endif
3dfcb315
AK		 1002struct page *realmode_pfn_to_page(unsigned long pfn);
1003
3dfcb315
AK		 1004static inline pte_t pmd_pte(pmd_t pmd)
1005{
66c570f5 1006 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 1007}
1008
1009static inline pmd_t pte_pmd(pte_t pte)
1010{
66c570f5 1011 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 1012}
1013
1014static inline pte_t *pmdp_ptep(pmd_t *pmd)
1015{
1016 return (pte_t *)pmd;
1017}
3dfcb315
AK		 1018#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1019#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1020#define pmd_young(pmd) pte_young(pmd_pte(pmd))
1021#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1022#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1023#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 1024#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 1025#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1026#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
c137a275
AK		 1027#define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
1028#define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
7207f436
LD		 1029
1030#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1031#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1032#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1033#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1034#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1035
1ca72129
AK		 1036#ifdef CONFIG_NUMA_BALANCING
1037static inline int pmd_protnone(pmd_t pmd)
1038{
1039 return pte_protnone(pmd_pte(pmd));
1040}
1041#endif /* CONFIG_NUMA_BALANCING */
3dfcb315 1042
3dfcb315 1043#define pmd_write(pmd) pte_write(pmd_pte(pmd))
d19469e8 1044#define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
c137a275 1045#define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
3dfcb315 1046
f72a85e3
AK		 1047#define pmd_access_permitted pmd_access_permitted
1048static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1049{
1050 return pte_access_permitted(pmd_pte(pmd), write);
1051}
1052
6a1ea362
AK		 1053#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1054extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1055extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1056extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1057extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1058 pmd_t *pmdp, pmd_t pmd);
1059extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1060 pmd_t *pmd);
3df33f12
AK		 1061extern int hash__has_transparent_hugepage(void);
1062static inline int has_transparent_hugepage(void)
1063{
bde3eb62
AK		 1064 if (radix_enabled())
1065 return radix__has_transparent_hugepage();
3df33f12
AK		 1066 return hash__has_transparent_hugepage();
1067}
c04a5880 1068#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 1069
3df33f12
AK		 1070static inline unsigned long
1071pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1072 unsigned long clr, unsigned long set)
3dfcb315 1073{
bde3eb62
AK		 1074 if (radix_enabled())
1075 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 1076 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1077}
1078
1079static inline int pmd_large(pmd_t pmd)
1080{
66c570f5 1081 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 1082}
1083
1084static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1085{
1086 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1087}
1088/*
1089 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1090 * the below will work for radix too
1091 */
1092static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1093 unsigned long addr, pmd_t *pmdp)
1094{
1095 unsigned long old;
1096
66c570f5 1097 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 1098 return 0;
1099 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1100 return ((old & _PAGE_ACCESSED) != 0);
1101}
1102
1103#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1104static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1105 pmd_t *pmdp)
1106{
d19469e8 1107 if (__pmd_write((*pmdp)))
52c50ca7
AK		 1108 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1109 else if (unlikely(pmd_savedwrite(*pmdp)))
1110 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
3dfcb315
AK		 1111}
1112
ab624762
AK		 1113static inline int pmd_trans_huge(pmd_t pmd)
1114{
1115 if (radix_enabled())
1116 return radix__pmd_trans_huge(pmd);
1117 return hash__pmd_trans_huge(pmd);
1118}
1119
1120#define __HAVE_ARCH_PMD_SAME
1121static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1122{
1123 if (radix_enabled())
1124 return radix__pmd_same(pmd_a, pmd_b);
1125 return hash__pmd_same(pmd_a, pmd_b);
1126}
1127
3dfcb315
AK		 1128static inline pmd_t pmd_mkhuge(pmd_t pmd)
1129{
ab624762
AK		 1130 if (radix_enabled())
1131 return radix__pmd_mkhuge(pmd);
1132 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 1133}
1134
3dfcb315
AK		 1135#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1136extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1137 unsigned long address, pmd_t *pmdp,
1138 pmd_t entry, int dirty);
1139
3dfcb315
AK		 1140#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1141extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1142 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 1143
1144#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 1145static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1146 unsigned long addr, pmd_t *pmdp)
1147{
bde3eb62
AK		 1148 if (radix_enabled())
1149 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 1150 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1151}
3dfcb315 1152
3df33f12
AK		 1153static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1154 unsigned long address, pmd_t *pmdp)
1155{
bde3eb62
AK		 1156 if (radix_enabled())
1157 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 1158 return hash__pmdp_collapse_flush(vma, address, pmdp);
1159}
3dfcb315
AK		 1160#define pmdp_collapse_flush pmdp_collapse_flush
1161
1162#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 1163static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1164 pmd_t *pmdp, pgtable_t pgtable)
1165{
bde3eb62
AK		 1166 if (radix_enabled())
1167 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 1168 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1169}
1170
3dfcb315 1171#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 1172static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1173 pmd_t *pmdp)
1174{
bde3eb62
AK		 1175 if (radix_enabled())
1176 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 1177 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1178}
3dfcb315
AK		 1179
1180#define __HAVE_ARCH_PMDP_INVALIDATE
1181extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1182 pmd_t *pmdp);
1183
c777e2a8 1184#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
3df33f12
AK		 1185static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
1186 unsigned long address, pmd_t *pmdp)
1187{
bde3eb62
AK		 1188 if (radix_enabled())
1189 return radix__pmdp_huge_split_prepare(vma, address, pmdp);
3df33f12
AK		 1190 return hash__pmdp_huge_split_prepare(vma, address, pmdp);
1191}
c777e2a8 1192
3dfcb315
AK		 1193#define pmd_move_must_withdraw pmd_move_must_withdraw
1194struct spinlock;
1195static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1dd38b6c
AK		 1196 struct spinlock *old_pmd_ptl,
1197 struct vm_area_struct *vma)
3dfcb315 1198{
bde3eb62
AK		 1199 if (radix_enabled())
1200 return false;
3dfcb315
AK		 1201 /*
1202 * Archs like ppc64 use pgtable to store per pmd
1203 * specific information. So when we switch the pmd,
1204 * we should also withdraw and deposit the pgtable
1205 */
1206 return true;
1207}
953c66c2
AK		 1208
1209
1210#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1211static inline bool arch_needs_pgtable_deposit(void)
1212{
1213 if (radix_enabled())
1214 return false;
1215 return true;
1216}
fa4531f7 1217extern void serialize_against_pte_lookup(struct mm_struct *mm);
953c66c2 1218
ebd31197
OH		 1219
1220static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1221{
1222 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1223}
1224
1225static inline int pmd_devmap(pmd_t pmd)
1226{
1227 return pte_devmap(pmd_pte(pmd));
1228}
1229
1230static inline int pud_devmap(pud_t pud)
1231{
1232 return 0;
1233}
1234
1235static inline int pgd_devmap(pgd_t pgd)
1236{
1237 return 0;
1238}
6a1ea362 1239#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
ebd31197
OH		 1240
1241static inline const int pud_pfn(pud_t pud)
1242{
1243 /*
1244 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1245 * check so this should never be used. If it grows another user we
1246 * want to know about it.
1247 */
1248 BUILD_BUG();
1249 return 0;
1250}
029d9252 1251
3dfcb315
AK		 1252#endif /* __ASSEMBLY__ */
1253#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)