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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3dfcb315 AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 | 4 | |
2fb47060 | 5 | #include <asm-generic/pgtable-nop4d.h> |
9849a569 | 6 | |
c137a275 AK |
7 | #ifndef __ASSEMBLY__ |
8 | #include <linux/mmdebug.h> | |
ebd31197 | 9 | #include <linux/bug.h> |
9ccba66d | 10 | #include <linux/sizes.h> |
c137a275 | 11 | #endif |
9849a569 | 12 | |
2e873519 AK |
13 | /* |
14 | * Common bits between hash and Radix page table | |
15 | */ | |
2e873519 AK |
16 | |
17 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
18 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
19 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
2e873519 | 20 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ |
12564485 | 21 | #define _PAGE_SAO 0x00010 /* Strong access order */ |
2e873519 AK |
22 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ |
23 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
24 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
25 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 26 | /* |
2e873519 | 27 | * Software bits |
3dfcb315 | 28 | */ |
69dfbaeb AK |
29 | #define _RPAGE_SW0 0x2000000000000000UL |
30 | #define _RPAGE_SW1 0x00800 | |
31 | #define _RPAGE_SW2 0x00400 | |
32 | #define _RPAGE_SW3 0x00200 | |
ee8b3933 AK |
33 | #define _RPAGE_RSV1 0x00040UL |
34 | ||
35 | #define _RPAGE_PKEY_BIT4 0x1000000000000000UL | |
36 | #define _RPAGE_PKEY_BIT3 0x0800000000000000UL | |
37 | #define _RPAGE_PKEY_BIT2 0x0400000000000000UL | |
38 | #define _RPAGE_PKEY_BIT1 0x0200000000000000UL | |
39 | #define _RPAGE_PKEY_BIT0 0x0100000000000000UL | |
6aa59f51 AK |
40 | |
41 | #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ | |
42 | #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ | |
bd0dbb73 AK |
43 | /* |
44 | * We need to mark a pmd pte invalid while splitting. We can do that by clearing | |
45 | * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to | |
46 | * differentiate between two use a SW field when invalidating. | |
47 | * | |
48 | * We do that temporary invalidate for regular pte entry in ptep_set_access_flags | |
49 | * | |
50 | * This is used only when _PAGE_PRESENT is cleared. | |
51 | */ | |
52 | #define _PAGE_INVALID _RPAGE_SW0 | |
6aa59f51 AK |
53 | |
54 | /* | |
55 | * Top and bottom bits of RPN which can be used by hash | |
56 | * translation mode, because we expect them to be zero | |
57 | * otherwise. | |
58 | */ | |
32789d38 AK |
59 | #define _RPAGE_RPN0 0x01000 |
60 | #define _RPAGE_RPN1 0x02000 | |
6aa59f51 AK |
61 | #define _RPAGE_RPN43 0x0080000000000000UL |
62 | #define _RPAGE_RPN42 0x0040000000000000UL | |
63 | #define _RPAGE_RPN41 0x0020000000000000UL | |
049d567a | 64 | |
2f18d533 | 65 | /* Max physical address bit as per radix table */ |
ee8b3933 | 66 | #define _RPAGE_PA_MAX 56 |
2f18d533 AK |
67 | |
68 | /* | |
69 | * Max physical address bit we will use for now. | |
70 | * | |
71 | * This is mostly a hardware limitation and for now Power9 has | |
72 | * a 51 bit limit. | |
73 | * | |
74 | * This is different from the number of physical bit required to address | |
75 | * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. | |
76 | * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum | |
77 | * number of sections we can support (SECTIONS_SHIFT). | |
78 | * | |
79 | * This is different from Radix page table limitation above and | |
80 | * should always be less than that. The limit is done such that | |
81 | * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX | |
82 | * for hash linux page table specific bits. | |
83 | * | |
84 | * In order to be compatible with future hardware generations we keep | |
85 | * some offsets and limit this for now to 53 | |
86 | */ | |
87 | #define _PAGE_PA_MAX 53 | |
88 | ||
69dfbaeb | 89 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
69dfbaeb | 90 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
ebd31197 | 91 | #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ |
ebd31197 | 92 | |
2e873519 AK |
93 | /* |
94 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
95 | * Instead of fixing all of them, add an alternate define which | |
96 | * maps CI pte mapping. | |
97 | */ | |
98 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
99 | /* | |
2f18d533 AK |
100 | * We support _RPAGE_PA_MAX bit real address in pte. On the linux side |
101 | * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX | |
102 | * and every thing below PAGE_SHIFT; | |
2e873519 | 103 | */ |
2f18d533 | 104 | #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) |
9fee28ba | 105 | #define PTE_RPN_SHIFT PAGE_SHIFT |
2e873519 AK |
106 | /* |
107 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
108 | * in here, on radix we expect them to be zero. | |
109 | */ | |
110 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
111 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
4628a645 | 112 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
113 | /* |
114 | * user access blocked by key | |
115 | */ | |
116 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
117 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
56bec2f9 | 118 | #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) |
6cc07821 | 119 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) |
2e873519 AK |
120 | /* |
121 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
122 | * pgprot changes | |
123 | */ | |
124 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
125 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
4628a645 | 126 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
eb95d016 | 127 | |
3dfcb315 | 128 | /* |
2e873519 AK |
129 | * We define 2 sets of base prot bits, one for basic pages (ie, |
130 | * cacheable kernel and user pages) and one for non cacheable | |
131 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
132 | * the processor might need it for DMA coherency. | |
3dfcb315 | 133 | */ |
093d7ca2 | 134 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
2e873519 AK |
135 | #define _PAGE_BASE (_PAGE_BASE_NC) |
136 | ||
58f53462 CL |
137 | #include <asm/pgtable-masks.h> |
138 | ||
2e873519 AK |
139 | /* Permission masks used for kernel mappings */ |
140 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
6cc07821 CL |
141 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) |
142 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) | |
2e873519 AK |
143 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) |
144 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
145 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
146 | ||
dd1842a2 AK |
147 | #ifndef __ASSEMBLY__ |
148 | /* | |
149 | * page table defines | |
150 | */ | |
151 | extern unsigned long __pte_index_size; | |
152 | extern unsigned long __pmd_index_size; | |
153 | extern unsigned long __pud_index_size; | |
154 | extern unsigned long __pgd_index_size; | |
fae22116 | 155 | extern unsigned long __pud_cache_index; |
dd1842a2 AK |
156 | #define PTE_INDEX_SIZE __pte_index_size |
157 | #define PMD_INDEX_SIZE __pmd_index_size | |
158 | #define PUD_INDEX_SIZE __pud_index_size | |
159 | #define PGD_INDEX_SIZE __pgd_index_size | |
738f9645 AK |
160 | /* pmd table use page table fragments */ |
161 | #define PMD_CACHE_INDEX 0 | |
fae22116 | 162 | #define PUD_CACHE_INDEX __pud_cache_index |
dd1842a2 AK |
163 | /* |
164 | * Because of use of pte fragments and THP, size of page table | |
165 | * are not always derived out of index size above. | |
166 | */ | |
167 | extern unsigned long __pte_table_size; | |
168 | extern unsigned long __pmd_table_size; | |
169 | extern unsigned long __pud_table_size; | |
170 | extern unsigned long __pgd_table_size; | |
171 | #define PTE_TABLE_SIZE __pte_table_size | |
172 | #define PMD_TABLE_SIZE __pmd_table_size | |
173 | #define PUD_TABLE_SIZE __pud_table_size | |
174 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
175 | |
176 | extern unsigned long __pmd_val_bits; | |
177 | extern unsigned long __pud_val_bits; | |
178 | extern unsigned long __pgd_val_bits; | |
179 | #define PMD_VAL_BITS __pmd_val_bits | |
180 | #define PUD_VAL_BITS __pud_val_bits | |
181 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
182 | |
183 | extern unsigned long __pte_frag_nr; | |
184 | #define PTE_FRAG_NR __pte_frag_nr | |
185 | extern unsigned long __pte_frag_size_shift; | |
186 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
187 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 | 188 | |
8a6c697b AK |
189 | extern unsigned long __pmd_frag_nr; |
190 | #define PMD_FRAG_NR __pmd_frag_nr | |
191 | extern unsigned long __pmd_frag_size_shift; | |
192 | #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift | |
193 | #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) | |
194 | ||
dd1842a2 AK |
195 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) |
196 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
197 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
198 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
199 | ||
41b7a347 DA |
200 | #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) |
201 | #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) | |
202 | #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) | |
e72421a0 CL |
203 | #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ |
204 | H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) | |
205 | ||
dd1842a2 AK |
206 | /* PMD_SHIFT determines what a second-level page table entry can map */ |
207 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
208 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
209 | #define PMD_MASK (~(PMD_SIZE-1)) | |
210 | ||
211 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
212 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
213 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
214 | #define PUD_MASK (~(PUD_SIZE-1)) | |
215 | ||
216 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
217 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
218 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
219 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
220 | ||
221 | /* Bits to mask out from a PMD to get to the PTE page */ | |
222 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
223 | /* Bits to mask out from a PUD to get to the PMD page */ | |
224 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
225 | /* Bits to mask out from a PGD to get to the PUD page */ | |
2fb47060 | 226 | #define P4D_MASKED_BITS 0xc0000000000000ffUL |
d6a9996e | 227 | |
0c4d2680 AK |
228 | /* |
229 | * Used as an indicator for rcu callback functions | |
230 | */ | |
231 | enum pgtable_index { | |
232 | PTE_INDEX = 0, | |
233 | PMD_INDEX, | |
234 | PUD_INDEX, | |
235 | PGD_INDEX, | |
fadd03c6 AK |
236 | /* |
237 | * Below are used with 4k page size and hugetlb | |
238 | */ | |
239 | HTLB_16M_INDEX, | |
240 | HTLB_16G_INDEX, | |
0c4d2680 AK |
241 | }; |
242 | ||
d6a9996e AK |
243 | extern unsigned long __vmalloc_start; |
244 | extern unsigned long __vmalloc_end; | |
245 | #define VMALLOC_START __vmalloc_start | |
246 | #define VMALLOC_END __vmalloc_end | |
247 | ||
d909f910 NP |
248 | static inline unsigned int ioremap_max_order(void) |
249 | { | |
250 | if (radix_enabled()) | |
251 | return PUD_SHIFT; | |
252 | return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ | |
253 | } | |
254 | #define IOREMAP_MAX_ORDER ioremap_max_order() | |
255 | ||
d6a9996e | 256 | extern unsigned long __kernel_virt_start; |
63ee9b2f | 257 | extern unsigned long __kernel_io_start; |
a35a3c6f | 258 | extern unsigned long __kernel_io_end; |
d6a9996e | 259 | #define KERN_VIRT_START __kernel_virt_start |
63ee9b2f | 260 | #define KERN_IO_START __kernel_io_start |
a35a3c6f AK |
261 | #define KERN_IO_END __kernel_io_end |
262 | ||
d6a9996e | 263 | extern struct page *vmemmap; |
bfa37087 | 264 | extern unsigned long pci_io_base; |
dd1842a2 | 265 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 266 | |
ab537dca | 267 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 268 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 269 | |
b32d5d7e AK |
270 | #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS |
271 | #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS | |
272 | #else | |
273 | #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS | |
274 | #endif | |
275 | ||
276 | ||
a9252aae AK |
277 | #ifdef CONFIG_PPC_64K_PAGES |
278 | #include <asm/book3s/64/pgtable-64k.h> | |
279 | #else | |
280 | #include <asm/book3s/64/pgtable-4k.h> | |
281 | #endif | |
282 | ||
3dfcb315 | 283 | #include <asm/barrier.h> |
3dfcb315 | 284 | /* |
a35a3c6f | 285 | * IO space itself carved into the PIO region (ISA and PHB IO space) and |
3dfcb315 AK |
286 | * the ioremap space |
287 | * | |
288 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
289 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
290 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
291 | */ | |
3dfcb315 AK |
292 | #define FULL_IO_SIZE 0x80000000ul |
293 | #define ISA_IO_BASE (KERN_IO_START) | |
294 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
295 | #define PHB_IO_BASE (ISA_IO_END) | |
296 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
297 | #define IOREMAP_BASE (PHB_IO_END) | |
4a45b746 | 298 | #define IOREMAP_START (ioremap_bot) |
9ccba66d CL |
299 | #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) |
300 | #define FIXADDR_SIZE SZ_32M | |
d3e01796 | 301 | #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE) |
3dfcb315 | 302 | |
3dfcb315 AK |
303 | #ifndef __ASSEMBLY__ |
304 | ||
305 | /* | |
306 | * This is the default implementation of various PTE accessors, it's | |
307 | * used in all cases except Book3S with 64K pages where we have a | |
308 | * concept of sub-pages | |
309 | */ | |
310 | #ifndef __real_pte | |
311 | ||
ff31e105 | 312 | #define __real_pte(e, p, o) ((real_pte_t){(e)}) |
3dfcb315 | 313 | #define __rpte_to_pte(r) ((r).pte) |
945537df | 314 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
315 | |
316 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
317 | do { \ | |
318 | index = 0; \ | |
319 | shift = mmu_psize_defs[psize].shift; \ | |
320 | ||
321 | #define pte_iterate_hashed_end() } while(0) | |
322 | ||
323 | /* | |
324 | * We expect this to be called only for user addresses or kernel virtual | |
325 | * addresses other than the linear mapping. | |
326 | */ | |
327 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
328 | ||
329 | #endif /* __real_pte */ | |
330 | ||
ac94ac79 AK |
331 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
332 | pte_t *ptep, unsigned long clr, | |
333 | unsigned long set, int huge) | |
334 | { | |
335 | if (radix_enabled()) | |
336 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
337 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
338 | } | |
13f829a5 AK |
339 | /* |
340 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
341 | * We currently remove entries from the hashtable regardless of whether | |
342 | * the entry was young or dirty. | |
343 | * | |
344 | * We should be more intelligent about this but for the moment we override | |
345 | * these functions and force a tlb flush unconditionally | |
346 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
347 | * function for both hash and radix. | |
348 | */ | |
349 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
350 | unsigned long addr, pte_t *ptep) | |
351 | { | |
352 | unsigned long old; | |
353 | ||
66c570f5 | 354 | if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
13f829a5 AK |
355 | return 0; |
356 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
357 | return (old & _PAGE_ACCESSED) != 0; | |
358 | } | |
359 | ||
360 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
361 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
362 | ({ \ | |
3cb1aa7a | 363 | __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ |
13f829a5 AK |
364 | }) |
365 | ||
3cb1aa7a NP |
366 | /* |
367 | * On Book3S CPUs, clearing the accessed bit without a TLB flush | |
368 | * doesn't cause data corruption. [ It could cause incorrect | |
369 | * page aging and the (mistaken) reclaim of hot pages, but the | |
370 | * chance of that should be relatively low. ] | |
371 | * | |
372 | * So as a performance optimization don't flush the TLB when | |
373 | * clearing the accessed bit, it will eventually be flushed by | |
374 | * a context switch or a VM operation anyway. [ In the rare | |
375 | * event of it not getting flushed for a long time the delay | |
376 | * shouldn't really matter because there's no real memory | |
377 | * pressure for swapout to react to. ] | |
b11931e9 NP |
378 | * |
379 | * Note: this optimisation also exists in pte_needs_flush() and | |
380 | * huge_pmd_needs_flush(). | |
3cb1aa7a NP |
381 | */ |
382 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
383 | #define ptep_clear_flush_young ptep_test_and_clear_young | |
384 | ||
385 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
386 | #define pmdp_clear_flush_young pmdp_test_and_clear_young | |
387 | ||
d19469e8 AK |
388 | static inline int pte_write(pte_t pte) |
389 | { | |
d6379159 | 390 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); |
d19469e8 AK |
391 | } |
392 | ||
ca8afd40 CL |
393 | static inline int pte_read(pte_t pte) |
394 | { | |
395 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); | |
396 | } | |
397 | ||
13f829a5 AK |
398 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
399 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
400 | pte_t *ptep) | |
401 | { | |
d6379159 | 402 | if (pte_write(*ptep)) |
52c50ca7 | 403 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); |
13f829a5 AK |
404 | } |
405 | ||
8e581d43 | 406 | #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT |
13f829a5 AK |
407 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, |
408 | unsigned long addr, pte_t *ptep) | |
409 | { | |
d6379159 | 410 | if (pte_write(*ptep)) |
52c50ca7 | 411 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); |
13f829a5 AK |
412 | } |
413 | ||
414 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
415 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
416 | unsigned long addr, pte_t *ptep) | |
417 | { | |
418 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
419 | return __pte(old); | |
420 | } | |
421 | ||
f4894b80 AK |
422 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
423 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
424 | unsigned long addr, | |
425 | pte_t *ptep, int full) | |
426 | { | |
427 | if (full && radix_enabled()) { | |
428 | /* | |
2bf1071a NP |
429 | * We know that this is a full mm pte clear and |
430 | * hence can be sure there is no parallel set_pte. | |
f4894b80 AK |
431 | */ |
432 | return radix__ptep_get_and_clear_full(mm, addr, ptep, full); | |
433 | } | |
434 | return ptep_get_and_clear(mm, addr, ptep); | |
435 | } | |
436 | ||
437 | ||
13f829a5 AK |
438 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
439 | pte_t * ptep) | |
440 | { | |
441 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
442 | } | |
66c570f5 | 443 | |
66c570f5 AK |
444 | static inline int pte_dirty(pte_t pte) |
445 | { | |
446 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); | |
447 | } | |
448 | ||
449 | static inline int pte_young(pte_t pte) | |
450 | { | |
451 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); | |
452 | } | |
453 | ||
454 | static inline int pte_special(pte_t pte) | |
455 | { | |
456 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); | |
457 | } | |
458 | ||
daba7902 CL |
459 | static inline bool pte_exec(pte_t pte) |
460 | { | |
461 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); | |
462 | } | |
463 | ||
13f829a5 AK |
464 | |
465 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
466 | static inline bool pte_soft_dirty(pte_t pte) | |
467 | { | |
66c570f5 | 468 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 | 469 | } |
66c570f5 | 470 | |
13f829a5 AK |
471 | static inline pte_t pte_mksoft_dirty(pte_t pte) |
472 | { | |
1b2443a5 | 473 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
474 | } |
475 | ||
476 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
477 | { | |
1b2443a5 | 478 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
479 | } |
480 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
481 | ||
482 | #ifdef CONFIG_NUMA_BALANCING | |
13f829a5 AK |
483 | static inline int pte_protnone(pte_t pte) |
484 | { | |
c137a275 AK |
485 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == |
486 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
487 | } | |
13f829a5 AK |
488 | #endif /* CONFIG_NUMA_BALANCING */ |
489 | ||
ec4abf1e AK |
490 | static inline bool pte_hw_valid(pte_t pte) |
491 | { | |
492 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == | |
493 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
494 | } | |
495 | ||
13f829a5 AK |
496 | static inline int pte_present(pte_t pte) |
497 | { | |
bd0dbb73 AK |
498 | /* |
499 | * A pte is considerent present if _PAGE_PRESENT is set. | |
500 | * We also need to consider the pte present which is marked | |
501 | * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID | |
502 | * if we find _PAGE_PRESENT cleared. | |
503 | */ | |
f72a85e3 | 504 | |
ec4abf1e AK |
505 | if (pte_hw_valid(pte)) |
506 | return true; | |
507 | return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == | |
508 | cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); | |
daba7902 CL |
509 | } |
510 | ||
bca7aacf | 511 | #ifdef CONFIG_PPC_MEM_KEYS |
f2407ef3 | 512 | extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); |
bca7aacf RP |
513 | #else |
514 | static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) | |
515 | { | |
516 | return true; | |
517 | } | |
518 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
f2407ef3 | 519 | |
1b2443a5 CL |
520 | static inline bool pte_user(pte_t pte) |
521 | { | |
522 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); | |
523 | } | |
524 | ||
f72a85e3 AK |
525 | #define pte_access_permitted pte_access_permitted |
526 | static inline bool pte_access_permitted(pte_t pte, bool write) | |
527 | { | |
f72a85e3 | 528 | /* |
773b93f1 AKI |
529 | * _PAGE_READ is needed for any access and will be cleared for |
530 | * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false. | |
f72a85e3 | 531 | */ |
1b2443a5 | 532 | if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) |
f72a85e3 AK |
533 | return false; |
534 | ||
1b2443a5 | 535 | if (write && !pte_write(pte)) |
f72a85e3 | 536 | return false; |
bca7aacf RP |
537 | |
538 | return arch_pte_access_permitted(pte_val(pte), write, 0); | |
f72a85e3 AK |
539 | } |
540 | ||
13f829a5 AK |
541 | /* |
542 | * Conversion functions: convert a page and protection to a page entry, | |
543 | * and a page entry and page directory to the page they refer to. | |
544 | * | |
545 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
546 | * long for now. | |
547 | */ | |
548 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
549 | { | |
6bb25170 NP |
550 | VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); |
551 | VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); | |
552 | ||
379c926d | 553 | return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); |
13f829a5 AK |
554 | } |
555 | ||
13f829a5 AK |
556 | /* Generic modifiers for PTE bits */ |
557 | static inline pte_t pte_wrprotect(pte_t pte) | |
558 | { | |
1b2443a5 | 559 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
13f829a5 AK |
560 | } |
561 | ||
daba7902 CL |
562 | static inline pte_t pte_exprotect(pte_t pte) |
563 | { | |
1b2443a5 | 564 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); |
13f829a5 AK |
565 | } |
566 | ||
567 | static inline pte_t pte_mkclean(pte_t pte) | |
568 | { | |
1b2443a5 | 569 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); |
13f829a5 AK |
570 | } |
571 | ||
572 | static inline pte_t pte_mkold(pte_t pte) | |
573 | { | |
1b2443a5 | 574 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); |
13f829a5 AK |
575 | } |
576 | ||
daba7902 CL |
577 | static inline pte_t pte_mkexec(pte_t pte) |
578 | { | |
1b2443a5 | 579 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); |
daba7902 CL |
580 | } |
581 | ||
2f0584f3 | 582 | static inline pte_t pte_mkwrite_novma(pte_t pte) |
13f829a5 AK |
583 | { |
584 | /* | |
585 | * write implies read, hence set both | |
586 | */ | |
1b2443a5 | 587 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); |
13f829a5 AK |
588 | } |
589 | ||
590 | static inline pte_t pte_mkdirty(pte_t pte) | |
591 | { | |
1b2443a5 | 592 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); |
13f829a5 AK |
593 | } |
594 | ||
595 | static inline pte_t pte_mkyoung(pte_t pte) | |
596 | { | |
1b2443a5 | 597 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); |
13f829a5 AK |
598 | } |
599 | ||
600 | static inline pte_t pte_mkspecial(pte_t pte) | |
601 | { | |
1b2443a5 | 602 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); |
13f829a5 AK |
603 | } |
604 | ||
605 | static inline pte_t pte_mkhuge(pte_t pte) | |
606 | { | |
607 | return pte; | |
608 | } | |
609 | ||
ebd31197 OH |
610 | static inline pte_t pte_mkdevmap(pte_t pte) |
611 | { | |
1b2443a5 | 612 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); |
ebd31197 OH |
613 | } |
614 | ||
c9c98bc5 OH |
615 | /* |
616 | * This is potentially called with a pmd as the argument, in which case it's not | |
617 | * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. | |
618 | * That's because the bit we use for _PAGE_DEVMAP is not reserved for software | |
619 | * use in page directory entries (ie. non-ptes). | |
620 | */ | |
ebd31197 OH |
621 | static inline int pte_devmap(pte_t pte) |
622 | { | |
2b4a6cc9 | 623 | __be64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); |
c9c98bc5 OH |
624 | |
625 | return (pte_raw(pte) & mask) == mask; | |
ebd31197 OH |
626 | } |
627 | ||
13f829a5 AK |
628 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
629 | { | |
630 | /* FIXME!! check whether this need to be a conditional */ | |
1b2443a5 CL |
631 | return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | |
632 | cpu_to_be64(pgprot_val(newprot))); | |
34fbadd8 AK |
633 | } |
634 | ||
635 | /* Encode and de-code a swap entry */ | |
636 | #define MAX_SWAPFILES_CHECK() do { \ | |
637 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
638 | /* \ | |
639 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
640 | * We filter HPTEFLAGS on set_pte. \ | |
641 | */ \ | |
03ac1b71 | 642 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ |
34fbadd8 | 643 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ |
bff9beaa | 644 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ |
34fbadd8 | 645 | } while (0) |
3159f943 | 646 | |
34fbadd8 | 647 | #define SWP_TYPE_BITS 5 |
03ac1b71 DH |
648 | #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) |
649 | #define __swp_type(x) ((x).val & SWP_TYPE_MASK) | |
34fbadd8 AK |
650 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) |
651 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
03ac1b71 | 652 | (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) |
34fbadd8 AK |
653 | /* |
654 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
655 | * swap type and offset we get from swap and convert that to pte to find a | |
656 | * matching pte in linux page table. | |
657 | * Clear bits not found in swap entries here. | |
658 | */ | |
659 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
660 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
a0820ff3 AK |
661 | #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) |
662 | #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) | |
34fbadd8 AK |
663 | |
664 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
bff9beaa | 665 | #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY |
34fbadd8 AK |
666 | #else |
667 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
668 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
669 | ||
bff9beaa DH |
670 | #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT |
671 | ||
34fbadd8 AK |
672 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
673 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
674 | { | |
1b2443a5 | 675 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 676 | } |
66c570f5 | 677 | |
34fbadd8 AK |
678 | static inline bool pte_swp_soft_dirty(pte_t pte) |
679 | { | |
66c570f5 | 680 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 681 | } |
66c570f5 | 682 | |
34fbadd8 AK |
683 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) |
684 | { | |
1b2443a5 | 685 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 AK |
686 | } |
687 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
688 | ||
bff9beaa DH |
689 | static inline pte_t pte_swp_mkexclusive(pte_t pte) |
690 | { | |
691 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
692 | } | |
693 | ||
694 | static inline int pte_swp_exclusive(pte_t pte) | |
695 | { | |
696 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
697 | } | |
698 | ||
699 | static inline pte_t pte_swp_clear_exclusive(pte_t pte) | |
700 | { | |
701 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); | |
702 | } | |
703 | ||
34fbadd8 AK |
704 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) |
705 | { | |
706 | /* | |
707 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
708 | */ | |
709 | if (access & ~ptev) | |
710 | return false; | |
711 | /* | |
712 | * This check for access to privilege space | |
713 | */ | |
714 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
715 | return false; | |
716 | ||
717 | return true; | |
718 | } | |
ac94ac79 AK |
719 | /* |
720 | * Generic functions with hash/radix callbacks | |
721 | */ | |
722 | ||
e4c1112c | 723 | static inline void __ptep_set_access_flags(struct vm_area_struct *vma, |
b3603e17 | 724 | pte_t *ptep, pte_t entry, |
e4c1112c AK |
725 | unsigned long address, |
726 | int psize) | |
ac94ac79 AK |
727 | { |
728 | if (radix_enabled()) | |
e4c1112c AK |
729 | return radix__ptep_set_access_flags(vma, ptep, entry, |
730 | address, psize); | |
ac94ac79 AK |
731 | return hash__ptep_set_access_flags(ptep, entry); |
732 | } | |
733 | ||
734 | #define __HAVE_ARCH_PTE_SAME | |
735 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
736 | { | |
737 | if (radix_enabled()) | |
738 | return radix__pte_same(pte_a, pte_b); | |
739 | return hash__pte_same(pte_a, pte_b); | |
740 | } | |
741 | ||
742 | static inline int pte_none(pte_t pte) | |
743 | { | |
744 | if (radix_enabled()) | |
745 | return radix__pte_none(pte); | |
746 | return hash__pte_none(pte); | |
747 | } | |
748 | ||
749 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
750 | pte_t *ptep, pte_t pte, int percpu) | |
751 | { | |
379c926d AK |
752 | |
753 | VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); | |
754 | /* | |
755 | * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE | |
756 | * in all the callers. | |
757 | */ | |
758 | pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); | |
759 | ||
ac94ac79 AK |
760 | if (radix_enabled()) |
761 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
762 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
763 | } | |
34fbadd8 | 764 | |
12564485 SA |
765 | #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
766 | ||
13f829a5 AK |
767 | #define pgprot_noncached pgprot_noncached |
768 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
769 | { | |
770 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
771 | _PAGE_NON_IDEMPOTENT); | |
772 | } | |
773 | ||
774 | #define pgprot_noncached_wc pgprot_noncached_wc | |
775 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
776 | { | |
777 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
778 | _PAGE_TOLERANT); | |
779 | } | |
780 | ||
781 | #define pgprot_cached pgprot_cached | |
782 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
783 | { | |
784 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
785 | } | |
786 | ||
787 | #define pgprot_writecombine pgprot_writecombine | |
788 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
789 | { | |
790 | return pgprot_noncached_wc(prot); | |
791 | } | |
792 | /* | |
793 | * check a pte mapping have cache inhibited property | |
794 | */ | |
795 | static inline bool pte_ci(pte_t pte) | |
796 | { | |
1b2443a5 | 797 | __be64 pte_v = pte_raw(pte); |
13f829a5 | 798 | |
1b2443a5 CL |
799 | if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || |
800 | ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) | |
13f829a5 AK |
801 | return true; |
802 | return false; | |
803 | } | |
804 | ||
f281b5d5 AK |
805 | static inline void pmd_clear(pmd_t *pmdp) |
806 | { | |
392b4669 AK |
807 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
808 | /* | |
809 | * Don't use this if we can possibly have a hash page table | |
810 | * entry mapping this. | |
811 | */ | |
812 | WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
813 | } | |
f281b5d5 AK |
814 | *pmdp = __pmd(0); |
815 | } | |
816 | ||
66c570f5 AK |
817 | static inline int pmd_none(pmd_t pmd) |
818 | { | |
819 | return !pmd_raw(pmd); | |
820 | } | |
821 | ||
822 | static inline int pmd_present(pmd_t pmd) | |
823 | { | |
da7ad366 AK |
824 | /* |
825 | * A pmd is considerent present if _PAGE_PRESENT is set. | |
826 | * We also need to consider the pmd present which is marked | |
827 | * invalid during a split. Hence we look for _PAGE_INVALID | |
828 | * if we find _PAGE_PRESENT cleared. | |
829 | */ | |
830 | if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) | |
831 | return true; | |
66c570f5 | 832 | |
da7ad366 | 833 | return false; |
66c570f5 | 834 | } |
3dfcb315 | 835 | |
33258a1d NP |
836 | static inline int pmd_is_serializing(pmd_t pmd) |
837 | { | |
838 | /* | |
839 | * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear | |
840 | * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). | |
841 | * | |
842 | * This condition may also occur when flushing a pmd while flushing | |
843 | * it (see ptep_modify_prot_start), so callers must ensure this | |
844 | * case is fine as well. | |
845 | */ | |
846 | if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == | |
847 | cpu_to_be64(_PAGE_INVALID)) | |
848 | return true; | |
849 | ||
850 | return false; | |
851 | } | |
852 | ||
ac94ac79 AK |
853 | static inline int pmd_bad(pmd_t pmd) |
854 | { | |
855 | if (radix_enabled()) | |
856 | return radix__pmd_bad(pmd); | |
857 | return hash__pmd_bad(pmd); | |
858 | } | |
859 | ||
f281b5d5 AK |
860 | static inline void pud_clear(pud_t *pudp) |
861 | { | |
392b4669 AK |
862 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
863 | /* | |
864 | * Don't use this if we can possibly have a hash page table | |
865 | * entry mapping this. | |
866 | */ | |
867 | WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
868 | } | |
f281b5d5 AK |
869 | *pudp = __pud(0); |
870 | } | |
871 | ||
66c570f5 AK |
872 | static inline int pud_none(pud_t pud) |
873 | { | |
874 | return !pud_raw(pud); | |
875 | } | |
876 | ||
877 | static inline int pud_present(pud_t pud) | |
878 | { | |
a5800762 | 879 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 880 | } |
3dfcb315 AK |
881 | |
882 | extern struct page *pud_page(pud_t pud); | |
371352ca | 883 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
884 | static inline pte_t pud_pte(pud_t pud) |
885 | { | |
66c570f5 | 886 | return __pte_raw(pud_raw(pud)); |
3dfcb315 AK |
887 | } |
888 | ||
889 | static inline pud_t pte_pud(pte_t pte) | |
890 | { | |
66c570f5 | 891 | return __pud_raw(pte_raw(pte)); |
3dfcb315 | 892 | } |
27af67f3 AK |
893 | |
894 | static inline pte_t *pudp_ptep(pud_t *pud) | |
895 | { | |
896 | return (pte_t *)pud; | |
897 | } | |
898 | ||
899 | #define pud_pfn(pud) pte_pfn(pud_pte(pud)) | |
900 | #define pud_dirty(pud) pte_dirty(pud_pte(pud)) | |
901 | #define pud_young(pud) pte_young(pud_pte(pud)) | |
902 | #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud))) | |
903 | #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud))) | |
904 | #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud))) | |
905 | #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud))) | |
906 | #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) | |
f441ff73 | 907 | #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) |
3dfcb315 | 908 | #define pud_write(pud) pte_write(pud_pte(pud)) |
ac94ac79 | 909 | |
27af67f3 AK |
910 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
911 | #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud)) | |
912 | #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud))) | |
913 | #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud))) | |
914 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
915 | ||
ac94ac79 AK |
916 | static inline int pud_bad(pud_t pud) |
917 | { | |
918 | if (radix_enabled()) | |
919 | return radix__pud_bad(pud); | |
920 | return hash__pud_bad(pud); | |
921 | } | |
922 | ||
f72a85e3 AK |
923 | #define pud_access_permitted pud_access_permitted |
924 | static inline bool pud_access_permitted(pud_t pud, bool write) | |
925 | { | |
926 | return pte_access_permitted(pud_pte(pud), write); | |
927 | } | |
ac94ac79 | 928 | |
2fb47060 MR |
929 | #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) |
930 | static inline __be64 p4d_raw(p4d_t x) | |
931 | { | |
932 | return pgd_raw(x.pgd); | |
933 | } | |
934 | ||
935 | #define p4d_write(p4d) pte_write(p4d_pte(p4d)) | |
3dfcb315 | 936 | |
2fb47060 | 937 | static inline void p4d_clear(p4d_t *p4dp) |
368ced78 | 938 | { |
2fb47060 | 939 | *p4dp = __p4d(0); |
368ced78 AK |
940 | } |
941 | ||
2fb47060 | 942 | static inline int p4d_none(p4d_t p4d) |
66c570f5 | 943 | { |
2fb47060 | 944 | return !p4d_raw(p4d); |
66c570f5 AK |
945 | } |
946 | ||
2fb47060 | 947 | static inline int p4d_present(p4d_t p4d) |
66c570f5 | 948 | { |
2fb47060 | 949 | return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 950 | } |
368ced78 | 951 | |
2fb47060 | 952 | static inline pte_t p4d_pte(p4d_t p4d) |
368ced78 | 953 | { |
2fb47060 | 954 | return __pte_raw(p4d_raw(p4d)); |
368ced78 AK |
955 | } |
956 | ||
2fb47060 | 957 | static inline p4d_t pte_p4d(pte_t pte) |
368ced78 | 958 | { |
2fb47060 | 959 | return __p4d_raw(pte_raw(pte)); |
368ced78 AK |
960 | } |
961 | ||
2fb47060 | 962 | static inline int p4d_bad(p4d_t p4d) |
ac94ac79 AK |
963 | { |
964 | if (radix_enabled()) | |
2fb47060 MR |
965 | return radix__p4d_bad(p4d); |
966 | return hash__p4d_bad(p4d); | |
ac94ac79 AK |
967 | } |
968 | ||
2fb47060 MR |
969 | #define p4d_access_permitted p4d_access_permitted |
970 | static inline bool p4d_access_permitted(p4d_t p4d, bool write) | |
f72a85e3 | 971 | { |
2fb47060 | 972 | return pte_access_permitted(p4d_pte(p4d), write); |
f72a85e3 AK |
973 | } |
974 | ||
2fb47060 | 975 | extern struct page *p4d_page(p4d_t p4d); |
368ced78 | 976 | |
aba480e1 AK |
977 | /* Pointers in the page table tree are physical addresses */ |
978 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
979 | ||
dc4875f0 AK |
980 | static inline pud_t *p4d_pgtable(p4d_t p4d) |
981 | { | |
982 | return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); | |
983 | } | |
aba480e1 | 984 | |
9cf6fa24 AK |
985 | static inline pmd_t *pud_pgtable(pud_t pud) |
986 | { | |
987 | return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); | |
988 | } | |
989 | ||
3dfcb315 AK |
990 | #define pmd_ERROR(e) \ |
991 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
992 | #define pud_ERROR(e) \ |
993 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
994 | #define pgd_ERROR(e) \ |
995 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
996 | ||
c766ee72 | 997 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) |
7207f436 | 998 | { |
d9225ad9 AK |
999 | if (radix_enabled()) { |
1000 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
1001 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
1002 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
1003 | #endif | |
c766ee72 | 1004 | return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); |
d9225ad9 | 1005 | } |
c766ee72 | 1006 | return hash__map_kernel_page(ea, pa, prot); |
7207f436 | 1007 | } |
31a14fae | 1008 | |
aec98260 CL |
1009 | void unmap_kernel_page(unsigned long va); |
1010 | ||
31a14fae AK |
1011 | static inline int __meminit vmemmap_create_mapping(unsigned long start, |
1012 | unsigned long page_size, | |
1013 | unsigned long phys) | |
7207f436 | 1014 | { |
d9225ad9 AK |
1015 | if (radix_enabled()) |
1016 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 1017 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 1018 | } |
31a14fae AK |
1019 | |
1020 | #ifdef CONFIG_MEMORY_HOTPLUG | |
1021 | static inline void vmemmap_remove_mapping(unsigned long start, | |
1022 | unsigned long page_size) | |
7207f436 | 1023 | { |
d9225ad9 AK |
1024 | if (radix_enabled()) |
1025 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 1026 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 1027 | } |
31a14fae | 1028 | #endif |
3dfcb315 | 1029 | |
a5edf981 | 1030 | #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) |
4f703e7f JS |
1031 | static inline void __kernel_map_pages(struct page *page, int numpages, int enable) |
1032 | { | |
1033 | if (radix_enabled()) | |
1034 | radix__kernel_map_pages(page, numpages, enable); | |
1035 | else | |
1036 | hash__kernel_map_pages(page, numpages, enable); | |
1037 | } | |
1038 | #endif | |
1039 | ||
3dfcb315 AK |
1040 | static inline pte_t pmd_pte(pmd_t pmd) |
1041 | { | |
66c570f5 | 1042 | return __pte_raw(pmd_raw(pmd)); |
3dfcb315 AK |
1043 | } |
1044 | ||
1045 | static inline pmd_t pte_pmd(pte_t pte) | |
1046 | { | |
66c570f5 | 1047 | return __pmd_raw(pte_raw(pte)); |
3dfcb315 AK |
1048 | } |
1049 | ||
1050 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
1051 | { | |
1052 | return (pte_t *)pmd; | |
1053 | } | |
3dfcb315 AK |
1054 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
1055 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
1056 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
1057 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
1058 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
1059 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 1060 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 | 1061 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
2f0584f3 | 1062 | #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) |
7207f436 LD |
1063 | |
1064 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
1065 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
1066 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
1067 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
a0820ff3 AK |
1068 | |
1069 | #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION | |
1070 | #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) | |
1071 | #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) | |
1072 | #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) | |
1073 | #endif | |
7207f436 LD |
1074 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ |
1075 | ||
1ca72129 AK |
1076 | #ifdef CONFIG_NUMA_BALANCING |
1077 | static inline int pmd_protnone(pmd_t pmd) | |
1078 | { | |
1079 | return pte_protnone(pmd_pte(pmd)); | |
1080 | } | |
1081 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 | 1082 | |
3dfcb315 AK |
1083 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
1084 | ||
f72a85e3 AK |
1085 | #define pmd_access_permitted pmd_access_permitted |
1086 | static inline bool pmd_access_permitted(pmd_t pmd, bool write) | |
1087 | { | |
33258a1d NP |
1088 | /* |
1089 | * pmdp_invalidate sets this combination (which is not caught by | |
1090 | * !pte_present() check in pte_access_permitted), to prevent | |
1091 | * lock-free lookups, as part of the serialize_against_pte_lookup() | |
1092 | * synchronisation. | |
1093 | * | |
1094 | * This also catches the case where the PTE's hardware PRESENT bit is | |
1095 | * cleared while TLB is flushed, which is suboptimal but should not | |
1096 | * be frequent. | |
1097 | */ | |
1098 | if (pmd_is_serializing(pmd)) | |
1099 | return false; | |
1100 | ||
f72a85e3 AK |
1101 | return pte_access_permitted(pmd_pte(pmd), write); |
1102 | } | |
1103 | ||
6a1ea362 AK |
1104 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1105 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
27af67f3 | 1106 | extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot); |
6a1ea362 AK |
1107 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); |
1108 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
1109 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1110 | pmd_t *pmdp, pmd_t pmd); | |
27af67f3 AK |
1111 | extern void set_pud_at(struct mm_struct *mm, unsigned long addr, |
1112 | pud_t *pudp, pud_t pud); | |
1113 | ||
18594f9b NP |
1114 | static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, |
1115 | unsigned long addr, pmd_t *pmd) | |
1116 | { | |
1117 | } | |
1118 | ||
27af67f3 AK |
1119 | static inline void update_mmu_cache_pud(struct vm_area_struct *vma, |
1120 | unsigned long addr, pud_t *pud) | |
1121 | { | |
1122 | } | |
1123 | ||
3df33f12 AK |
1124 | extern int hash__has_transparent_hugepage(void); |
1125 | static inline int has_transparent_hugepage(void) | |
1126 | { | |
bde3eb62 AK |
1127 | if (radix_enabled()) |
1128 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
1129 | return hash__has_transparent_hugepage(); |
1130 | } | |
c04a5880 | 1131 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 1132 | |
27af67f3 AK |
1133 | static inline int has_transparent_pud_hugepage(void) |
1134 | { | |
1135 | if (radix_enabled()) | |
1136 | return radix__has_transparent_pud_hugepage(); | |
1137 | return 0; | |
1138 | } | |
1139 | #define has_transparent_pud_hugepage has_transparent_pud_hugepage | |
1140 | ||
3df33f12 AK |
1141 | static inline unsigned long |
1142 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
1143 | unsigned long clr, unsigned long set) | |
3dfcb315 | 1144 | { |
bde3eb62 AK |
1145 | if (radix_enabled()) |
1146 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
1147 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
1148 | } | |
1149 | ||
27af67f3 AK |
1150 | static inline unsigned long |
1151 | pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp, | |
1152 | unsigned long clr, unsigned long set) | |
1153 | { | |
1154 | if (radix_enabled()) | |
1155 | return radix__pud_hugepage_update(mm, addr, pudp, clr, set); | |
1156 | BUG(); | |
1157 | return pud_val(*pudp); | |
1158 | } | |
1159 | ||
3df33f12 AK |
1160 | /* |
1161 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
1162 | * the below will work for radix too | |
1163 | */ | |
1164 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
1165 | unsigned long addr, pmd_t *pmdp) | |
1166 | { | |
1167 | unsigned long old; | |
1168 | ||
66c570f5 | 1169 | if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
3df33f12 AK |
1170 | return 0; |
1171 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
1172 | return ((old & _PAGE_ACCESSED) != 0); | |
1173 | } | |
1174 | ||
27af67f3 AK |
1175 | static inline int __pudp_test_and_clear_young(struct mm_struct *mm, |
1176 | unsigned long addr, pud_t *pudp) | |
1177 | { | |
1178 | unsigned long old; | |
1179 | ||
1180 | if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
1181 | return 0; | |
1182 | old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0); | |
1183 | return ((old & _PAGE_ACCESSED) != 0); | |
1184 | } | |
1185 | ||
3df33f12 AK |
1186 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1187 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1188 | pmd_t *pmdp) | |
1189 | { | |
d6379159 | 1190 | if (pmd_write(*pmdp)) |
52c50ca7 | 1191 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); |
3dfcb315 AK |
1192 | } |
1193 | ||
27af67f3 AK |
1194 | #define __HAVE_ARCH_PUDP_SET_WRPROTECT |
1195 | static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1196 | pud_t *pudp) | |
1197 | { | |
1198 | if (pud_write(*pudp)) | |
1199 | pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0); | |
1200 | } | |
1201 | ||
8890e033 AK |
1202 | /* |
1203 | * Only returns true for a THP. False for pmd migration entry. | |
1204 | * We also need to return true when we come across a pte that | |
1205 | * in between a thp split. While splitting THP, we mark the pmd | |
1206 | * invalid (pmdp_invalidate()) before we set it with pte page | |
1207 | * address. A pmd_trans_huge() check against a pmd entry during that time | |
1208 | * should return true. | |
1209 | * We should not call this on a hugetlb entry. We should check for HugeTLB | |
1210 | * entry using vma->vm_flags | |
ee65728e | 1211 | * The page table walk rule is explained in Documentation/mm/transhuge.rst |
8890e033 | 1212 | */ |
ab624762 AK |
1213 | static inline int pmd_trans_huge(pmd_t pmd) |
1214 | { | |
8890e033 AK |
1215 | if (!pmd_present(pmd)) |
1216 | return false; | |
1217 | ||
ab624762 AK |
1218 | if (radix_enabled()) |
1219 | return radix__pmd_trans_huge(pmd); | |
1220 | return hash__pmd_trans_huge(pmd); | |
1221 | } | |
1222 | ||
27af67f3 AK |
1223 | static inline int pud_trans_huge(pud_t pud) |
1224 | { | |
1225 | if (!pud_present(pud)) | |
1226 | return false; | |
1227 | ||
1228 | if (radix_enabled()) | |
1229 | return radix__pud_trans_huge(pud); | |
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | ||
ab624762 AK |
1234 | #define __HAVE_ARCH_PMD_SAME |
1235 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
1236 | { | |
1237 | if (radix_enabled()) | |
1238 | return radix__pmd_same(pmd_a, pmd_b); | |
1239 | return hash__pmd_same(pmd_a, pmd_b); | |
1240 | } | |
1241 | ||
27af67f3 AK |
1242 | #define pud_same pud_same |
1243 | static inline int pud_same(pud_t pud_a, pud_t pud_b) | |
1244 | { | |
1245 | if (radix_enabled()) | |
1246 | return radix__pud_same(pud_a, pud_b); | |
1247 | return hash__pud_same(pud_a, pud_b); | |
1248 | } | |
1249 | ||
1250 | ||
53f45ecc | 1251 | static inline pmd_t __pmd_mkhuge(pmd_t pmd) |
3dfcb315 | 1252 | { |
ab624762 AK |
1253 | if (radix_enabled()) |
1254 | return radix__pmd_mkhuge(pmd); | |
1255 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
1256 | } |
1257 | ||
27af67f3 AK |
1258 | static inline pud_t __pud_mkhuge(pud_t pud) |
1259 | { | |
1260 | if (radix_enabled()) | |
1261 | return radix__pud_mkhuge(pud); | |
1262 | BUG(); | |
1263 | return pud; | |
1264 | } | |
1265 | ||
53f45ecc AK |
1266 | /* |
1267 | * pfn_pmd return a pmd_t that can be used as pmd pte entry. | |
1268 | */ | |
1269 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1270 | { | |
1271 | #ifdef CONFIG_DEBUG_VM | |
1272 | if (radix_enabled()) | |
1273 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1274 | else | |
1275 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != | |
1276 | cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); | |
1277 | #endif | |
1278 | return pmd; | |
1279 | } | |
1280 | ||
27af67f3 AK |
1281 | static inline pud_t pud_mkhuge(pud_t pud) |
1282 | { | |
1283 | #ifdef CONFIG_DEBUG_VM | |
1284 | if (radix_enabled()) | |
1285 | WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1286 | else | |
1287 | WARN_ON(1); | |
1288 | #endif | |
1289 | return pud; | |
1290 | } | |
1291 | ||
1292 | ||
3dfcb315 AK |
1293 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1294 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1295 | unsigned long address, pmd_t *pmdp, | |
1296 | pmd_t entry, int dirty); | |
27af67f3 AK |
1297 | #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS |
1298 | extern int pudp_set_access_flags(struct vm_area_struct *vma, | |
1299 | unsigned long address, pud_t *pudp, | |
1300 | pud_t entry, int dirty); | |
3dfcb315 | 1301 | |
3dfcb315 AK |
1302 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1303 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1304 | unsigned long address, pmd_t *pmdp); | |
27af67f3 AK |
1305 | #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG |
1306 | extern int pudp_test_and_clear_young(struct vm_area_struct *vma, | |
1307 | unsigned long address, pud_t *pudp); | |
1308 | ||
3dfcb315 AK |
1309 | |
1310 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
1311 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
1312 | unsigned long addr, pmd_t *pmdp) | |
1313 | { | |
bde3eb62 AK |
1314 | if (radix_enabled()) |
1315 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
1316 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
1317 | } | |
3dfcb315 | 1318 | |
27af67f3 AK |
1319 | #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR |
1320 | static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, | |
1321 | unsigned long addr, pud_t *pudp) | |
1322 | { | |
1323 | if (radix_enabled()) | |
1324 | return radix__pudp_huge_get_and_clear(mm, addr, pudp); | |
1325 | BUG(); | |
1326 | return *pudp; | |
1327 | } | |
1328 | ||
3df33f12 AK |
1329 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1330 | unsigned long address, pmd_t *pmdp) | |
1331 | { | |
bde3eb62 AK |
1332 | if (radix_enabled()) |
1333 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
1334 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
1335 | } | |
3dfcb315 AK |
1336 | #define pmdp_collapse_flush pmdp_collapse_flush |
1337 | ||
75358ea3 AK |
1338 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1339 | pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1340 | unsigned long addr, | |
1341 | pmd_t *pmdp, int full); | |
1342 | ||
27af67f3 AK |
1343 | #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL |
1344 | pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1345 | unsigned long addr, | |
1346 | pud_t *pudp, int full); | |
1347 | ||
3dfcb315 | 1348 | #define __HAVE_ARCH_PGTABLE_DEPOSIT |
3df33f12 AK |
1349 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
1350 | pmd_t *pmdp, pgtable_t pgtable) | |
1351 | { | |
bde3eb62 AK |
1352 | if (radix_enabled()) |
1353 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
1354 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
1355 | } | |
1356 | ||
3dfcb315 | 1357 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
1358 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
1359 | pmd_t *pmdp) | |
1360 | { | |
bde3eb62 AK |
1361 | if (radix_enabled()) |
1362 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
1363 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
1364 | } | |
3dfcb315 AK |
1365 | |
1366 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
8cc931e0 AK |
1367 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, |
1368 | pmd_t *pmdp); | |
3dfcb315 AK |
1369 | |
1370 | #define pmd_move_must_withdraw pmd_move_must_withdraw | |
1371 | struct spinlock; | |
579b9239 AK |
1372 | extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, |
1373 | struct spinlock *old_pmd_ptl, | |
1374 | struct vm_area_struct *vma); | |
1375 | /* | |
1376 | * Hash translation mode use the deposited table to store hash pte | |
1377 | * slot information. | |
1378 | */ | |
953c66c2 AK |
1379 | #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit |
1380 | static inline bool arch_needs_pgtable_deposit(void) | |
1381 | { | |
1382 | if (radix_enabled()) | |
1383 | return false; | |
1384 | return true; | |
1385 | } | |
fa4531f7 | 1386 | extern void serialize_against_pte_lookup(struct mm_struct *mm); |
953c66c2 | 1387 | |
ebd31197 OH |
1388 | |
1389 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) | |
1390 | { | |
36b78402 AK |
1391 | if (radix_enabled()) |
1392 | return radix__pmd_mkdevmap(pmd); | |
1393 | return hash__pmd_mkdevmap(pmd); | |
ebd31197 OH |
1394 | } |
1395 | ||
27af67f3 AK |
1396 | static inline pud_t pud_mkdevmap(pud_t pud) |
1397 | { | |
1398 | if (radix_enabled()) | |
1399 | return radix__pud_mkdevmap(pud); | |
1400 | BUG(); | |
1401 | return pud; | |
1402 | } | |
1403 | ||
ebd31197 OH |
1404 | static inline int pmd_devmap(pmd_t pmd) |
1405 | { | |
1406 | return pte_devmap(pmd_pte(pmd)); | |
1407 | } | |
1408 | ||
1409 | static inline int pud_devmap(pud_t pud) | |
1410 | { | |
27af67f3 | 1411 | return pte_devmap(pud_pte(pud)); |
ebd31197 OH |
1412 | } |
1413 | ||
1414 | static inline int pgd_devmap(pgd_t pgd) | |
1415 | { | |
1416 | return 0; | |
1417 | } | |
6a1ea362 | 1418 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
ebd31197 | 1419 | |
5b323367 AK |
1420 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1421 | pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); | |
1422 | void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, | |
1423 | pte_t *, pte_t, pte_t); | |
1424 | ||
1425 | /* | |
1426 | * Returns true for a R -> RW upgrade of pte | |
1427 | */ | |
1428 | static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) | |
1429 | { | |
1430 | if (!(old_val & _PAGE_READ)) | |
1431 | return false; | |
1432 | ||
1433 | if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) | |
1434 | return true; | |
1435 | ||
1436 | return false; | |
1437 | } | |
029d9252 | 1438 | |
d6eacedd | 1439 | /* |
e72c7c2b | 1440 | * Like pmd_huge(), but works regardless of config options |
d6eacedd | 1441 | */ |
bd18b688 | 1442 | #define pmd_leaf pmd_leaf |
bd18b688 | 1443 | static inline bool pmd_leaf(pmd_t pmd) |
d6eacedd AK |
1444 | { |
1445 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); | |
1446 | } | |
1447 | ||
bd18b688 | 1448 | #define pud_leaf pud_leaf |
bd18b688 | 1449 | static inline bool pud_leaf(pud_t pud) |
d6eacedd AK |
1450 | { |
1451 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); | |
1452 | } | |
1453 | ||
3dfcb315 AK |
1454 | #endif /* __ASSEMBLY__ */ |
1455 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |