projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
powerpc: Untangle fixmap.h and pgtable.h and mmu.h
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
3dfcb315
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519 4
2fb47060 5#include <asm-generic/pgtable-nop4d.h>
9849a569 6
c137a275
AK		 7#ifndef __ASSEMBLY__
8#include <linux/mmdebug.h>
ebd31197 9#include <linux/bug.h>
9ccba66d 10#include <linux/sizes.h>
c137a275 11#endif
9849a569 12
2e873519
AK		 13/*
14 * Common bits between hash and Radix page table
15 */
2e873519
AK		 16
17#define _PAGE_EXEC 0x00001 /* execute permission */
18#define _PAGE_WRITE 0x00002 /* write access allowed */
19#define _PAGE_READ 0x00004 /* read access allowed */
20#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
21#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
22#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
12564485 23#define _PAGE_SAO 0x00010 /* Strong access order */
2e873519
AK		 24#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
25#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
26#define _PAGE_DIRTY 0x00080 /* C: page changed */
27#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 28/*
2e873519 29 * Software bits
3dfcb315 30 */
69dfbaeb
AK		 31#define _RPAGE_SW0 0x2000000000000000UL
32#define _RPAGE_SW1 0x00800
33#define _RPAGE_SW2 0x00400
34#define _RPAGE_SW3 0x00200
ee8b3933
AK		 35#define _RPAGE_RSV1 0x00040UL
36
37#define _RPAGE_PKEY_BIT4 0x1000000000000000UL
38#define _RPAGE_PKEY_BIT3 0x0800000000000000UL
39#define _RPAGE_PKEY_BIT2 0x0400000000000000UL
40#define _RPAGE_PKEY_BIT1 0x0200000000000000UL
41#define _RPAGE_PKEY_BIT0 0x0100000000000000UL
6aa59f51
AK		 42
43#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
44#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
bd0dbb73
AK		 45/*
46 * We need to mark a pmd pte invalid while splitting. We can do that by clearing
47 * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to
48 * differentiate between two use a SW field when invalidating.
49 *
50 * We do that temporary invalidate for regular pte entry in ptep_set_access_flags
51 *
52 * This is used only when _PAGE_PRESENT is cleared.
53 */
54#define _PAGE_INVALID _RPAGE_SW0
6aa59f51
AK		 55
56/*
57 * Top and bottom bits of RPN which can be used by hash
58 * translation mode, because we expect them to be zero
59 * otherwise.
60 */
32789d38
AK		 61#define _RPAGE_RPN0 0x01000
62#define _RPAGE_RPN1 0x02000
6aa59f51
AK		 63#define _RPAGE_RPN43 0x0080000000000000UL
64#define _RPAGE_RPN42 0x0040000000000000UL
65#define _RPAGE_RPN41 0x0020000000000000UL
049d567a 66
2f18d533 67/* Max physical address bit as per radix table */
ee8b3933 68#define _RPAGE_PA_MAX 56
2f18d533
AK		 69
70/*
71 * Max physical address bit we will use for now.
72 *
73 * This is mostly a hardware limitation and for now Power9 has
74 * a 51 bit limit.
75 *
76 * This is different from the number of physical bit required to address
77 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
78 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
79 * number of sections we can support (SECTIONS_SHIFT).
80 *
81 * This is different from Radix page table limitation above and
82 * should always be less than that. The limit is done such that
83 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
84 * for hash linux page table specific bits.
85 *
86 * In order to be compatible with future hardware generations we keep
87 * some offsets and limit this for now to 53
88 */
89#define _PAGE_PA_MAX 53
90
69dfbaeb 91#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
69dfbaeb 92#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
ebd31197 93#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
ebd31197 94
2e873519
AK		 95/*
96 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
97 * Instead of fixing all of them, add an alternate define which
98 * maps CI pte mapping.
99 */
100#define _PAGE_NO_CACHE _PAGE_TOLERANT
101/*
2f18d533
AK		 102 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
103 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
104 * and every thing below PAGE_SHIFT;
2e873519 105 */
2f18d533 106#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
9fee28ba 107#define PTE_RPN_SHIFT PAGE_SHIFT
2e873519
AK		 108/*
109 * set of bits not changed in pmd_modify. Even though we have hash specific bits
110 * in here, on radix we expect them to be zero.
111 */
112#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
113 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
4628a645 114 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP)
2e873519
AK		 115/*
116 * user access blocked by key
117 */
118#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
119#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
56bec2f9 120#define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC)
6cc07821 121#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
2e873519
AK		 122/*
123 * _PAGE_CHG_MASK masks of bits that are to be preserved across
124 * pgprot changes
125 */
126#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
127 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
4628a645 128 _PAGE_SOFT_DIRTY | _PAGE_DEVMAP)
eb95d016 129
3dfcb315 130/*
2e873519
AK		 131 * We define 2 sets of base prot bits, one for basic pages (ie,
132 * cacheable kernel and user pages) and one for non cacheable
133 * pages. We always set _PAGE_COHERENT when SMP is enabled or
134 * the processor might need it for DMA coherency.
3dfcb315 135 */
093d7ca2 136#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
2e873519
AK		 137#define _PAGE_BASE (_PAGE_BASE_NC)
138
139/* Permission masks used to generate the __P and __S table,
140 *
141 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
142 *
143 * Write permissions imply read permissions for now (we could make write-only
144 * pages on BookE but we don't bother for now). Execute permission control is
145 * possible on platforms that define _PAGE_EXEC
2e873519
AK		 146 */
147#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
148#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
149#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
150#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
151#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
152#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
153#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
395cac77
RC		 154/* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */
155#define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC)
2e873519 156
2e873519
AK		 157/* Permission masks used for kernel mappings */
158#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
6cc07821
CL		 159#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT)
160#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT)
2e873519
AK		 161#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
162#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
163#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
164
dd1842a2
AK		 165#ifndef __ASSEMBLY__
166/*
167 * page table defines
168 */
169extern unsigned long __pte_index_size;
170extern unsigned long __pmd_index_size;
171extern unsigned long __pud_index_size;
172extern unsigned long __pgd_index_size;
fae22116 173extern unsigned long __pud_cache_index;
dd1842a2
AK		 174#define PTE_INDEX_SIZE __pte_index_size
175#define PMD_INDEX_SIZE __pmd_index_size
176#define PUD_INDEX_SIZE __pud_index_size
177#define PGD_INDEX_SIZE __pgd_index_size
738f9645
AK		 178/* pmd table use page table fragments */
179#define PMD_CACHE_INDEX 0
fae22116 180#define PUD_CACHE_INDEX __pud_cache_index
dd1842a2
AK		 181/*
182 * Because of use of pte fragments and THP, size of page table
183 * are not always derived out of index size above.
184 */
185extern unsigned long __pte_table_size;
186extern unsigned long __pmd_table_size;
187extern unsigned long __pud_table_size;
188extern unsigned long __pgd_table_size;
189#define PTE_TABLE_SIZE __pte_table_size
190#define PMD_TABLE_SIZE __pmd_table_size
191#define PUD_TABLE_SIZE __pud_table_size
192#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 193
194extern unsigned long __pmd_val_bits;
195extern unsigned long __pud_val_bits;
196extern unsigned long __pgd_val_bits;
197#define PMD_VAL_BITS __pmd_val_bits
198#define PUD_VAL_BITS __pud_val_bits
199#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 200
201extern unsigned long __pte_frag_nr;
202#define PTE_FRAG_NR __pte_frag_nr
203extern unsigned long __pte_frag_size_shift;
204#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
205#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2 206
8a6c697b
AK		 207extern unsigned long __pmd_frag_nr;
208#define PMD_FRAG_NR __pmd_frag_nr
209extern unsigned long __pmd_frag_size_shift;
210#define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
211#define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
212
dd1842a2
AK		 213#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
214#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
215#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
216#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
217
41b7a347
DA		 218#define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE)
219#define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD)
220#define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD)
e72421a0
CL		 221#define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \
222 H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE))
223
dd1842a2
AK		 224/* PMD_SHIFT determines what a second-level page table entry can map */
225#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
226#define PMD_SIZE (1UL << PMD_SHIFT)
227#define PMD_MASK (~(PMD_SIZE-1))
228
229/* PUD_SHIFT determines what a third-level page table entry can map */
230#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
231#define PUD_SIZE (1UL << PUD_SHIFT)
232#define PUD_MASK (~(PUD_SIZE-1))
233
234/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
235#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
236#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
237#define PGDIR_MASK (~(PGDIR_SIZE-1))
238
239/* Bits to mask out from a PMD to get to the PTE page */
240#define PMD_MASKED_BITS 0xc0000000000000ffUL
241/* Bits to mask out from a PUD to get to the PMD page */
242#define PUD_MASKED_BITS 0xc0000000000000ffUL
243/* Bits to mask out from a PGD to get to the PUD page */
2fb47060 244#define P4D_MASKED_BITS 0xc0000000000000ffUL
d6a9996e 245
0c4d2680
AK		 246/*
247 * Used as an indicator for rcu callback functions
248 */
249enum pgtable_index {
250 PTE_INDEX = 0,
251 PMD_INDEX,
252 PUD_INDEX,
253 PGD_INDEX,
fadd03c6
AK		 254 /*
255 * Below are used with 4k page size and hugetlb
256 */
257 HTLB_16M_INDEX,
258 HTLB_16G_INDEX,
0c4d2680
AK		 259};
260
d6a9996e
AK		 261extern unsigned long __vmalloc_start;
262extern unsigned long __vmalloc_end;
263#define VMALLOC_START __vmalloc_start
264#define VMALLOC_END __vmalloc_end
265
d909f910
NP		 266static inline unsigned int ioremap_max_order(void)
267{
268 if (radix_enabled())
269 return PUD_SHIFT;
270 return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */
271}
272#define IOREMAP_MAX_ORDER ioremap_max_order()
273
d6a9996e 274extern unsigned long __kernel_virt_start;
63ee9b2f 275extern unsigned long __kernel_io_start;
a35a3c6f 276extern unsigned long __kernel_io_end;
d6a9996e 277#define KERN_VIRT_START __kernel_virt_start
63ee9b2f 278#define KERN_IO_START __kernel_io_start
a35a3c6f
AK		 279#define KERN_IO_END __kernel_io_end
280
d6a9996e 281extern struct page *vmemmap;
bfa37087 282extern unsigned long pci_io_base;
dd1842a2 283#endif /* __ASSEMBLY__ */
3dfcb315 284
ab537dca 285#include <asm/book3s/64/hash.h>
b0b5e9b1 286#include <asm/book3s/64/radix.h>
3dfcb315 287
b32d5d7e
AK		 288#if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS
289#define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS
290#else
291#define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS
292#endif
293
294
a9252aae
AK		 295#ifdef CONFIG_PPC_64K_PAGES
296#include <asm/book3s/64/pgtable-64k.h>
297#else
298#include <asm/book3s/64/pgtable-4k.h>
299#endif
300
3dfcb315 301#include <asm/barrier.h>
3dfcb315 302/*
a35a3c6f 303 * IO space itself carved into the PIO region (ISA and PHB IO space) and
3dfcb315
AK		 304 * the ioremap space
305 *
306 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
307 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
308 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
309 */
3dfcb315
AK		 310#define FULL_IO_SIZE 0x80000000ul
311#define ISA_IO_BASE (KERN_IO_START)
312#define ISA_IO_END (KERN_IO_START + 0x10000ul)
313#define PHB_IO_BASE (ISA_IO_END)
314#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
315#define IOREMAP_BASE (PHB_IO_END)
4a45b746 316#define IOREMAP_START (ioremap_bot)
9ccba66d
CL		 317#define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE)
318#define FIXADDR_SIZE SZ_32M
d3e01796 319#define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE)
3dfcb315 320
3dfcb315
AK		 321#ifndef __ASSEMBLY__
322
323/*
324 * This is the default implementation of various PTE accessors, it's
325 * used in all cases except Book3S with 64K pages where we have a
326 * concept of sub-pages
327 */
328#ifndef __real_pte
329
ff31e105 330#define __real_pte(e, p, o) ((real_pte_t){(e)})
3dfcb315 331#define __rpte_to_pte(r) ((r).pte)
945537df 332#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 333
334#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
335 do { \
336 index = 0; \
337 shift = mmu_psize_defs[psize].shift; \
338
339#define pte_iterate_hashed_end() } while(0)
340
341/*
342 * We expect this to be called only for user addresses or kernel virtual
343 * addresses other than the linear mapping.
344 */
345#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
346
347#endif /* __real_pte */
348
ac94ac79
AK		 349static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
350 pte_t *ptep, unsigned long clr,
351 unsigned long set, int huge)
352{
353 if (radix_enabled())
354 return radix__pte_update(mm, addr, ptep, clr, set, huge);
355 return hash__pte_update(mm, addr, ptep, clr, set, huge);
356}
13f829a5
AK		 357/*
358 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
359 * We currently remove entries from the hashtable regardless of whether
360 * the entry was young or dirty.
361 *
362 * We should be more intelligent about this but for the moment we override
363 * these functions and force a tlb flush unconditionally
364 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
365 * function for both hash and radix.
366 */
367static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
368 unsigned long addr, pte_t *ptep)
369{
370 unsigned long old;
371
66c570f5 372 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 373 return 0;
374 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
375 return (old & _PAGE_ACCESSED) != 0;
376}
377
378#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
379#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
380({ \
3cb1aa7a 381 __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
13f829a5
AK		 382})
383
3cb1aa7a
NP		 384/*
385 * On Book3S CPUs, clearing the accessed bit without a TLB flush
386 * doesn't cause data corruption. [ It could cause incorrect
387 * page aging and the (mistaken) reclaim of hot pages, but the
388 * chance of that should be relatively low. ]
389 *
390 * So as a performance optimization don't flush the TLB when
391 * clearing the accessed bit, it will eventually be flushed by
392 * a context switch or a VM operation anyway. [ In the rare
393 * event of it not getting flushed for a long time the delay
394 * shouldn't really matter because there's no real memory
395 * pressure for swapout to react to. ]
b11931e9
NP		 396 *
397 * Note: this optimisation also exists in pte_needs_flush() and
398 * huge_pmd_needs_flush().
3cb1aa7a
NP		 399 */
400#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
401#define ptep_clear_flush_young ptep_test_and_clear_young
402
403#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
404#define pmdp_clear_flush_young pmdp_test_and_clear_young
405
d19469e8
AK		 406static inline int pte_write(pte_t pte)
407{
d6379159 408 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
d19469e8
AK		 409}
410
ca8afd40
CL		 411static inline int pte_read(pte_t pte)
412{
413 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
414}
415
13f829a5
AK		 416#define __HAVE_ARCH_PTEP_SET_WRPROTECT
417static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
418 pte_t *ptep)
419{
d6379159 420 if (pte_write(*ptep))
52c50ca7 421 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
13f829a5
AK		 422}
423
8e581d43 424#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
13f829a5
AK		 425static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
426 unsigned long addr, pte_t *ptep)
427{
d6379159 428 if (pte_write(*ptep))
52c50ca7 429 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
13f829a5
AK		 430}
431
432#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
433static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
434 unsigned long addr, pte_t *ptep)
435{
436 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
437 return __pte(old);
438}
439
f4894b80
AK		 440#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
441static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
442 unsigned long addr,
443 pte_t *ptep, int full)
444{
445 if (full && radix_enabled()) {
446 /*
2bf1071a
NP		 447 * We know that this is a full mm pte clear and
448 * hence can be sure there is no parallel set_pte.
f4894b80
AK		 449 */
450 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
451 }
452 return ptep_get_and_clear(mm, addr, ptep);
453}
454
455
13f829a5
AK		 456static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
457 pte_t * ptep)
458{
459 pte_update(mm, addr, ptep, ~0UL, 0, 0);
460}
66c570f5 461
66c570f5
AK		 462static inline int pte_dirty(pte_t pte)
463{
464 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
465}
466
467static inline int pte_young(pte_t pte)
468{
469 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
470}
471
472static inline int pte_special(pte_t pte)
473{
474 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
475}
476
daba7902
CL		 477static inline bool pte_exec(pte_t pte)
478{
479 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC));
480}
481
13f829a5
AK		 482
483#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
484static inline bool pte_soft_dirty(pte_t pte)
485{
66c570f5 486 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 487}
66c570f5 488
13f829a5
AK		 489static inline pte_t pte_mksoft_dirty(pte_t pte)
490{
1b2443a5 491 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5
AK		 492}
493
494static inline pte_t pte_clear_soft_dirty(pte_t pte)
495{
1b2443a5 496 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY));
13f829a5
AK		 497}
498#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
499
500#ifdef CONFIG_NUMA_BALANCING
13f829a5
AK		 501static inline int pte_protnone(pte_t pte)
502{
c137a275
AK		 503 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
504 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
505}
13f829a5
AK		 506#endif /* CONFIG_NUMA_BALANCING */
507
ec4abf1e
AK		 508static inline bool pte_hw_valid(pte_t pte)
509{
510 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) ==
511 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
512}
513
13f829a5
AK		 514static inline int pte_present(pte_t pte)
515{
bd0dbb73
AK		 516 /*
517 * A pte is considerent present if _PAGE_PRESENT is set.
518 * We also need to consider the pte present which is marked
519 * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID
520 * if we find _PAGE_PRESENT cleared.
521 */
f72a85e3 522
ec4abf1e
AK		 523 if (pte_hw_valid(pte))
524 return true;
525 return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) ==
526 cpu_to_be64(_PAGE_INVALID | _PAGE_PTE);
daba7902
CL		 527}
528
bca7aacf 529#ifdef CONFIG_PPC_MEM_KEYS
f2407ef3 530extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
bca7aacf
RP		 531#else
532static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
533{
534 return true;
535}
536#endif /* CONFIG_PPC_MEM_KEYS */
f2407ef3 537
1b2443a5
CL		 538static inline bool pte_user(pte_t pte)
539{
540 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
541}
542
f72a85e3
AK		 543#define pte_access_permitted pte_access_permitted
544static inline bool pte_access_permitted(pte_t pte, bool write)
545{
f72a85e3
AK		 546 /*
547 * _PAGE_READ is needed for any access and will be
548 * cleared for PROT_NONE
549 */
1b2443a5 550 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
f72a85e3
AK		 551 return false;
552
1b2443a5 553 if (write && !pte_write(pte))
f72a85e3 554 return false;
bca7aacf
RP		 555
556 return arch_pte_access_permitted(pte_val(pte), write, 0);
f72a85e3
AK		 557}
558
13f829a5
AK		 559/*
560 * Conversion functions: convert a page and protection to a page entry,
561 * and a page entry and page directory to the page they refer to.
562 *
563 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
564 * long for now.
565 */
566static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
567{
6bb25170
NP		 568 VM_BUG_ON(pfn >> (64 - PAGE_SHIFT));
569 VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK);
570
379c926d 571 return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE);
13f829a5
AK		 572}
573
13f829a5
AK		 574/* Generic modifiers for PTE bits */
575static inline pte_t pte_wrprotect(pte_t pte)
576{
1b2443a5 577 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE));
13f829a5
AK		 578}
579
daba7902
CL		 580static inline pte_t pte_exprotect(pte_t pte)
581{
1b2443a5 582 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC));
13f829a5
AK		 583}
584
585static inline pte_t pte_mkclean(pte_t pte)
586{
1b2443a5 587 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY));
13f829a5
AK		 588}
589
590static inline pte_t pte_mkold(pte_t pte)
591{
1b2443a5 592 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED));
13f829a5
AK		 593}
594
daba7902
CL		 595static inline pte_t pte_mkexec(pte_t pte)
596{
1b2443a5 597 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC));
daba7902
CL		 598}
599
2f0584f3 600static inline pte_t pte_mkwrite_novma(pte_t pte)
13f829a5
AK		 601{
602 /*
603 * write implies read, hence set both
604 */
1b2443a5 605 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW));
13f829a5
AK		 606}
607
608static inline pte_t pte_mkdirty(pte_t pte)
609{
1b2443a5 610 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
13f829a5
AK		 611}
612
613static inline pte_t pte_mkyoung(pte_t pte)
614{
1b2443a5 615 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED));
13f829a5
AK		 616}
617
618static inline pte_t pte_mkspecial(pte_t pte)
619{
1b2443a5 620 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL));
13f829a5
AK		 621}
622
623static inline pte_t pte_mkhuge(pte_t pte)
624{
625 return pte;
626}
627
ebd31197
OH		 628static inline pte_t pte_mkdevmap(pte_t pte)
629{
1b2443a5 630 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP));
ebd31197
OH		 631}
632
daba7902
CL		 633static inline pte_t pte_mkprivileged(pte_t pte)
634{
1b2443a5 635 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED));
daba7902
CL		 636}
637
638static inline pte_t pte_mkuser(pte_t pte)
639{
1b2443a5 640 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED));
ebd31197
OH		 641}
642
c9c98bc5
OH		 643/*
644 * This is potentially called with a pmd as the argument, in which case it's not
645 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
646 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
647 * use in page directory entries (ie. non-ptes).
648 */
ebd31197
OH		 649static inline int pte_devmap(pte_t pte)
650{
c9c98bc5
OH		 651 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
652
653 return (pte_raw(pte) & mask) == mask;
ebd31197
OH		 654}
655
13f829a5
AK		 656static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
657{
658 /* FIXME!! check whether this need to be a conditional */
1b2443a5
CL		 659 return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) |
660 cpu_to_be64(pgprot_val(newprot)));
34fbadd8
AK		 661}
662
663/* Encode and de-code a swap entry */
664#define MAX_SWAPFILES_CHECK() do { \
665 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
666 /* \
667 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
668 * We filter HPTEFLAGS on set_pte. \
669 */ \
03ac1b71 670 BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \
34fbadd8 671 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
bff9beaa 672 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \
34fbadd8 673 } while (0)
3159f943 674
34fbadd8 675#define SWP_TYPE_BITS 5
03ac1b71
DH		 676#define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1)
677#define __swp_type(x) ((x).val & SWP_TYPE_MASK)
34fbadd8
AK		 678#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
679#define __swp_entry(type, offset) ((swp_entry_t) { \
03ac1b71 680 (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
34fbadd8
AK		 681/*
682 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
683 * swap type and offset we get from swap and convert that to pte to find a
684 * matching pte in linux page table.
685 * Clear bits not found in swap entries here.
686 */
687#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
688#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
a0820ff3
AK		 689#define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd)))
690#define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x)))
34fbadd8
AK		 691
692#ifdef CONFIG_MEM_SOFT_DIRTY
bff9beaa 693#define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY
34fbadd8
AK		 694#else
695#define _PAGE_SWP_SOFT_DIRTY 0UL
696#endif /* CONFIG_MEM_SOFT_DIRTY */
697
bff9beaa
DH		 698#define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT
699
34fbadd8
AK		 700#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
701static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
702{
1b2443a5 703 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 704}
66c570f5 705
34fbadd8
AK		 706static inline bool pte_swp_soft_dirty(pte_t pte)
707{
66c570f5 708 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 709}
66c570f5 710
34fbadd8
AK		 711static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
712{
1b2443a5 713 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY));
34fbadd8
AK		 714}
715#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
716
bff9beaa
DH		 717static inline pte_t pte_swp_mkexclusive(pte_t pte)
718{
719 return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
720}
721
722static inline int pte_swp_exclusive(pte_t pte)
723{
724 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE));
725}
726
727static inline pte_t pte_swp_clear_exclusive(pte_t pte)
728{
729 return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE));
730}
731
34fbadd8
AK		 732static inline bool check_pte_access(unsigned long access, unsigned long ptev)
733{
734 /*
735 * This check for _PAGE_RWX and _PAGE_PRESENT bits
736 */
737 if (access & ~ptev)
738 return false;
739 /*
740 * This check for access to privilege space
741 */
742 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
743 return false;
744
745 return true;
746}
ac94ac79
AK		 747/*
748 * Generic functions with hash/radix callbacks
749 */
750
e4c1112c 751static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
b3603e17 752 pte_t *ptep, pte_t entry,
e4c1112c
AK		 753 unsigned long address,
754 int psize)
ac94ac79
AK		 755{
756 if (radix_enabled())
e4c1112c
AK		 757 return radix__ptep_set_access_flags(vma, ptep, entry,
758 address, psize);
ac94ac79
AK		 759 return hash__ptep_set_access_flags(ptep, entry);
760}
761
762#define __HAVE_ARCH_PTE_SAME
763static inline int pte_same(pte_t pte_a, pte_t pte_b)
764{
765 if (radix_enabled())
766 return radix__pte_same(pte_a, pte_b);
767 return hash__pte_same(pte_a, pte_b);
768}
769
770static inline int pte_none(pte_t pte)
771{
772 if (radix_enabled())
773 return radix__pte_none(pte);
774 return hash__pte_none(pte);
775}
776
777static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
778 pte_t *ptep, pte_t pte, int percpu)
779{
379c926d
AK		 780
781 VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE)));
782 /*
783 * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE
784 * in all the callers.
785 */
786 pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE));
787
ac94ac79
AK		 788 if (radix_enabled())
789 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
790 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
791}
34fbadd8 792
12564485
SA		 793#define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
794
13f829a5
AK		 795#define pgprot_noncached pgprot_noncached
796static inline pgprot_t pgprot_noncached(pgprot_t prot)
797{
798 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
799 _PAGE_NON_IDEMPOTENT);
800}
801
802#define pgprot_noncached_wc pgprot_noncached_wc
803static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
804{
805 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
806 _PAGE_TOLERANT);
807}
808
809#define pgprot_cached pgprot_cached
810static inline pgprot_t pgprot_cached(pgprot_t prot)
811{
812 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
813}
814
815#define pgprot_writecombine pgprot_writecombine
816static inline pgprot_t pgprot_writecombine(pgprot_t prot)
817{
818 return pgprot_noncached_wc(prot);
819}
820/*
821 * check a pte mapping have cache inhibited property
822 */
823static inline bool pte_ci(pte_t pte)
824{
1b2443a5 825 __be64 pte_v = pte_raw(pte);
13f829a5 826
1b2443a5
CL		 827 if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) ||
828 ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT)))
13f829a5
AK		 829 return true;
830 return false;
831}
832
f281b5d5
AK		 833static inline void pmd_clear(pmd_t *pmdp)
834{
392b4669
AK		 835 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
836 /*
837 * Don't use this if we can possibly have a hash page table
838 * entry mapping this.
839 */
840 WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
841 }
f281b5d5
AK		 842 *pmdp = __pmd(0);
843}
844
66c570f5
AK		 845static inline int pmd_none(pmd_t pmd)
846{
847 return !pmd_raw(pmd);
848}
849
850static inline int pmd_present(pmd_t pmd)
851{
da7ad366
AK		 852 /*
853 * A pmd is considerent present if _PAGE_PRESENT is set.
854 * We also need to consider the pmd present which is marked
855 * invalid during a split. Hence we look for _PAGE_INVALID
856 * if we find _PAGE_PRESENT cleared.
857 */
858 if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID))
859 return true;
66c570f5 860
da7ad366 861 return false;
66c570f5 862}
3dfcb315 863
33258a1d
NP		 864static inline int pmd_is_serializing(pmd_t pmd)
865{
866 /*
867 * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear
868 * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate).
869 *
870 * This condition may also occur when flushing a pmd while flushing
871 * it (see ptep_modify_prot_start), so callers must ensure this
872 * case is fine as well.
873 */
874 if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) ==
875 cpu_to_be64(_PAGE_INVALID))
876 return true;
877
878 return false;
879}
880
ac94ac79
AK		 881static inline int pmd_bad(pmd_t pmd)
882{
883 if (radix_enabled())
884 return radix__pmd_bad(pmd);
885 return hash__pmd_bad(pmd);
886}
887
f281b5d5
AK		 888static inline void pud_clear(pud_t *pudp)
889{
392b4669
AK		 890 if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) {
891 /*
892 * Don't use this if we can possibly have a hash page table
893 * entry mapping this.
894 */
895 WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE));
896 }
f281b5d5
AK		 897 *pudp = __pud(0);
898}
899
66c570f5
AK		 900static inline int pud_none(pud_t pud)
901{
902 return !pud_raw(pud);
903}
904
905static inline int pud_present(pud_t pud)
906{
a5800762 907 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT));
66c570f5 908}
3dfcb315
AK		 909
910extern struct page *pud_page(pud_t pud);
371352ca 911extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 912static inline pte_t pud_pte(pud_t pud)
913{
66c570f5 914 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 915}
916
917static inline pud_t pte_pud(pte_t pte)
918{
66c570f5 919 return __pud_raw(pte_raw(pte));
3dfcb315 920}
27af67f3
AK		 921
922static inline pte_t *pudp_ptep(pud_t *pud)
923{
924 return (pte_t *)pud;
925}
926
927#define pud_pfn(pud) pte_pfn(pud_pte(pud))
928#define pud_dirty(pud) pte_dirty(pud_pte(pud))
929#define pud_young(pud) pte_young(pud_pte(pud))
930#define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud)))
931#define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud)))
932#define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud)))
933#define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud)))
934#define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
f441ff73 935#define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud)))
3dfcb315 936#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79 937
27af67f3
AK		 938#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
939#define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud))
940#define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud)))
941#define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud)))
942#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
943
ac94ac79
AK		 944static inline int pud_bad(pud_t pud)
945{
946 if (radix_enabled())
947 return radix__pud_bad(pud);
948 return hash__pud_bad(pud);
949}
950
f72a85e3
AK		 951#define pud_access_permitted pud_access_permitted
952static inline bool pud_access_permitted(pud_t pud, bool write)
953{
954 return pte_access_permitted(pud_pte(pud), write);
955}
ac94ac79 956
2fb47060
MR		 957#define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) })
958static inline __be64 p4d_raw(p4d_t x)
959{
960 return pgd_raw(x.pgd);
961}
962
963#define p4d_write(p4d) pte_write(p4d_pte(p4d))
3dfcb315 964
2fb47060 965static inline void p4d_clear(p4d_t *p4dp)
368ced78 966{
2fb47060 967 *p4dp = __p4d(0);
368ced78
AK		 968}
969
2fb47060 970static inline int p4d_none(p4d_t p4d)
66c570f5 971{
2fb47060 972 return !p4d_raw(p4d);
66c570f5
AK		 973}
974
2fb47060 975static inline int p4d_present(p4d_t p4d)
66c570f5 976{
2fb47060 977 return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT));
66c570f5 978}
368ced78 979
2fb47060 980static inline pte_t p4d_pte(p4d_t p4d)
368ced78 981{
2fb47060 982 return __pte_raw(p4d_raw(p4d));
368ced78
AK		 983}
984
2fb47060 985static inline p4d_t pte_p4d(pte_t pte)
368ced78 986{
2fb47060 987 return __p4d_raw(pte_raw(pte));
368ced78
AK		 988}
989
2fb47060 990static inline int p4d_bad(p4d_t p4d)
ac94ac79
AK		 991{
992 if (radix_enabled())
2fb47060
MR		 993 return radix__p4d_bad(p4d);
994 return hash__p4d_bad(p4d);
ac94ac79
AK		 995}
996
2fb47060
MR		 997#define p4d_access_permitted p4d_access_permitted
998static inline bool p4d_access_permitted(p4d_t p4d, bool write)
f72a85e3 999{
2fb47060 1000 return pte_access_permitted(p4d_pte(p4d), write);
f72a85e3
AK		 1001}
1002
2fb47060 1003extern struct page *p4d_page(p4d_t p4d);
368ced78 1004
aba480e1
AK		 1005/* Pointers in the page table tree are physical addresses */
1006#define __pgtable_ptr_val(ptr) __pa(ptr)
1007
dc4875f0
AK		 1008static inline pud_t *p4d_pgtable(p4d_t p4d)
1009{
1010 return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS);
1011}
aba480e1 1012
9cf6fa24
AK		 1013static inline pmd_t *pud_pgtable(pud_t pud)
1014{
1015 return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS);
1016}
1017
3dfcb315
AK		 1018#define pmd_ERROR(e) \
1019 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 1020#define pud_ERROR(e) \
1021 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 1022#define pgd_ERROR(e) \
1023 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1024
c766ee72 1025static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
7207f436 1026{
d9225ad9
AK		 1027 if (radix_enabled()) {
1028#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1029 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1030 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1031#endif
c766ee72 1032 return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE);
d9225ad9 1033 }
c766ee72 1034 return hash__map_kernel_page(ea, pa, prot);
7207f436 1035}
31a14fae 1036
aec98260
CL		 1037void unmap_kernel_page(unsigned long va);
1038
31a14fae
AK		 1039static inline int __meminit vmemmap_create_mapping(unsigned long start,
1040 unsigned long page_size,
1041 unsigned long phys)
7207f436 1042{
d9225ad9
AK		 1043 if (radix_enabled())
1044 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 1045 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 1046}
31a14fae
AK		 1047
1048#ifdef CONFIG_MEMORY_HOTPLUG
1049static inline void vmemmap_remove_mapping(unsigned long start,
1050 unsigned long page_size)
7207f436 1051{
d9225ad9
AK		 1052 if (radix_enabled())
1053 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 1054 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 1055}
31a14fae 1056#endif
3dfcb315 1057
a5edf981 1058#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE)
4f703e7f
JS		 1059static inline void __kernel_map_pages(struct page *page, int numpages, int enable)
1060{
1061 if (radix_enabled())
1062 radix__kernel_map_pages(page, numpages, enable);
1063 else
1064 hash__kernel_map_pages(page, numpages, enable);
1065}
1066#endif
1067
3dfcb315
AK		 1068static inline pte_t pmd_pte(pmd_t pmd)
1069{
66c570f5 1070 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 1071}
1072
1073static inline pmd_t pte_pmd(pte_t pte)
1074{
66c570f5 1075 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 1076}
1077
1078static inline pte_t *pmdp_ptep(pmd_t *pmd)
1079{
1080 return (pte_t *)pmd;
1081}
3dfcb315
AK		 1082#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1083#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1084#define pmd_young(pmd) pte_young(pmd_pte(pmd))
1085#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1086#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1087#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 1088#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315 1089#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
2f0584f3 1090#define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd)))
7207f436
LD		 1091
1092#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1093#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1094#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1095#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
a0820ff3
AK		 1096
1097#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1098#define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd)))
1099#define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd))
1100#define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd)))
1101#endif
7207f436
LD		 1102#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1103
1ca72129
AK		 1104#ifdef CONFIG_NUMA_BALANCING
1105static inline int pmd_protnone(pmd_t pmd)
1106{
1107 return pte_protnone(pmd_pte(pmd));
1108}
1109#endif /* CONFIG_NUMA_BALANCING */
3dfcb315 1110
3dfcb315
AK		 1111#define pmd_write(pmd) pte_write(pmd_pte(pmd))
1112
f72a85e3
AK		 1113#define pmd_access_permitted pmd_access_permitted
1114static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1115{
33258a1d
NP		 1116 /*
1117 * pmdp_invalidate sets this combination (which is not caught by
1118 * !pte_present() check in pte_access_permitted), to prevent
1119 * lock-free lookups, as part of the serialize_against_pte_lookup()
1120 * synchronisation.
1121 *
1122 * This also catches the case where the PTE's hardware PRESENT bit is
1123 * cleared while TLB is flushed, which is suboptimal but should not
1124 * be frequent.
1125 */
1126 if (pmd_is_serializing(pmd))
1127 return false;
1128
f72a85e3
AK		 1129 return pte_access_permitted(pmd_pte(pmd), write);
1130}
1131
6a1ea362
AK		 1132#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1133extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
27af67f3 1134extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot);
6a1ea362
AK		 1135extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1136extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1137extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1138 pmd_t *pmdp, pmd_t pmd);
27af67f3
AK		 1139extern void set_pud_at(struct mm_struct *mm, unsigned long addr,
1140 pud_t *pudp, pud_t pud);
1141
18594f9b
NP		 1142static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
1143 unsigned long addr, pmd_t *pmd)
1144{
1145}
1146
27af67f3
AK		 1147static inline void update_mmu_cache_pud(struct vm_area_struct *vma,
1148 unsigned long addr, pud_t *pud)
1149{
1150}
1151
3df33f12
AK		 1152extern int hash__has_transparent_hugepage(void);
1153static inline int has_transparent_hugepage(void)
1154{
bde3eb62
AK		 1155 if (radix_enabled())
1156 return radix__has_transparent_hugepage();
3df33f12
AK		 1157 return hash__has_transparent_hugepage();
1158}
c04a5880 1159#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 1160
27af67f3
AK		 1161static inline int has_transparent_pud_hugepage(void)
1162{
1163 if (radix_enabled())
1164 return radix__has_transparent_pud_hugepage();
1165 return 0;
1166}
1167#define has_transparent_pud_hugepage has_transparent_pud_hugepage
1168
3df33f12
AK		 1169static inline unsigned long
1170pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1171 unsigned long clr, unsigned long set)
3dfcb315 1172{
bde3eb62
AK		 1173 if (radix_enabled())
1174 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 1175 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1176}
1177
27af67f3
AK		 1178static inline unsigned long
1179pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp,
1180 unsigned long clr, unsigned long set)
1181{
1182 if (radix_enabled())
1183 return radix__pud_hugepage_update(mm, addr, pudp, clr, set);
1184 BUG();
1185 return pud_val(*pudp);
1186}
1187
8890e033
AK		 1188/*
1189 * returns true for pmd migration entries, THP, devmap, hugetlb
1190 * But compile time dependent on THP config
1191 */
3df33f12
AK		 1192static inline int pmd_large(pmd_t pmd)
1193{
66c570f5 1194 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 1195}
1196
27af67f3
AK		 1197static inline int pud_large(pud_t pud)
1198{
1199 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
1200}
1201
3df33f12
AK		 1202/*
1203 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1204 * the below will work for radix too
1205 */
1206static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1207 unsigned long addr, pmd_t *pmdp)
1208{
1209 unsigned long old;
1210
66c570f5 1211 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 1212 return 0;
1213 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1214 return ((old & _PAGE_ACCESSED) != 0);
1215}
1216
27af67f3
AK		 1217static inline int __pudp_test_and_clear_young(struct mm_struct *mm,
1218 unsigned long addr, pud_t *pudp)
1219{
1220 unsigned long old;
1221
1222 if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
1223 return 0;
1224 old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0);
1225 return ((old & _PAGE_ACCESSED) != 0);
1226}
1227
3df33f12
AK		 1228#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1229static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1230 pmd_t *pmdp)
1231{
d6379159 1232 if (pmd_write(*pmdp))
52c50ca7 1233 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
3dfcb315
AK		 1234}
1235
27af67f3
AK		 1236#define __HAVE_ARCH_PUDP_SET_WRPROTECT
1237static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1238 pud_t *pudp)
1239{
1240 if (pud_write(*pudp))
1241 pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0);
1242}
1243
8890e033
AK		 1244/*
1245 * Only returns true for a THP. False for pmd migration entry.
1246 * We also need to return true when we come across a pte that
1247 * in between a thp split. While splitting THP, we mark the pmd
1248 * invalid (pmdp_invalidate()) before we set it with pte page
1249 * address. A pmd_trans_huge() check against a pmd entry during that time
1250 * should return true.
1251 * We should not call this on a hugetlb entry. We should check for HugeTLB
1252 * entry using vma->vm_flags
ee65728e 1253 * The page table walk rule is explained in Documentation/mm/transhuge.rst
8890e033 1254 */
ab624762
AK		 1255static inline int pmd_trans_huge(pmd_t pmd)
1256{
8890e033
AK		 1257 if (!pmd_present(pmd))
1258 return false;
1259
ab624762
AK		 1260 if (radix_enabled())
1261 return radix__pmd_trans_huge(pmd);
1262 return hash__pmd_trans_huge(pmd);
1263}
1264
27af67f3
AK		 1265static inline int pud_trans_huge(pud_t pud)
1266{
1267 if (!pud_present(pud))
1268 return false;
1269
1270 if (radix_enabled())
1271 return radix__pud_trans_huge(pud);
1272 return 0;
1273}
1274
1275
ab624762
AK		 1276#define __HAVE_ARCH_PMD_SAME
1277static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1278{
1279 if (radix_enabled())
1280 return radix__pmd_same(pmd_a, pmd_b);
1281 return hash__pmd_same(pmd_a, pmd_b);
1282}
1283
27af67f3
AK		 1284#define pud_same pud_same
1285static inline int pud_same(pud_t pud_a, pud_t pud_b)
1286{
1287 if (radix_enabled())
1288 return radix__pud_same(pud_a, pud_b);
1289 return hash__pud_same(pud_a, pud_b);
1290}
1291
1292
53f45ecc 1293static inline pmd_t __pmd_mkhuge(pmd_t pmd)
3dfcb315 1294{
ab624762
AK		 1295 if (radix_enabled())
1296 return radix__pmd_mkhuge(pmd);
1297 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 1298}
1299
27af67f3
AK		 1300static inline pud_t __pud_mkhuge(pud_t pud)
1301{
1302 if (radix_enabled())
1303 return radix__pud_mkhuge(pud);
1304 BUG();
1305 return pud;
1306}
1307
53f45ecc
AK		 1308/*
1309 * pfn_pmd return a pmd_t that can be used as pmd pte entry.
1310 */
1311static inline pmd_t pmd_mkhuge(pmd_t pmd)
1312{
1313#ifdef CONFIG_DEBUG_VM
1314 if (radix_enabled())
1315 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0);
1316 else
1317 WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) !=
1318 cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE));
1319#endif
1320 return pmd;
1321}
1322
27af67f3
AK		 1323static inline pud_t pud_mkhuge(pud_t pud)
1324{
1325#ifdef CONFIG_DEBUG_VM
1326 if (radix_enabled())
1327 WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0);
1328 else
1329 WARN_ON(1);
1330#endif
1331 return pud;
1332}
1333
1334
3dfcb315
AK		 1335#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1336extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1337 unsigned long address, pmd_t *pmdp,
1338 pmd_t entry, int dirty);
27af67f3
AK		 1339#define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS
1340extern int pudp_set_access_flags(struct vm_area_struct *vma,
1341 unsigned long address, pud_t *pudp,
1342 pud_t entry, int dirty);
3dfcb315 1343
3dfcb315
AK		 1344#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1345extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1346 unsigned long address, pmd_t *pmdp);
27af67f3
AK		 1347#define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG
1348extern int pudp_test_and_clear_young(struct vm_area_struct *vma,
1349 unsigned long address, pud_t *pudp);
1350
3dfcb315
AK		 1351
1352#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 1353static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1354 unsigned long addr, pmd_t *pmdp)
1355{
bde3eb62
AK		 1356 if (radix_enabled())
1357 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 1358 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1359}
3dfcb315 1360
27af67f3
AK		 1361#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR
1362static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm,
1363 unsigned long addr, pud_t *pudp)
1364{
1365 if (radix_enabled())
1366 return radix__pudp_huge_get_and_clear(mm, addr, pudp);
1367 BUG();
1368 return *pudp;
1369}
1370
3df33f12
AK		 1371static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1372 unsigned long address, pmd_t *pmdp)
1373{
bde3eb62
AK		 1374 if (radix_enabled())
1375 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 1376 return hash__pmdp_collapse_flush(vma, address, pmdp);
1377}
3dfcb315
AK		 1378#define pmdp_collapse_flush pmdp_collapse_flush
1379
75358ea3
AK		 1380#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
1381pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
1382 unsigned long addr,
1383 pmd_t *pmdp, int full);
1384
27af67f3
AK		 1385#define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL
1386pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma,
1387 unsigned long addr,
1388 pud_t *pudp, int full);
1389
3dfcb315 1390#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 1391static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1392 pmd_t *pmdp, pgtable_t pgtable)
1393{
bde3eb62
AK		 1394 if (radix_enabled())
1395 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 1396 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1397}
1398
3dfcb315 1399#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 1400static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1401 pmd_t *pmdp)
1402{
bde3eb62
AK		 1403 if (radix_enabled())
1404 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 1405 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1406}
3dfcb315
AK		 1407
1408#define __HAVE_ARCH_PMDP_INVALIDATE
8cc931e0
AK		 1409extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1410 pmd_t *pmdp);
3dfcb315
AK		 1411
1412#define pmd_move_must_withdraw pmd_move_must_withdraw
1413struct spinlock;
579b9239
AK		 1414extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1415 struct spinlock *old_pmd_ptl,
1416 struct vm_area_struct *vma);
1417/*
1418 * Hash translation mode use the deposited table to store hash pte
1419 * slot information.
1420 */
953c66c2
AK		 1421#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1422static inline bool arch_needs_pgtable_deposit(void)
1423{
1424 if (radix_enabled())
1425 return false;
1426 return true;
1427}
fa4531f7 1428extern void serialize_against_pte_lookup(struct mm_struct *mm);
953c66c2 1429
ebd31197
OH		 1430
1431static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1432{
36b78402
AK		 1433 if (radix_enabled())
1434 return radix__pmd_mkdevmap(pmd);
1435 return hash__pmd_mkdevmap(pmd);
ebd31197
OH		 1436}
1437
27af67f3
AK		 1438static inline pud_t pud_mkdevmap(pud_t pud)
1439{
1440 if (radix_enabled())
1441 return radix__pud_mkdevmap(pud);
1442 BUG();
1443 return pud;
1444}
1445
ebd31197
OH		 1446static inline int pmd_devmap(pmd_t pmd)
1447{
1448 return pte_devmap(pmd_pte(pmd));
1449}
1450
1451static inline int pud_devmap(pud_t pud)
1452{
27af67f3 1453 return pte_devmap(pud_pte(pud));
ebd31197
OH		 1454}
1455
1456static inline int pgd_devmap(pgd_t pgd)
1457{
1458 return 0;
1459}
6a1ea362 1460#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
ebd31197 1461
5b323367
AK		 1462#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1463pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
1464void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1465 pte_t *, pte_t, pte_t);
1466
1467/*
1468 * Returns true for a R -> RW upgrade of pte
1469 */
1470static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val)
1471{
1472 if (!(old_val & _PAGE_READ))
1473 return false;
1474
1475 if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE))
1476 return true;
1477
1478 return false;
1479}
029d9252 1480
d6eacedd
AK		 1481/*
1482 * Like pmd_huge() and pmd_large(), but works regardless of config options
1483 */
1484#define pmd_is_leaf pmd_is_leaf
070434b1 1485#define pmd_leaf pmd_is_leaf
d6eacedd
AK		 1486static inline bool pmd_is_leaf(pmd_t pmd)
1487{
1488 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
1489}
1490
1491#define pud_is_leaf pud_is_leaf
070434b1 1492#define pud_leaf pud_is_leaf
d6eacedd
AK		 1493static inline bool pud_is_leaf(pud_t pud)
1494{
1495 return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE));
1496}
1497
3dfcb315
AK		 1498#endif /* __ASSEMBLY__ */
1499#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)