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Linux 4.18-rc1
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
3dfcb315
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519 4
9849a569
KS		 5#include <asm-generic/5level-fixup.h>
6
c137a275
AK		 7#ifndef __ASSEMBLY__
8#include <linux/mmdebug.h>
ebd31197 9#include <linux/bug.h>
c137a275 10#endif
9849a569 11
2e873519
AK		 12/*
13 * Common bits between hash and Radix page table
14 */
15#define _PAGE_BIT_SWAP_TYPE 0
16
35175033 17#define _PAGE_NA 0
6b8cb66a 18#define _PAGE_RO 0
812fadcb 19#define _PAGE_USER 0
6b8cb66a 20
2e873519
AK		 21#define _PAGE_EXEC 0x00001 /* execute permission */
22#define _PAGE_WRITE 0x00002 /* write access allowed */
23#define _PAGE_READ 0x00004 /* read access allowed */
24#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
25#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
26#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
27#define _PAGE_SAO 0x00010 /* Strong access order */
28#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
29#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
30#define _PAGE_DIRTY 0x00080 /* C: page changed */
31#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 32/*
2e873519 33 * Software bits
3dfcb315 34 */
69dfbaeb
AK		 35#define _RPAGE_SW0 0x2000000000000000UL
36#define _RPAGE_SW1 0x00800
37#define _RPAGE_SW2 0x00400
38#define _RPAGE_SW3 0x00200
049d567a
AK		 39#define _RPAGE_RSV1 0x1000000000000000UL
40#define _RPAGE_RSV2 0x0800000000000000UL
41#define _RPAGE_RSV3 0x0400000000000000UL
42#define _RPAGE_RSV4 0x0200000000000000UL
eb95d016 43#define _RPAGE_RSV5 0x00040UL
6aa59f51
AK		 44
45#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
46#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
47
48/*
49 * Top and bottom bits of RPN which can be used by hash
50 * translation mode, because we expect them to be zero
51 * otherwise.
52 */
32789d38
AK		 53#define _RPAGE_RPN0 0x01000
54#define _RPAGE_RPN1 0x02000
6aa59f51
AK		 55#define _RPAGE_RPN44 0x0100000000000000UL
56#define _RPAGE_RPN43 0x0080000000000000UL
57#define _RPAGE_RPN42 0x0040000000000000UL
58#define _RPAGE_RPN41 0x0020000000000000UL
049d567a 59
2f18d533
AK		 60/* Max physical address bit as per radix table */
61#define _RPAGE_PA_MAX 57
62
63/*
64 * Max physical address bit we will use for now.
65 *
66 * This is mostly a hardware limitation and for now Power9 has
67 * a 51 bit limit.
68 *
69 * This is different from the number of physical bit required to address
70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
72 * number of sections we can support (SECTIONS_SHIFT).
73 *
74 * This is different from Radix page table limitation above and
75 * should always be less than that. The limit is done such that
76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
77 * for hash linux page table specific bits.
78 *
79 * In order to be compatible with future hardware generations we keep
80 * some offsets and limit this for now to 53
81 */
82#define _PAGE_PA_MAX 53
83
69dfbaeb 84#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
69dfbaeb 85#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
ebd31197
OH		 86#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
87#define __HAVE_ARCH_PTE_DEVMAP
88
2e873519
AK		 89/*
90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
91 * Instead of fixing all of them, add an alternate define which
92 * maps CI pte mapping.
93 */
94#define _PAGE_NO_CACHE _PAGE_TOLERANT
95/*
2f18d533
AK		 96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
98 * and every thing below PAGE_SHIFT;
2e873519 99 */
2f18d533 100#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
2e873519
AK		 101/*
102 * set of bits not changed in pmd_modify. Even though we have hash specific bits
103 * in here, on radix we expect them to be zero.
104 */
105#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
107 _PAGE_SOFT_DIRTY)
108/*
109 * user access blocked by key
110 */
111#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
112#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
113#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
114 _PAGE_RW | _PAGE_EXEC)
115/*
116 * No page size encoding in the linux PTE
117 */
118#define _PAGE_PSIZE 0
119/*
120 * _PAGE_CHG_MASK masks of bits that are to be preserved across
121 * pgprot changes
122 */
123#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
125 _PAGE_SOFT_DIRTY)
eb95d016
RP		 126
127#define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \
128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4)
2e873519
AK		 129/*
130 * Mask of bits returned by pte_pgprot()
131 */
132#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
eb95d016 135 _PAGE_SOFT_DIRTY | H_PTE_PKEY)
3dfcb315 136/*
2e873519
AK		 137 * We define 2 sets of base prot bits, one for basic pages (ie,
138 * cacheable kernel and user pages) and one for non cacheable
139 * pages. We always set _PAGE_COHERENT when SMP is enabled or
140 * the processor might need it for DMA coherency.
3dfcb315 141 */
2e873519
AK		 142#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
143#define _PAGE_BASE (_PAGE_BASE_NC)
144
145/* Permission masks used to generate the __P and __S table,
146 *
147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
148 *
149 * Write permissions imply read permissions for now (we could make write-only
150 * pages on BookE but we don't bother for now). Execute permission control is
151 * possible on platforms that define _PAGE_EXEC
152 *
153 * Note due to the way vm flags are laid out, the bits are XWR
154 */
155#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
156#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
157#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
158#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
159#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
160#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
161#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
162
163#define __P000 PAGE_NONE
164#define __P001 PAGE_READONLY
165#define __P010 PAGE_COPY
166#define __P011 PAGE_COPY
167#define __P100 PAGE_READONLY_X
168#define __P101 PAGE_READONLY_X
169#define __P110 PAGE_COPY_X
170#define __P111 PAGE_COPY_X
171
172#define __S000 PAGE_NONE
173#define __S001 PAGE_READONLY
174#define __S010 PAGE_SHARED
175#define __S011 PAGE_SHARED
176#define __S100 PAGE_READONLY_X
177#define __S101 PAGE_READONLY_X
178#define __S110 PAGE_SHARED_X
179#define __S111 PAGE_SHARED_X
180
181/* Permission masks used for kernel mappings */
182#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
183#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
184 _PAGE_TOLERANT)
185#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
186 _PAGE_NON_IDEMPOTENT)
187#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
188#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
189#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
190
191/*
192 * Protection used for kernel text. We want the debuggers to be able to
193 * set breakpoints anywhere, so don't write protect the kernel text
194 * on platforms where such control is possible.
195 */
196#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
198#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
199#else
200#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
201#endif
202
203/* Make modules code happy. We don't set RO yet */
204#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
205#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 206
dd1842a2
AK		 207#ifndef __ASSEMBLY__
208/*
209 * page table defines
210 */
211extern unsigned long __pte_index_size;
212extern unsigned long __pmd_index_size;
213extern unsigned long __pud_index_size;
214extern unsigned long __pgd_index_size;
fae22116 215extern unsigned long __pud_cache_index;
dd1842a2
AK		 216#define PTE_INDEX_SIZE __pte_index_size
217#define PMD_INDEX_SIZE __pmd_index_size
218#define PUD_INDEX_SIZE __pud_index_size
219#define PGD_INDEX_SIZE __pgd_index_size
738f9645
AK		 220/* pmd table use page table fragments */
221#define PMD_CACHE_INDEX 0
fae22116 222#define PUD_CACHE_INDEX __pud_cache_index
dd1842a2
AK		 223/*
224 * Because of use of pte fragments and THP, size of page table
225 * are not always derived out of index size above.
226 */
227extern unsigned long __pte_table_size;
228extern unsigned long __pmd_table_size;
229extern unsigned long __pud_table_size;
230extern unsigned long __pgd_table_size;
231#define PTE_TABLE_SIZE __pte_table_size
232#define PMD_TABLE_SIZE __pmd_table_size
233#define PUD_TABLE_SIZE __pud_table_size
234#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 235
236extern unsigned long __pmd_val_bits;
237extern unsigned long __pud_val_bits;
238extern unsigned long __pgd_val_bits;
239#define PMD_VAL_BITS __pmd_val_bits
240#define PUD_VAL_BITS __pud_val_bits
241#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 242
243extern unsigned long __pte_frag_nr;
244#define PTE_FRAG_NR __pte_frag_nr
245extern unsigned long __pte_frag_size_shift;
246#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
247#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2 248
8a6c697b
AK		 249extern unsigned long __pmd_frag_nr;
250#define PMD_FRAG_NR __pmd_frag_nr
251extern unsigned long __pmd_frag_size_shift;
252#define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
253#define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
254
dd1842a2
AK		 255#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
256#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
257#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
258#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
259
260/* PMD_SHIFT determines what a second-level page table entry can map */
261#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
262#define PMD_SIZE (1UL << PMD_SHIFT)
263#define PMD_MASK (~(PMD_SIZE-1))
264
265/* PUD_SHIFT determines what a third-level page table entry can map */
266#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
267#define PUD_SIZE (1UL << PUD_SHIFT)
268#define PUD_MASK (~(PUD_SIZE-1))
269
270/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
271#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
272#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
273#define PGDIR_MASK (~(PGDIR_SIZE-1))
274
275/* Bits to mask out from a PMD to get to the PTE page */
276#define PMD_MASKED_BITS 0xc0000000000000ffUL
277/* Bits to mask out from a PUD to get to the PMD page */
278#define PUD_MASKED_BITS 0xc0000000000000ffUL
279/* Bits to mask out from a PGD to get to the PUD page */
280#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e 281
0c4d2680
AK		 282/*
283 * Used as an indicator for rcu callback functions
284 */
285enum pgtable_index {
286 PTE_INDEX = 0,
287 PMD_INDEX,
288 PUD_INDEX,
289 PGD_INDEX,
290};
291
d6a9996e
AK		 292extern unsigned long __vmalloc_start;
293extern unsigned long __vmalloc_end;
294#define VMALLOC_START __vmalloc_start
295#define VMALLOC_END __vmalloc_end
296
297extern unsigned long __kernel_virt_start;
298extern unsigned long __kernel_virt_size;
63ee9b2f 299extern unsigned long __kernel_io_start;
d6a9996e
AK		 300#define KERN_VIRT_START __kernel_virt_start
301#define KERN_VIRT_SIZE __kernel_virt_size
63ee9b2f 302#define KERN_IO_START __kernel_io_start
d6a9996e
AK		 303extern struct page *vmemmap;
304extern unsigned long ioremap_bot;
bfa37087 305extern unsigned long pci_io_base;
dd1842a2 306#endif /* __ASSEMBLY__ */
3dfcb315 307
ab537dca 308#include <asm/book3s/64/hash.h>
b0b5e9b1 309#include <asm/book3s/64/radix.h>
3dfcb315 310
a9252aae
AK		 311#ifdef CONFIG_PPC_64K_PAGES
312#include <asm/book3s/64/pgtable-64k.h>
313#else
314#include <asm/book3s/64/pgtable-4k.h>
315#endif
316
3dfcb315 317#include <asm/barrier.h>
3dfcb315
AK		 318/*
319 * The second half of the kernel virtual space is used for IO mappings,
320 * it's itself carved into the PIO region (ISA and PHB IO space) and
321 * the ioremap space
322 *
323 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
324 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
325 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
326 */
3dfcb315
AK		 327#define FULL_IO_SIZE 0x80000000ul
328#define ISA_IO_BASE (KERN_IO_START)
329#define ISA_IO_END (KERN_IO_START + 0x10000ul)
330#define PHB_IO_BASE (ISA_IO_END)
331#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
332#define IOREMAP_BASE (PHB_IO_END)
333#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
334
b0412ea9 335/* Advertise special mapping type for AGP */
b0412ea9
AK		 336#define HAVE_PAGE_AGP
337
3dfcb315
AK		 338#ifndef __ASSEMBLY__
339
340/*
341 * This is the default implementation of various PTE accessors, it's
342 * used in all cases except Book3S with 64K pages where we have a
343 * concept of sub-pages
344 */
345#ifndef __real_pte
346
ff31e105 347#define __real_pte(e, p, o) ((real_pte_t){(e)})
3dfcb315 348#define __rpte_to_pte(r) ((r).pte)
945537df 349#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 350
351#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
352 do { \
353 index = 0; \
354 shift = mmu_psize_defs[psize].shift; \
355
356#define pte_iterate_hashed_end() } while(0)
357
358/*
359 * We expect this to be called only for user addresses or kernel virtual
360 * addresses other than the linear mapping.
361 */
362#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
363
364#endif /* __real_pte */
365
ac94ac79
AK		 366static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
367 pte_t *ptep, unsigned long clr,
368 unsigned long set, int huge)
369{
370 if (radix_enabled())
371 return radix__pte_update(mm, addr, ptep, clr, set, huge);
372 return hash__pte_update(mm, addr, ptep, clr, set, huge);
373}
13f829a5
AK		 374/*
375 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
376 * We currently remove entries from the hashtable regardless of whether
377 * the entry was young or dirty.
378 *
379 * We should be more intelligent about this but for the moment we override
380 * these functions and force a tlb flush unconditionally
381 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
382 * function for both hash and radix.
383 */
384static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
385 unsigned long addr, pte_t *ptep)
386{
387 unsigned long old;
388
66c570f5 389 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 390 return 0;
391 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
392 return (old & _PAGE_ACCESSED) != 0;
393}
394
395#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
396#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
397({ \
398 int __r; \
399 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
400 __r; \
401})
402
d19469e8 403static inline int __pte_write(pte_t pte)
52c50ca7
AK		 404{
405 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
406}
407
408#ifdef CONFIG_NUMA_BALANCING
409#define pte_savedwrite pte_savedwrite
410static inline bool pte_savedwrite(pte_t pte)
411{
412 /*
413 * Saved write ptes are prot none ptes that doesn't have
414 * privileged bit sit. We mark prot none as one which has
415 * present and pviliged bit set and RWX cleared. To mark
416 * protnone which used to have _PAGE_WRITE set we clear
417 * the privileged bit.
418 */
419 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
420}
421#else
422#define pte_savedwrite pte_savedwrite
423static inline bool pte_savedwrite(pte_t pte)
424{
425 return false;
426}
427#endif
428
d19469e8
AK		 429static inline int pte_write(pte_t pte)
430{
431 return __pte_write(pte) || pte_savedwrite(pte);
432}
433
ca8afd40
CL		 434static inline int pte_read(pte_t pte)
435{
436 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
437}
438
13f829a5
AK		 439#define __HAVE_ARCH_PTEP_SET_WRPROTECT
440static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
441 pte_t *ptep)
442{
d19469e8 443 if (__pte_write(*ptep))
52c50ca7
AK		 444 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
445 else if (unlikely(pte_savedwrite(*ptep)))
446 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
13f829a5
AK		 447}
448
449static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
450 unsigned long addr, pte_t *ptep)
451{
52c50ca7
AK		 452 /*
453 * We should not find protnone for hugetlb, but this complete the
454 * interface.
455 */
d19469e8 456 if (__pte_write(*ptep))
52c50ca7
AK		 457 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
458 else if (unlikely(pte_savedwrite(*ptep)))
459 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
13f829a5
AK		 460}
461
462#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
463static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
464 unsigned long addr, pte_t *ptep)
465{
466 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
467 return __pte(old);
468}
469
f4894b80
AK		 470#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
471static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
472 unsigned long addr,
473 pte_t *ptep, int full)
474{
475 if (full && radix_enabled()) {
476 /*
477 * Let's skip the DD1 style pte update here. We know that
478 * this is a full mm pte clear and hence can be sure there is
479 * no parallel set_pte.
480 */
481 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
482 }
483 return ptep_get_and_clear(mm, addr, ptep);
484}
485
486
13f829a5
AK		 487static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
488 pte_t * ptep)
489{
490 pte_update(mm, addr, ptep, ~0UL, 0, 0);
491}
66c570f5 492
66c570f5
AK		 493static inline int pte_dirty(pte_t pte)
494{
495 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
496}
497
498static inline int pte_young(pte_t pte)
499{
500 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
501}
502
503static inline int pte_special(pte_t pte)
504{
505 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
506}
507
13f829a5
AK		 508static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
509
510#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
511static inline bool pte_soft_dirty(pte_t pte)
512{
66c570f5 513 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 514}
66c570f5 515
13f829a5
AK		 516static inline pte_t pte_mksoft_dirty(pte_t pte)
517{
518 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
519}
520
521static inline pte_t pte_clear_soft_dirty(pte_t pte)
522{
523 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
524}
525#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
526
527#ifdef CONFIG_NUMA_BALANCING
13f829a5
AK		 528static inline int pte_protnone(pte_t pte)
529{
c137a275
AK		 530 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
531 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
532}
533
534#define pte_mk_savedwrite pte_mk_savedwrite
535static inline pte_t pte_mk_savedwrite(pte_t pte)
536{
537 /*
538 * Used by Autonuma subsystem to preserve the write bit
539 * while marking the pte PROT_NONE. Only allow this
540 * on PROT_NONE pte
541 */
542 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
543 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
544 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
545}
546
547#define pte_clear_savedwrite pte_clear_savedwrite
548static inline pte_t pte_clear_savedwrite(pte_t pte)
549{
550 /*
551 * Used by KSM subsystem to make a protnone pte readonly.
552 */
553 VM_BUG_ON(!pte_protnone(pte));
554 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
555}
d19469e8
AK		 556#else
557#define pte_clear_savedwrite pte_clear_savedwrite
558static inline pte_t pte_clear_savedwrite(pte_t pte)
559{
560 VM_WARN_ON(1);
561 return __pte(pte_val(pte) & ~_PAGE_WRITE);
562}
13f829a5
AK		 563#endif /* CONFIG_NUMA_BALANCING */
564
565static inline int pte_present(pte_t pte)
566{
66c570f5 567 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
13f829a5 568}
f72a85e3 569
bca7aacf 570#ifdef CONFIG_PPC_MEM_KEYS
f2407ef3 571extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
bca7aacf
RP		 572#else
573static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
574{
575 return true;
576}
577#endif /* CONFIG_PPC_MEM_KEYS */
f2407ef3 578
f72a85e3
AK		 579#define pte_access_permitted pte_access_permitted
580static inline bool pte_access_permitted(pte_t pte, bool write)
581{
582 unsigned long pteval = pte_val(pte);
583 /* Also check for pte_user */
584 unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
585 /*
586 * _PAGE_READ is needed for any access and will be
587 * cleared for PROT_NONE
588 */
589 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
590
591 if (write)
592 need_pte_bits |= _PAGE_WRITE;
593
594 if ((pteval & need_pte_bits) != need_pte_bits)
595 return false;
596
597 if ((pteval & clear_pte_bits) == clear_pte_bits)
598 return false;
bca7aacf
RP		 599
600 return arch_pte_access_permitted(pte_val(pte), write, 0);
f72a85e3
AK		 601}
602
13f829a5
AK		 603/*
604 * Conversion functions: convert a page and protection to a page entry,
605 * and a page entry and page directory to the page they refer to.
606 *
607 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
608 * long for now.
609 */
610static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
611{
612 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
613 pgprot_val(pgprot));
614}
615
616static inline unsigned long pte_pfn(pte_t pte)
617{
618 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
619}
620
621/* Generic modifiers for PTE bits */
622static inline pte_t pte_wrprotect(pte_t pte)
623{
d19469e8
AK		 624 if (unlikely(pte_savedwrite(pte)))
625 return pte_clear_savedwrite(pte);
13f829a5
AK		 626 return __pte(pte_val(pte) & ~_PAGE_WRITE);
627}
628
629static inline pte_t pte_mkclean(pte_t pte)
630{
631 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
632}
633
634static inline pte_t pte_mkold(pte_t pte)
635{
636 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
637}
638
639static inline pte_t pte_mkwrite(pte_t pte)
640{
641 /*
642 * write implies read, hence set both
643 */
644 return __pte(pte_val(pte) | _PAGE_RW);
645}
646
647static inline pte_t pte_mkdirty(pte_t pte)
648{
649 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
650}
651
652static inline pte_t pte_mkyoung(pte_t pte)
653{
654 return __pte(pte_val(pte) | _PAGE_ACCESSED);
655}
656
657static inline pte_t pte_mkspecial(pte_t pte)
658{
659 return __pte(pte_val(pte) | _PAGE_SPECIAL);
660}
661
662static inline pte_t pte_mkhuge(pte_t pte)
663{
664 return pte;
665}
666
ebd31197
OH		 667static inline pte_t pte_mkdevmap(pte_t pte)
668{
669 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
670}
671
c9c98bc5
OH		 672/*
673 * This is potentially called with a pmd as the argument, in which case it's not
674 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
675 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
676 * use in page directory entries (ie. non-ptes).
677 */
ebd31197
OH		 678static inline int pte_devmap(pte_t pte)
679{
c9c98bc5
OH		 680 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
681
682 return (pte_raw(pte) & mask) == mask;
ebd31197
OH		 683}
684
13f829a5
AK		 685static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
686{
687 /* FIXME!! check whether this need to be a conditional */
688 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
689}
690
34fbadd8
AK		 691static inline bool pte_user(pte_t pte)
692{
66c570f5 693 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
34fbadd8
AK		 694}
695
696/* Encode and de-code a swap entry */
697#define MAX_SWAPFILES_CHECK() do { \
698 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
699 /* \
700 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
701 * We filter HPTEFLAGS on set_pte. \
702 */ \
703 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
704 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
705 } while (0)
706/*
707 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
708 */
709#define SWP_TYPE_BITS 5
710#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
711 & ((1UL << SWP_TYPE_BITS) - 1))
712#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
713#define __swp_entry(type, offset) ((swp_entry_t) { \
714 ((type) << _PAGE_BIT_SWAP_TYPE) \
715 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
716/*
717 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
718 * swap type and offset we get from swap and convert that to pte to find a
719 * matching pte in linux page table.
720 * Clear bits not found in swap entries here.
721 */
722#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
723#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
724
725#ifdef CONFIG_MEM_SOFT_DIRTY
726#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
727#else
728#define _PAGE_SWP_SOFT_DIRTY 0UL
729#endif /* CONFIG_MEM_SOFT_DIRTY */
730
731#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
732static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
733{
734 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
735}
66c570f5 736
34fbadd8
AK		 737static inline bool pte_swp_soft_dirty(pte_t pte)
738{
66c570f5 739 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 740}
66c570f5 741
34fbadd8
AK		 742static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
743{
744 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
745}
746#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
747
748static inline bool check_pte_access(unsigned long access, unsigned long ptev)
749{
750 /*
751 * This check for _PAGE_RWX and _PAGE_PRESENT bits
752 */
753 if (access & ~ptev)
754 return false;
755 /*
756 * This check for access to privilege space
757 */
758 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
759 return false;
760
761 return true;
762}
ac94ac79
AK		 763/*
764 * Generic functions with hash/radix callbacks
765 */
766
e4c1112c 767static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
b3603e17 768 pte_t *ptep, pte_t entry,
e4c1112c
AK		 769 unsigned long address,
770 int psize)
ac94ac79
AK		 771{
772 if (radix_enabled())
e4c1112c
AK		 773 return radix__ptep_set_access_flags(vma, ptep, entry,
774 address, psize);
ac94ac79
AK		 775 return hash__ptep_set_access_flags(ptep, entry);
776}
777
778#define __HAVE_ARCH_PTE_SAME
779static inline int pte_same(pte_t pte_a, pte_t pte_b)
780{
781 if (radix_enabled())
782 return radix__pte_same(pte_a, pte_b);
783 return hash__pte_same(pte_a, pte_b);
784}
785
786static inline int pte_none(pte_t pte)
787{
788 if (radix_enabled())
789 return radix__pte_none(pte);
790 return hash__pte_none(pte);
791}
792
793static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
794 pte_t *ptep, pte_t pte, int percpu)
795{
796 if (radix_enabled())
797 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
798 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
799}
34fbadd8 800
13f829a5
AK		 801#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
802
803#define pgprot_noncached pgprot_noncached
804static inline pgprot_t pgprot_noncached(pgprot_t prot)
805{
806 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
807 _PAGE_NON_IDEMPOTENT);
808}
809
810#define pgprot_noncached_wc pgprot_noncached_wc
811static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
812{
813 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
814 _PAGE_TOLERANT);
815}
816
817#define pgprot_cached pgprot_cached
818static inline pgprot_t pgprot_cached(pgprot_t prot)
819{
820 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
821}
822
823#define pgprot_writecombine pgprot_writecombine
824static inline pgprot_t pgprot_writecombine(pgprot_t prot)
825{
826 return pgprot_noncached_wc(prot);
827}
828/*
829 * check a pte mapping have cache inhibited property
830 */
831static inline bool pte_ci(pte_t pte)
832{
833 unsigned long pte_v = pte_val(pte);
834
835 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
836 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
837 return true;
838 return false;
839}
840
f281b5d5
AK		 841static inline void pmd_set(pmd_t *pmdp, unsigned long val)
842{
843 *pmdp = __pmd(val);
844}
845
846static inline void pmd_clear(pmd_t *pmdp)
847{
848 *pmdp = __pmd(0);
849}
850
66c570f5
AK		 851static inline int pmd_none(pmd_t pmd)
852{
853 return !pmd_raw(pmd);
854}
855
856static inline int pmd_present(pmd_t pmd)
857{
858
859 return !pmd_none(pmd);
860}
3dfcb315 861
ac94ac79
AK		 862static inline int pmd_bad(pmd_t pmd)
863{
864 if (radix_enabled())
865 return radix__pmd_bad(pmd);
866 return hash__pmd_bad(pmd);
867}
868
f281b5d5
AK		 869static inline void pud_set(pud_t *pudp, unsigned long val)
870{
871 *pudp = __pud(val);
872}
873
874static inline void pud_clear(pud_t *pudp)
875{
876 *pudp = __pud(0);
877}
878
66c570f5
AK		 879static inline int pud_none(pud_t pud)
880{
881 return !pud_raw(pud);
882}
883
884static inline int pud_present(pud_t pud)
885{
886 return !pud_none(pud);
887}
3dfcb315
AK		 888
889extern struct page *pud_page(pud_t pud);
371352ca 890extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 891static inline pte_t pud_pte(pud_t pud)
892{
66c570f5 893 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 894}
895
896static inline pud_t pte_pud(pte_t pte)
897{
66c570f5 898 return __pud_raw(pte_raw(pte));
3dfcb315
AK		 899}
900#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 901
902static inline int pud_bad(pud_t pud)
903{
904 if (radix_enabled())
905 return radix__pud_bad(pud);
906 return hash__pud_bad(pud);
907}
908
f72a85e3
AK		 909#define pud_access_permitted pud_access_permitted
910static inline bool pud_access_permitted(pud_t pud, bool write)
911{
912 return pte_access_permitted(pud_pte(pud), write);
913}
ac94ac79 914
3dfcb315 915#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 916static inline void pgd_set(pgd_t *pgdp, unsigned long val)
917{
918 *pgdp = __pgd(val);
919}
3dfcb315 920
368ced78
AK		 921static inline void pgd_clear(pgd_t *pgdp)
922{
923 *pgdp = __pgd(0);
924}
925
66c570f5
AK		 926static inline int pgd_none(pgd_t pgd)
927{
928 return !pgd_raw(pgd);
929}
930
931static inline int pgd_present(pgd_t pgd)
932{
933 return !pgd_none(pgd);
934}
368ced78
AK		 935
936static inline pte_t pgd_pte(pgd_t pgd)
937{
66c570f5 938 return __pte_raw(pgd_raw(pgd));
368ced78
AK		 939}
940
941static inline pgd_t pte_pgd(pte_t pte)
942{
66c570f5 943 return __pgd_raw(pte_raw(pte));
368ced78
AK		 944}
945
ac94ac79
AK		 946static inline int pgd_bad(pgd_t pgd)
947{
948 if (radix_enabled())
949 return radix__pgd_bad(pgd);
950 return hash__pgd_bad(pgd);
951}
952
f72a85e3
AK		 953#define pgd_access_permitted pgd_access_permitted
954static inline bool pgd_access_permitted(pgd_t pgd, bool write)
955{
956 return pte_access_permitted(pgd_pte(pgd), write);
957}
958
368ced78
AK		 959extern struct page *pgd_page(pgd_t pgd);
960
aba480e1
AK		 961/* Pointers in the page table tree are physical addresses */
962#define __pgtable_ptr_val(ptr) __pa(ptr)
963
964#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
965#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
966#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
967
968#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
969#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
970#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
971#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
972
3dfcb315
AK		 973/*
974 * Find an entry in a page-table-directory. We combine the address region
975 * (the high order N bits) and the pgd portion of the address.
976 */
3dfcb315
AK		 977
978#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
979
368ced78
AK		 980#define pud_offset(pgdp, addr) \
981 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 982#define pmd_offset(pudp,addr) \
371352ca 983 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 984#define pte_offset_kernel(dir,addr) \
371352ca 985 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 986
987#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
988#define pte_unmap(pte) do { } while(0)
989
990/* to find an entry in a kernel page-table-directory */
991/* This now only contains the vmalloc pages */
992#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 993
994#define pte_ERROR(e) \
995 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
996#define pmd_ERROR(e) \
997 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 998#define pud_ERROR(e) \
999 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 1000#define pgd_ERROR(e) \
1001 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1002
31a14fae
AK		 1003static inline int map_kernel_page(unsigned long ea, unsigned long pa,
1004 unsigned long flags)
7207f436 1005{
d9225ad9
AK		 1006 if (radix_enabled()) {
1007#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1008 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1009 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1010#endif
1011 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
1012 }
31a14fae 1013 return hash__map_kernel_page(ea, pa, flags);
7207f436 1014}
31a14fae
AK		 1015
1016static inline int __meminit vmemmap_create_mapping(unsigned long start,
1017 unsigned long page_size,
1018 unsigned long phys)
7207f436 1019{
d9225ad9
AK		 1020 if (radix_enabled())
1021 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 1022 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 1023}
31a14fae
AK		 1024
1025#ifdef CONFIG_MEMORY_HOTPLUG
1026static inline void vmemmap_remove_mapping(unsigned long start,
1027 unsigned long page_size)
7207f436 1028{
d9225ad9
AK		 1029 if (radix_enabled())
1030 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 1031 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 1032}
31a14fae 1033#endif
3dfcb315
AK		 1034struct page *realmode_pfn_to_page(unsigned long pfn);
1035
3dfcb315
AK		 1036static inline pte_t pmd_pte(pmd_t pmd)
1037{
66c570f5 1038 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 1039}
1040
1041static inline pmd_t pte_pmd(pte_t pte)
1042{
66c570f5 1043 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 1044}
1045
1046static inline pte_t *pmdp_ptep(pmd_t *pmd)
1047{
1048 return (pte_t *)pmd;
1049}
3dfcb315
AK		 1050#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1051#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1052#define pmd_young(pmd) pte_young(pmd_pte(pmd))
1053#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1054#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1055#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 1056#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 1057#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1058#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
c137a275
AK		 1059#define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
1060#define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
7207f436
LD		 1061
1062#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1063#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1064#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1065#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1066#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1067
1ca72129
AK		 1068#ifdef CONFIG_NUMA_BALANCING
1069static inline int pmd_protnone(pmd_t pmd)
1070{
1071 return pte_protnone(pmd_pte(pmd));
1072}
1073#endif /* CONFIG_NUMA_BALANCING */
3dfcb315 1074
3dfcb315 1075#define pmd_write(pmd) pte_write(pmd_pte(pmd))
d19469e8 1076#define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
c137a275 1077#define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
3dfcb315 1078
f72a85e3
AK		 1079#define pmd_access_permitted pmd_access_permitted
1080static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1081{
1082 return pte_access_permitted(pmd_pte(pmd), write);
1083}
1084
6a1ea362
AK		 1085#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1086extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1087extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1088extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1089extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1090 pmd_t *pmdp, pmd_t pmd);
1091extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1092 pmd_t *pmd);
3df33f12
AK		 1093extern int hash__has_transparent_hugepage(void);
1094static inline int has_transparent_hugepage(void)
1095{
bde3eb62
AK		 1096 if (radix_enabled())
1097 return radix__has_transparent_hugepage();
3df33f12
AK		 1098 return hash__has_transparent_hugepage();
1099}
c04a5880 1100#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 1101
3df33f12
AK		 1102static inline unsigned long
1103pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1104 unsigned long clr, unsigned long set)
3dfcb315 1105{
bde3eb62
AK		 1106 if (radix_enabled())
1107 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 1108 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1109}
1110
1111static inline int pmd_large(pmd_t pmd)
1112{
66c570f5 1113 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 1114}
1115
1116static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1117{
1118 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1119}
1120/*
1121 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1122 * the below will work for radix too
1123 */
1124static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1125 unsigned long addr, pmd_t *pmdp)
1126{
1127 unsigned long old;
1128
66c570f5 1129 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 1130 return 0;
1131 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1132 return ((old & _PAGE_ACCESSED) != 0);
1133}
1134
1135#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1136static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1137 pmd_t *pmdp)
1138{
d19469e8 1139 if (__pmd_write((*pmdp)))
52c50ca7
AK		 1140 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1141 else if (unlikely(pmd_savedwrite(*pmdp)))
1142 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
3dfcb315
AK		 1143}
1144
ab624762
AK		 1145static inline int pmd_trans_huge(pmd_t pmd)
1146{
1147 if (radix_enabled())
1148 return radix__pmd_trans_huge(pmd);
1149 return hash__pmd_trans_huge(pmd);
1150}
1151
1152#define __HAVE_ARCH_PMD_SAME
1153static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1154{
1155 if (radix_enabled())
1156 return radix__pmd_same(pmd_a, pmd_b);
1157 return hash__pmd_same(pmd_a, pmd_b);
1158}
1159
3dfcb315
AK		 1160static inline pmd_t pmd_mkhuge(pmd_t pmd)
1161{
ab624762
AK		 1162 if (radix_enabled())
1163 return radix__pmd_mkhuge(pmd);
1164 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 1165}
1166
3dfcb315
AK		 1167#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1168extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1169 unsigned long address, pmd_t *pmdp,
1170 pmd_t entry, int dirty);
1171
3dfcb315
AK		 1172#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1173extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1174 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 1175
1176#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 1177static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1178 unsigned long addr, pmd_t *pmdp)
1179{
bde3eb62
AK		 1180 if (radix_enabled())
1181 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 1182 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1183}
3dfcb315 1184
3df33f12
AK		 1185static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1186 unsigned long address, pmd_t *pmdp)
1187{
bde3eb62
AK		 1188 if (radix_enabled())
1189 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 1190 return hash__pmdp_collapse_flush(vma, address, pmdp);
1191}
3dfcb315
AK		 1192#define pmdp_collapse_flush pmdp_collapse_flush
1193
1194#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 1195static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1196 pmd_t *pmdp, pgtable_t pgtable)
1197{
bde3eb62
AK		 1198 if (radix_enabled())
1199 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 1200 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1201}
1202
3dfcb315 1203#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 1204static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1205 pmd_t *pmdp)
1206{
bde3eb62
AK		 1207 if (radix_enabled())
1208 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 1209 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1210}
3dfcb315
AK		 1211
1212#define __HAVE_ARCH_PMDP_INVALIDATE
8cc931e0
AK		 1213extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1214 pmd_t *pmdp);
3dfcb315
AK		 1215
1216#define pmd_move_must_withdraw pmd_move_must_withdraw
1217struct spinlock;
1218static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1dd38b6c
AK		 1219 struct spinlock *old_pmd_ptl,
1220 struct vm_area_struct *vma)
3dfcb315 1221{
bde3eb62
AK		 1222 if (radix_enabled())
1223 return false;
3dfcb315
AK		 1224 /*
1225 * Archs like ppc64 use pgtable to store per pmd
1226 * specific information. So when we switch the pmd,
1227 * we should also withdraw and deposit the pgtable
1228 */
1229 return true;
1230}
953c66c2
AK		 1231
1232
1233#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1234static inline bool arch_needs_pgtable_deposit(void)
1235{
1236 if (radix_enabled())
1237 return false;
1238 return true;
1239}
fa4531f7 1240extern void serialize_against_pte_lookup(struct mm_struct *mm);
953c66c2 1241
ebd31197
OH		 1242
1243static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1244{
1245 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1246}
1247
1248static inline int pmd_devmap(pmd_t pmd)
1249{
1250 return pte_devmap(pmd_pte(pmd));
1251}
1252
1253static inline int pud_devmap(pud_t pud)
1254{
1255 return 0;
1256}
1257
1258static inline int pgd_devmap(pgd_t pgd)
1259{
1260 return 0;
1261}
6a1ea362 1262#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
ebd31197
OH		 1263
1264static inline const int pud_pfn(pud_t pud)
1265{
1266 /*
1267 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1268 * check so this should never be used. If it grows another user we
1269 * want to know about it.
1270 */
1271 BUILD_BUG();
1272 return 0;
1273}
029d9252 1274
3dfcb315
AK		 1275#endif /* __ASSEMBLY__ */
1276#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)