Commit | Line | Data |
---|---|---|
3dfcb315 AK |
1 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
2 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 AK |
3 | |
4 | /* | |
5 | * Common bits between hash and Radix page table | |
6 | */ | |
7 | #define _PAGE_BIT_SWAP_TYPE 0 | |
8 | ||
9 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
10 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
11 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
12 | #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) | |
13 | #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) | |
14 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ | |
15 | #define _PAGE_SAO 0x00010 /* Strong access order */ | |
16 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ | |
17 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
18 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
19 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
20 | /* | |
21 | * Software bits | |
22 | */ | |
23 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
24 | #define _PAGE_SOFT_DIRTY 0x00200 /* software: software dirty tracking */ | |
25 | #else | |
26 | #define _PAGE_SOFT_DIRTY 0x00000 | |
27 | #endif | |
28 | #define _PAGE_SPECIAL 0x00400 /* software: special page */ | |
29 | ||
30 | ||
31 | #define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */ | |
32 | #define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */ | |
33 | /* | |
34 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
35 | * Instead of fixing all of them, add an alternate define which | |
36 | * maps CI pte mapping. | |
37 | */ | |
38 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
39 | /* | |
40 | * We support 57 bit real address in pte. Clear everything above 57, and | |
41 | * every thing below PAGE_SHIFT; | |
42 | */ | |
43 | #define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK)) | |
44 | /* | |
45 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
46 | * in here, on radix we expect them to be zero. | |
47 | */ | |
48 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
49 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
50 | _PAGE_SOFT_DIRTY) | |
51 | /* | |
52 | * user access blocked by key | |
53 | */ | |
54 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
55 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
56 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ | |
57 | _PAGE_RW | _PAGE_EXEC) | |
58 | /* | |
59 | * No page size encoding in the linux PTE | |
60 | */ | |
61 | #define _PAGE_PSIZE 0 | |
62 | /* | |
63 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
64 | * pgprot changes | |
65 | */ | |
66 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
67 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
68 | _PAGE_SOFT_DIRTY) | |
69 | /* | |
70 | * Mask of bits returned by pte_pgprot() | |
71 | */ | |
72 | #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ | |
73 | H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ | |
74 | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ | |
75 | _PAGE_SOFT_DIRTY) | |
3dfcb315 | 76 | /* |
2e873519 AK |
77 | * We define 2 sets of base prot bits, one for basic pages (ie, |
78 | * cacheable kernel and user pages) and one for non cacheable | |
79 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
80 | * the processor might need it for DMA coherency. | |
3dfcb315 | 81 | */ |
2e873519 AK |
82 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) |
83 | #define _PAGE_BASE (_PAGE_BASE_NC) | |
84 | ||
85 | /* Permission masks used to generate the __P and __S table, | |
86 | * | |
87 | * Note:__pgprot is defined in arch/powerpc/include/asm/page.h | |
88 | * | |
89 | * Write permissions imply read permissions for now (we could make write-only | |
90 | * pages on BookE but we don't bother for now). Execute permission control is | |
91 | * possible on platforms that define _PAGE_EXEC | |
92 | * | |
93 | * Note due to the way vm flags are laid out, the bits are XWR | |
94 | */ | |
95 | #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) | |
96 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) | |
97 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) | |
98 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) | |
99 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
100 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) | |
101 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
102 | ||
103 | #define __P000 PAGE_NONE | |
104 | #define __P001 PAGE_READONLY | |
105 | #define __P010 PAGE_COPY | |
106 | #define __P011 PAGE_COPY | |
107 | #define __P100 PAGE_READONLY_X | |
108 | #define __P101 PAGE_READONLY_X | |
109 | #define __P110 PAGE_COPY_X | |
110 | #define __P111 PAGE_COPY_X | |
111 | ||
112 | #define __S000 PAGE_NONE | |
113 | #define __S001 PAGE_READONLY | |
114 | #define __S010 PAGE_SHARED | |
115 | #define __S011 PAGE_SHARED | |
116 | #define __S100 PAGE_READONLY_X | |
117 | #define __S101 PAGE_READONLY_X | |
118 | #define __S110 PAGE_SHARED_X | |
119 | #define __S111 PAGE_SHARED_X | |
120 | ||
121 | /* Permission masks used for kernel mappings */ | |
122 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
123 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
124 | _PAGE_TOLERANT) | |
125 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
126 | _PAGE_NON_IDEMPOTENT) | |
127 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) | |
128 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
129 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
130 | ||
131 | /* | |
132 | * Protection used for kernel text. We want the debuggers to be able to | |
133 | * set breakpoints anywhere, so don't write protect the kernel text | |
134 | * on platforms where such control is possible. | |
135 | */ | |
136 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ | |
137 | defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) | |
138 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_X | |
139 | #else | |
140 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX | |
141 | #endif | |
142 | ||
143 | /* Make modules code happy. We don't set RO yet */ | |
144 | #define PAGE_KERNEL_EXEC PAGE_KERNEL_X | |
145 | #define PAGE_AGP (PAGE_KERNEL_NC) | |
3dfcb315 | 146 | |
dd1842a2 AK |
147 | #ifndef __ASSEMBLY__ |
148 | /* | |
149 | * page table defines | |
150 | */ | |
151 | extern unsigned long __pte_index_size; | |
152 | extern unsigned long __pmd_index_size; | |
153 | extern unsigned long __pud_index_size; | |
154 | extern unsigned long __pgd_index_size; | |
155 | extern unsigned long __pmd_cache_index; | |
156 | #define PTE_INDEX_SIZE __pte_index_size | |
157 | #define PMD_INDEX_SIZE __pmd_index_size | |
158 | #define PUD_INDEX_SIZE __pud_index_size | |
159 | #define PGD_INDEX_SIZE __pgd_index_size | |
160 | #define PMD_CACHE_INDEX __pmd_cache_index | |
161 | /* | |
162 | * Because of use of pte fragments and THP, size of page table | |
163 | * are not always derived out of index size above. | |
164 | */ | |
165 | extern unsigned long __pte_table_size; | |
166 | extern unsigned long __pmd_table_size; | |
167 | extern unsigned long __pud_table_size; | |
168 | extern unsigned long __pgd_table_size; | |
169 | #define PTE_TABLE_SIZE __pte_table_size | |
170 | #define PMD_TABLE_SIZE __pmd_table_size | |
171 | #define PUD_TABLE_SIZE __pud_table_size | |
172 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
173 | |
174 | extern unsigned long __pmd_val_bits; | |
175 | extern unsigned long __pud_val_bits; | |
176 | extern unsigned long __pgd_val_bits; | |
177 | #define PMD_VAL_BITS __pmd_val_bits | |
178 | #define PUD_VAL_BITS __pud_val_bits | |
179 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
180 | |
181 | extern unsigned long __pte_frag_nr; | |
182 | #define PTE_FRAG_NR __pte_frag_nr | |
183 | extern unsigned long __pte_frag_size_shift; | |
184 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
185 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 AK |
186 | /* |
187 | * Pgtable size used by swapper, init in asm code | |
dd1842a2 | 188 | */ |
a2f41eb9 | 189 | #define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE) |
dd1842a2 AK |
190 | |
191 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
192 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
193 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
194 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
195 | ||
196 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
197 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
198 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
199 | #define PMD_MASK (~(PMD_SIZE-1)) | |
200 | ||
201 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
202 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
203 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
204 | #define PUD_MASK (~(PUD_SIZE-1)) | |
205 | ||
206 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
207 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
208 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
209 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
210 | ||
211 | /* Bits to mask out from a PMD to get to the PTE page */ | |
212 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
213 | /* Bits to mask out from a PUD to get to the PMD page */ | |
214 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
215 | /* Bits to mask out from a PGD to get to the PUD page */ | |
216 | #define PGD_MASKED_BITS 0xc0000000000000ffUL | |
d6a9996e AK |
217 | |
218 | extern unsigned long __vmalloc_start; | |
219 | extern unsigned long __vmalloc_end; | |
220 | #define VMALLOC_START __vmalloc_start | |
221 | #define VMALLOC_END __vmalloc_end | |
222 | ||
223 | extern unsigned long __kernel_virt_start; | |
224 | extern unsigned long __kernel_virt_size; | |
225 | #define KERN_VIRT_START __kernel_virt_start | |
226 | #define KERN_VIRT_SIZE __kernel_virt_size | |
227 | extern struct page *vmemmap; | |
228 | extern unsigned long ioremap_bot; | |
dd1842a2 AK |
229 | #endif /* __ASSEMBLY__ */ |
230 | ||
ab537dca | 231 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 232 | #include <asm/book3s/64/radix.h> |
a9252aae AK |
233 | |
234 | #ifdef CONFIG_PPC_64K_PAGES | |
235 | #include <asm/book3s/64/pgtable-64k.h> | |
236 | #else | |
237 | #include <asm/book3s/64/pgtable-4k.h> | |
238 | #endif | |
239 | ||
3dfcb315 | 240 | #include <asm/barrier.h> |
3dfcb315 AK |
241 | /* |
242 | * The second half of the kernel virtual space is used for IO mappings, | |
243 | * it's itself carved into the PIO region (ISA and PHB IO space) and | |
244 | * the ioremap space | |
245 | * | |
246 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
247 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
248 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
249 | */ | |
250 | #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) | |
251 | #define FULL_IO_SIZE 0x80000000ul | |
252 | #define ISA_IO_BASE (KERN_IO_START) | |
253 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
254 | #define PHB_IO_BASE (ISA_IO_END) | |
255 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
256 | #define IOREMAP_BASE (PHB_IO_END) | |
257 | #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) | |
258 | ||
b0412ea9 | 259 | /* Advertise special mapping type for AGP */ |
b0412ea9 AK |
260 | #define HAVE_PAGE_AGP |
261 | ||
262 | /* Advertise support for _PAGE_SPECIAL */ | |
263 | #define __HAVE_ARCH_PTE_SPECIAL | |
264 | ||
3dfcb315 AK |
265 | #ifndef __ASSEMBLY__ |
266 | ||
267 | /* | |
268 | * This is the default implementation of various PTE accessors, it's | |
269 | * used in all cases except Book3S with 64K pages where we have a | |
270 | * concept of sub-pages | |
271 | */ | |
272 | #ifndef __real_pte | |
273 | ||
3dfcb315 AK |
274 | #define __real_pte(e,p) ((real_pte_t){(e)}) |
275 | #define __rpte_to_pte(r) ((r).pte) | |
945537df | 276 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
277 | |
278 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
279 | do { \ | |
280 | index = 0; \ | |
281 | shift = mmu_psize_defs[psize].shift; \ | |
282 | ||
283 | #define pte_iterate_hashed_end() } while(0) | |
284 | ||
285 | /* | |
286 | * We expect this to be called only for user addresses or kernel virtual | |
287 | * addresses other than the linear mapping. | |
288 | */ | |
289 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
290 | ||
291 | #endif /* __real_pte */ | |
292 | ||
ac94ac79 AK |
293 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
294 | pte_t *ptep, unsigned long clr, | |
295 | unsigned long set, int huge) | |
296 | { | |
297 | if (radix_enabled()) | |
298 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
299 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
300 | } | |
13f829a5 AK |
301 | /* |
302 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
303 | * We currently remove entries from the hashtable regardless of whether | |
304 | * the entry was young or dirty. | |
305 | * | |
306 | * We should be more intelligent about this but for the moment we override | |
307 | * these functions and force a tlb flush unconditionally | |
308 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
309 | * function for both hash and radix. | |
310 | */ | |
311 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
312 | unsigned long addr, pte_t *ptep) | |
313 | { | |
314 | unsigned long old; | |
315 | ||
316 | if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
317 | return 0; | |
318 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
319 | return (old & _PAGE_ACCESSED) != 0; | |
320 | } | |
321 | ||
322 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
323 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
324 | ({ \ | |
325 | int __r; \ | |
326 | __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ | |
327 | __r; \ | |
328 | }) | |
329 | ||
330 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
331 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
332 | pte_t *ptep) | |
333 | { | |
334 | ||
335 | if ((pte_val(*ptep) & _PAGE_WRITE) == 0) | |
336 | return; | |
337 | ||
338 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); | |
339 | } | |
340 | ||
341 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, | |
342 | unsigned long addr, pte_t *ptep) | |
343 | { | |
344 | if ((pte_val(*ptep) & _PAGE_WRITE) == 0) | |
345 | return; | |
346 | ||
347 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); | |
348 | } | |
349 | ||
350 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
351 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
352 | unsigned long addr, pte_t *ptep) | |
353 | { | |
354 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
355 | return __pte(old); | |
356 | } | |
357 | ||
358 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
359 | pte_t * ptep) | |
360 | { | |
361 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
362 | } | |
363 | static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);} | |
364 | static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } | |
365 | static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } | |
366 | static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } | |
367 | static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } | |
368 | ||
369 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
370 | static inline bool pte_soft_dirty(pte_t pte) | |
371 | { | |
372 | return !!(pte_val(pte) & _PAGE_SOFT_DIRTY); | |
373 | } | |
374 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
375 | { | |
376 | return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); | |
377 | } | |
378 | ||
379 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
380 | { | |
381 | return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); | |
382 | } | |
383 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
384 | ||
385 | #ifdef CONFIG_NUMA_BALANCING | |
386 | /* | |
387 | * These work without NUMA balancing but the kernel does not care. See the | |
388 | * comment in include/asm-generic/pgtable.h . On powerpc, this will only | |
389 | * work for user pages and always return true for kernel pages. | |
390 | */ | |
391 | static inline int pte_protnone(pte_t pte) | |
392 | { | |
393 | return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) == | |
394 | (_PAGE_PRESENT | _PAGE_PRIVILEGED); | |
395 | } | |
396 | #endif /* CONFIG_NUMA_BALANCING */ | |
397 | ||
398 | static inline int pte_present(pte_t pte) | |
399 | { | |
400 | return !!(pte_val(pte) & _PAGE_PRESENT); | |
401 | } | |
402 | /* | |
403 | * Conversion functions: convert a page and protection to a page entry, | |
404 | * and a page entry and page directory to the page they refer to. | |
405 | * | |
406 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
407 | * long for now. | |
408 | */ | |
409 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
410 | { | |
411 | return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | | |
412 | pgprot_val(pgprot)); | |
413 | } | |
414 | ||
415 | static inline unsigned long pte_pfn(pte_t pte) | |
416 | { | |
417 | return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; | |
418 | } | |
419 | ||
420 | /* Generic modifiers for PTE bits */ | |
421 | static inline pte_t pte_wrprotect(pte_t pte) | |
422 | { | |
423 | return __pte(pte_val(pte) & ~_PAGE_WRITE); | |
424 | } | |
425 | ||
426 | static inline pte_t pte_mkclean(pte_t pte) | |
427 | { | |
428 | return __pte(pte_val(pte) & ~_PAGE_DIRTY); | |
429 | } | |
430 | ||
431 | static inline pte_t pte_mkold(pte_t pte) | |
432 | { | |
433 | return __pte(pte_val(pte) & ~_PAGE_ACCESSED); | |
434 | } | |
435 | ||
436 | static inline pte_t pte_mkwrite(pte_t pte) | |
437 | { | |
438 | /* | |
439 | * write implies read, hence set both | |
440 | */ | |
441 | return __pte(pte_val(pte) | _PAGE_RW); | |
442 | } | |
443 | ||
444 | static inline pte_t pte_mkdirty(pte_t pte) | |
445 | { | |
446 | return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); | |
447 | } | |
448 | ||
449 | static inline pte_t pte_mkyoung(pte_t pte) | |
450 | { | |
451 | return __pte(pte_val(pte) | _PAGE_ACCESSED); | |
452 | } | |
453 | ||
454 | static inline pte_t pte_mkspecial(pte_t pte) | |
455 | { | |
456 | return __pte(pte_val(pte) | _PAGE_SPECIAL); | |
457 | } | |
458 | ||
459 | static inline pte_t pte_mkhuge(pte_t pte) | |
460 | { | |
461 | return pte; | |
462 | } | |
463 | ||
464 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |
465 | { | |
466 | /* FIXME!! check whether this need to be a conditional */ | |
467 | return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); | |
468 | } | |
469 | ||
34fbadd8 AK |
470 | static inline bool pte_user(pte_t pte) |
471 | { | |
472 | return !(pte_val(pte) & _PAGE_PRIVILEGED); | |
473 | } | |
474 | ||
475 | /* Encode and de-code a swap entry */ | |
476 | #define MAX_SWAPFILES_CHECK() do { \ | |
477 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
478 | /* \ | |
479 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
480 | * We filter HPTEFLAGS on set_pte. \ | |
481 | */ \ | |
482 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ | |
483 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ | |
484 | } while (0) | |
485 | /* | |
486 | * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; | |
487 | */ | |
488 | #define SWP_TYPE_BITS 5 | |
489 | #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ | |
490 | & ((1UL << SWP_TYPE_BITS) - 1)) | |
491 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) | |
492 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
493 | ((type) << _PAGE_BIT_SWAP_TYPE) \ | |
494 | | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) | |
495 | /* | |
496 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
497 | * swap type and offset we get from swap and convert that to pte to find a | |
498 | * matching pte in linux page table. | |
499 | * Clear bits not found in swap entries here. | |
500 | */ | |
501 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
502 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
503 | ||
504 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
505 | #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) | |
506 | #else | |
507 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
508 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
509 | ||
510 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
511 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
512 | { | |
513 | return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); | |
514 | } | |
515 | static inline bool pte_swp_soft_dirty(pte_t pte) | |
516 | { | |
517 | return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY); | |
518 | } | |
519 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) | |
520 | { | |
521 | return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); | |
522 | } | |
523 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
524 | ||
525 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) | |
526 | { | |
527 | /* | |
528 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
529 | */ | |
530 | if (access & ~ptev) | |
531 | return false; | |
532 | /* | |
533 | * This check for access to privilege space | |
534 | */ | |
535 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
536 | return false; | |
537 | ||
538 | return true; | |
539 | } | |
ac94ac79 AK |
540 | /* |
541 | * Generic functions with hash/radix callbacks | |
542 | */ | |
543 | ||
544 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) | |
545 | { | |
546 | if (radix_enabled()) | |
547 | return radix__ptep_set_access_flags(ptep, entry); | |
548 | return hash__ptep_set_access_flags(ptep, entry); | |
549 | } | |
550 | ||
551 | #define __HAVE_ARCH_PTE_SAME | |
552 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
553 | { | |
554 | if (radix_enabled()) | |
555 | return radix__pte_same(pte_a, pte_b); | |
556 | return hash__pte_same(pte_a, pte_b); | |
557 | } | |
558 | ||
559 | static inline int pte_none(pte_t pte) | |
560 | { | |
561 | if (radix_enabled()) | |
562 | return radix__pte_none(pte); | |
563 | return hash__pte_none(pte); | |
564 | } | |
565 | ||
566 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
567 | pte_t *ptep, pte_t pte, int percpu) | |
568 | { | |
569 | if (radix_enabled()) | |
570 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
571 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
572 | } | |
34fbadd8 | 573 | |
13f829a5 AK |
574 | #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
575 | ||
576 | #define pgprot_noncached pgprot_noncached | |
577 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
578 | { | |
579 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
580 | _PAGE_NON_IDEMPOTENT); | |
581 | } | |
582 | ||
583 | #define pgprot_noncached_wc pgprot_noncached_wc | |
584 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
585 | { | |
586 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
587 | _PAGE_TOLERANT); | |
588 | } | |
589 | ||
590 | #define pgprot_cached pgprot_cached | |
591 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
592 | { | |
593 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
594 | } | |
595 | ||
596 | #define pgprot_writecombine pgprot_writecombine | |
597 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
598 | { | |
599 | return pgprot_noncached_wc(prot); | |
600 | } | |
601 | /* | |
602 | * check a pte mapping have cache inhibited property | |
603 | */ | |
604 | static inline bool pte_ci(pte_t pte) | |
605 | { | |
606 | unsigned long pte_v = pte_val(pte); | |
607 | ||
608 | if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || | |
609 | ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) | |
610 | return true; | |
611 | return false; | |
612 | } | |
613 | ||
f281b5d5 AK |
614 | static inline void pmd_set(pmd_t *pmdp, unsigned long val) |
615 | { | |
616 | *pmdp = __pmd(val); | |
617 | } | |
618 | ||
619 | static inline void pmd_clear(pmd_t *pmdp) | |
620 | { | |
621 | *pmdp = __pmd(0); | |
622 | } | |
623 | ||
3dfcb315 | 624 | #define pmd_none(pmd) (!pmd_val(pmd)) |
3dfcb315 | 625 | #define pmd_present(pmd) (!pmd_none(pmd)) |
3dfcb315 | 626 | |
ac94ac79 AK |
627 | static inline int pmd_bad(pmd_t pmd) |
628 | { | |
629 | if (radix_enabled()) | |
630 | return radix__pmd_bad(pmd); | |
631 | return hash__pmd_bad(pmd); | |
632 | } | |
633 | ||
f281b5d5 AK |
634 | static inline void pud_set(pud_t *pudp, unsigned long val) |
635 | { | |
636 | *pudp = __pud(val); | |
637 | } | |
638 | ||
639 | static inline void pud_clear(pud_t *pudp) | |
640 | { | |
641 | *pudp = __pud(0); | |
642 | } | |
643 | ||
3dfcb315 | 644 | #define pud_none(pud) (!pud_val(pud)) |
3dfcb315 | 645 | #define pud_present(pud) (pud_val(pud) != 0) |
3dfcb315 AK |
646 | |
647 | extern struct page *pud_page(pud_t pud); | |
371352ca | 648 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
649 | static inline pte_t pud_pte(pud_t pud) |
650 | { | |
651 | return __pte(pud_val(pud)); | |
652 | } | |
653 | ||
654 | static inline pud_t pte_pud(pte_t pte) | |
655 | { | |
656 | return __pud(pte_val(pte)); | |
657 | } | |
658 | #define pud_write(pud) pte_write(pud_pte(pud)) | |
ac94ac79 AK |
659 | |
660 | static inline int pud_bad(pud_t pud) | |
661 | { | |
662 | if (radix_enabled()) | |
663 | return radix__pud_bad(pud); | |
664 | return hash__pud_bad(pud); | |
665 | } | |
666 | ||
667 | ||
3dfcb315 | 668 | #define pgd_write(pgd) pte_write(pgd_pte(pgd)) |
f281b5d5 AK |
669 | static inline void pgd_set(pgd_t *pgdp, unsigned long val) |
670 | { | |
671 | *pgdp = __pgd(val); | |
672 | } | |
3dfcb315 | 673 | |
368ced78 AK |
674 | static inline void pgd_clear(pgd_t *pgdp) |
675 | { | |
676 | *pgdp = __pgd(0); | |
677 | } | |
678 | ||
679 | #define pgd_none(pgd) (!pgd_val(pgd)) | |
680 | #define pgd_present(pgd) (!pgd_none(pgd)) | |
681 | ||
682 | static inline pte_t pgd_pte(pgd_t pgd) | |
683 | { | |
684 | return __pte(pgd_val(pgd)); | |
685 | } | |
686 | ||
687 | static inline pgd_t pte_pgd(pte_t pte) | |
688 | { | |
689 | return __pgd(pte_val(pte)); | |
690 | } | |
691 | ||
ac94ac79 AK |
692 | static inline int pgd_bad(pgd_t pgd) |
693 | { | |
694 | if (radix_enabled()) | |
695 | return radix__pgd_bad(pgd); | |
696 | return hash__pgd_bad(pgd); | |
697 | } | |
698 | ||
368ced78 AK |
699 | extern struct page *pgd_page(pgd_t pgd); |
700 | ||
aba480e1 AK |
701 | /* Pointers in the page table tree are physical addresses */ |
702 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
703 | ||
704 | #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) | |
705 | #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) | |
706 | #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) | |
707 | ||
708 | #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) | |
709 | #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) | |
710 | #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) | |
711 | #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) | |
712 | ||
3dfcb315 AK |
713 | /* |
714 | * Find an entry in a page-table-directory. We combine the address region | |
715 | * (the high order N bits) and the pgd portion of the address. | |
716 | */ | |
3dfcb315 AK |
717 | |
718 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
719 | ||
368ced78 AK |
720 | #define pud_offset(pgdp, addr) \ |
721 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) | |
3dfcb315 | 722 | #define pmd_offset(pudp,addr) \ |
371352ca | 723 | (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) |
3dfcb315 | 724 | #define pte_offset_kernel(dir,addr) \ |
371352ca | 725 | (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) |
3dfcb315 AK |
726 | |
727 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
728 | #define pte_unmap(pte) do { } while(0) | |
729 | ||
730 | /* to find an entry in a kernel page-table-directory */ | |
731 | /* This now only contains the vmalloc pages */ | |
732 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
3dfcb315 AK |
733 | |
734 | #define pte_ERROR(e) \ | |
735 | pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | |
736 | #define pmd_ERROR(e) \ | |
737 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
738 | #define pud_ERROR(e) \ |
739 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
740 | #define pgd_ERROR(e) \ |
741 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
742 | ||
3dfcb315 AK |
743 | void pgtable_cache_add(unsigned shift, void (*ctor)(void *)); |
744 | void pgtable_cache_init(void); | |
3dfcb315 | 745 | |
31a14fae AK |
746 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, |
747 | unsigned long flags) | |
748 | { | |
d9225ad9 AK |
749 | if (radix_enabled()) { |
750 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
751 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
752 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
753 | #endif | |
754 | return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); | |
755 | } | |
31a14fae AK |
756 | return hash__map_kernel_page(ea, pa, flags); |
757 | } | |
758 | ||
759 | static inline int __meminit vmemmap_create_mapping(unsigned long start, | |
760 | unsigned long page_size, | |
761 | unsigned long phys) | |
762 | { | |
d9225ad9 AK |
763 | if (radix_enabled()) |
764 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae AK |
765 | return hash__vmemmap_create_mapping(start, page_size, phys); |
766 | } | |
767 | ||
768 | #ifdef CONFIG_MEMORY_HOTPLUG | |
769 | static inline void vmemmap_remove_mapping(unsigned long start, | |
770 | unsigned long page_size) | |
771 | { | |
d9225ad9 AK |
772 | if (radix_enabled()) |
773 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae AK |
774 | return hash__vmemmap_remove_mapping(start, page_size); |
775 | } | |
776 | #endif | |
3dfcb315 AK |
777 | struct page *realmode_pfn_to_page(unsigned long pfn); |
778 | ||
3dfcb315 AK |
779 | static inline pte_t pmd_pte(pmd_t pmd) |
780 | { | |
781 | return __pte(pmd_val(pmd)); | |
782 | } | |
783 | ||
784 | static inline pmd_t pte_pmd(pte_t pte) | |
785 | { | |
786 | return __pmd(pte_val(pte)); | |
787 | } | |
788 | ||
789 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
790 | { | |
791 | return (pte_t *)pmd; | |
792 | } | |
3dfcb315 AK |
793 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
794 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
795 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
796 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
797 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
798 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 799 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 AK |
800 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
801 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
7207f436 LD |
802 | |
803 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
804 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
805 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
806 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
807 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
808 | ||
1ca72129 AK |
809 | #ifdef CONFIG_NUMA_BALANCING |
810 | static inline int pmd_protnone(pmd_t pmd) | |
811 | { | |
812 | return pte_protnone(pmd_pte(pmd)); | |
813 | } | |
814 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 AK |
815 | |
816 | #define __HAVE_ARCH_PMD_WRITE | |
817 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) | |
818 | ||
6a1ea362 AK |
819 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
820 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
821 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); | |
822 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
823 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
824 | pmd_t *pmdp, pmd_t pmd); | |
825 | extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, | |
826 | pmd_t *pmd); | |
3df33f12 AK |
827 | extern int hash__has_transparent_hugepage(void); |
828 | static inline int has_transparent_hugepage(void) | |
829 | { | |
bde3eb62 AK |
830 | if (radix_enabled()) |
831 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
832 | return hash__has_transparent_hugepage(); |
833 | } | |
6a1ea362 | 834 | |
3df33f12 AK |
835 | static inline unsigned long |
836 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
837 | unsigned long clr, unsigned long set) | |
3dfcb315 | 838 | { |
bde3eb62 AK |
839 | if (radix_enabled()) |
840 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
841 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
842 | } | |
843 | ||
844 | static inline int pmd_large(pmd_t pmd) | |
845 | { | |
846 | return !!(pmd_val(pmd) & _PAGE_PTE); | |
847 | } | |
848 | ||
849 | static inline pmd_t pmd_mknotpresent(pmd_t pmd) | |
850 | { | |
851 | return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); | |
852 | } | |
853 | /* | |
854 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
855 | * the below will work for radix too | |
856 | */ | |
857 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
858 | unsigned long addr, pmd_t *pmdp) | |
859 | { | |
860 | unsigned long old; | |
861 | ||
862 | if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
863 | return 0; | |
864 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
865 | return ((old & _PAGE_ACCESSED) != 0); | |
866 | } | |
867 | ||
868 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
869 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
870 | pmd_t *pmdp) | |
871 | { | |
872 | ||
873 | if ((pmd_val(*pmdp) & _PAGE_WRITE) == 0) | |
874 | return; | |
875 | ||
876 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); | |
3dfcb315 AK |
877 | } |
878 | ||
3dfcb315 AK |
879 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
880 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
881 | unsigned long address, pmd_t *pmdp, | |
882 | pmd_t entry, int dirty); | |
883 | ||
3dfcb315 AK |
884 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
885 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
886 | unsigned long address, pmd_t *pmdp); | |
3dfcb315 AK |
887 | |
888 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
889 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
890 | unsigned long addr, pmd_t *pmdp) | |
891 | { | |
bde3eb62 AK |
892 | if (radix_enabled()) |
893 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
894 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
895 | } | |
3dfcb315 | 896 | |
3df33f12 AK |
897 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
898 | unsigned long address, pmd_t *pmdp) | |
899 | { | |
bde3eb62 AK |
900 | if (radix_enabled()) |
901 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
902 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
903 | } | |
3dfcb315 AK |
904 | #define pmdp_collapse_flush pmdp_collapse_flush |
905 | ||
906 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
3df33f12 AK |
907 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
908 | pmd_t *pmdp, pgtable_t pgtable) | |
909 | { | |
bde3eb62 AK |
910 | if (radix_enabled()) |
911 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
912 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
913 | } | |
914 | ||
3dfcb315 | 915 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
916 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
917 | pmd_t *pmdp) | |
918 | { | |
bde3eb62 AK |
919 | if (radix_enabled()) |
920 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
921 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
922 | } | |
3dfcb315 AK |
923 | |
924 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
925 | extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, | |
926 | pmd_t *pmdp); | |
927 | ||
c777e2a8 | 928 | #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE |
3df33f12 AK |
929 | static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, |
930 | unsigned long address, pmd_t *pmdp) | |
931 | { | |
bde3eb62 AK |
932 | if (radix_enabled()) |
933 | return radix__pmdp_huge_split_prepare(vma, address, pmdp); | |
3df33f12 AK |
934 | return hash__pmdp_huge_split_prepare(vma, address, pmdp); |
935 | } | |
c777e2a8 | 936 | |
3dfcb315 AK |
937 | #define pmd_move_must_withdraw pmd_move_must_withdraw |
938 | struct spinlock; | |
939 | static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, | |
940 | struct spinlock *old_pmd_ptl) | |
941 | { | |
bde3eb62 AK |
942 | if (radix_enabled()) |
943 | return false; | |
3dfcb315 AK |
944 | /* |
945 | * Archs like ppc64 use pgtable to store per pmd | |
946 | * specific information. So when we switch the pmd, | |
947 | * we should also withdraw and deposit the pgtable | |
948 | */ | |
949 | return true; | |
950 | } | |
6a1ea362 | 951 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
3dfcb315 AK |
952 | #endif /* __ASSEMBLY__ */ |
953 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |