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powerpc: Program HPTE key protection bits
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
3dfcb315
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519 4
9849a569
KS		 5#include <asm-generic/5level-fixup.h>
6
c137a275
AK		 7#ifndef __ASSEMBLY__
8#include <linux/mmdebug.h>
ebd31197 9#include <linux/bug.h>
c137a275 10#endif
9849a569 11
2e873519
AK		 12/*
13 * Common bits between hash and Radix page table
14 */
15#define _PAGE_BIT_SWAP_TYPE 0
16
35175033 17#define _PAGE_NA 0
6b8cb66a 18#define _PAGE_RO 0
812fadcb 19#define _PAGE_USER 0
6b8cb66a 20
2e873519
AK		 21#define _PAGE_EXEC 0x00001 /* execute permission */
22#define _PAGE_WRITE 0x00002 /* write access allowed */
23#define _PAGE_READ 0x00004 /* read access allowed */
24#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
25#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
26#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
27#define _PAGE_SAO 0x00010 /* Strong access order */
28#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
29#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
30#define _PAGE_DIRTY 0x00080 /* C: page changed */
31#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 32/*
2e873519 33 * Software bits
3dfcb315 34 */
69dfbaeb
AK		 35#define _RPAGE_SW0 0x2000000000000000UL
36#define _RPAGE_SW1 0x00800
37#define _RPAGE_SW2 0x00400
38#define _RPAGE_SW3 0x00200
049d567a
AK		 39#define _RPAGE_RSV1 0x1000000000000000UL
40#define _RPAGE_RSV2 0x0800000000000000UL
41#define _RPAGE_RSV3 0x0400000000000000UL
42#define _RPAGE_RSV4 0x0200000000000000UL
eb95d016 43#define _RPAGE_RSV5 0x00040UL
6aa59f51
AK		 44
45#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
46#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
47
48/*
49 * Top and bottom bits of RPN which can be used by hash
50 * translation mode, because we expect them to be zero
51 * otherwise.
52 */
32789d38
AK		 53#define _RPAGE_RPN0 0x01000
54#define _RPAGE_RPN1 0x02000
6aa59f51
AK		 55#define _RPAGE_RPN44 0x0100000000000000UL
56#define _RPAGE_RPN43 0x0080000000000000UL
57#define _RPAGE_RPN42 0x0040000000000000UL
58#define _RPAGE_RPN41 0x0020000000000000UL
049d567a 59
2f18d533
AK		 60/* Max physical address bit as per radix table */
61#define _RPAGE_PA_MAX 57
62
eb95d016
RP		 63#ifdef CONFIG_PPC_MEM_KEYS
64#ifdef CONFIG_PPC_64K_PAGES
65#define H_PTE_PKEY_BIT0 _RPAGE_RSV1
66#define H_PTE_PKEY_BIT1 _RPAGE_RSV2
67#else /* CONFIG_PPC_64K_PAGES */
68#define H_PTE_PKEY_BIT0 0 /* _RPAGE_RSV1 is not available */
69#define H_PTE_PKEY_BIT1 0 /* _RPAGE_RSV2 is not available */
70#endif /* CONFIG_PPC_64K_PAGES */
71#define H_PTE_PKEY_BIT2 _RPAGE_RSV3
72#define H_PTE_PKEY_BIT3 _RPAGE_RSV4
73#define H_PTE_PKEY_BIT4 _RPAGE_RSV5
74#else /* CONFIG_PPC_MEM_KEYS */
75#define H_PTE_PKEY_BIT0 0
76#define H_PTE_PKEY_BIT1 0
77#define H_PTE_PKEY_BIT2 0
78#define H_PTE_PKEY_BIT3 0
79#define H_PTE_PKEY_BIT4 0
80#endif /* CONFIG_PPC_MEM_KEYS */
81
2f18d533
AK		 82/*
83 * Max physical address bit we will use for now.
84 *
85 * This is mostly a hardware limitation and for now Power9 has
86 * a 51 bit limit.
87 *
88 * This is different from the number of physical bit required to address
89 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
90 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
91 * number of sections we can support (SECTIONS_SHIFT).
92 *
93 * This is different from Radix page table limitation above and
94 * should always be less than that. The limit is done such that
95 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
96 * for hash linux page table specific bits.
97 *
98 * In order to be compatible with future hardware generations we keep
99 * some offsets and limit this for now to 53
100 */
101#define _PAGE_PA_MAX 53
102
69dfbaeb 103#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
69dfbaeb 104#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
ebd31197
OH		 105#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
106#define __HAVE_ARCH_PTE_DEVMAP
107
2e873519
AK		 108/*
109 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
110 * Instead of fixing all of them, add an alternate define which
111 * maps CI pte mapping.
112 */
113#define _PAGE_NO_CACHE _PAGE_TOLERANT
114/*
2f18d533
AK		 115 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
116 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
117 * and every thing below PAGE_SHIFT;
2e873519 118 */
2f18d533 119#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
2e873519
AK		 120/*
121 * set of bits not changed in pmd_modify. Even though we have hash specific bits
122 * in here, on radix we expect them to be zero.
123 */
124#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
125 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
126 _PAGE_SOFT_DIRTY)
127/*
128 * user access blocked by key
129 */
130#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
131#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
132#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
133 _PAGE_RW | _PAGE_EXEC)
134/*
135 * No page size encoding in the linux PTE
136 */
137#define _PAGE_PSIZE 0
138/*
139 * _PAGE_CHG_MASK masks of bits that are to be preserved across
140 * pgprot changes
141 */
142#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
143 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
144 _PAGE_SOFT_DIRTY)
eb95d016
RP		 145
146#define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \
147 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4)
2e873519
AK		 148/*
149 * Mask of bits returned by pte_pgprot()
150 */
151#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
152 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
153 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
eb95d016 154 _PAGE_SOFT_DIRTY | H_PTE_PKEY)
3dfcb315 155/*
2e873519
AK		 156 * We define 2 sets of base prot bits, one for basic pages (ie,
157 * cacheable kernel and user pages) and one for non cacheable
158 * pages. We always set _PAGE_COHERENT when SMP is enabled or
159 * the processor might need it for DMA coherency.
3dfcb315 160 */
2e873519
AK		 161#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
162#define _PAGE_BASE (_PAGE_BASE_NC)
163
164/* Permission masks used to generate the __P and __S table,
165 *
166 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
167 *
168 * Write permissions imply read permissions for now (we could make write-only
169 * pages on BookE but we don't bother for now). Execute permission control is
170 * possible on platforms that define _PAGE_EXEC
171 *
172 * Note due to the way vm flags are laid out, the bits are XWR
173 */
174#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
175#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
176#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
177#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
178#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
179#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
180#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
181
182#define __P000 PAGE_NONE
183#define __P001 PAGE_READONLY
184#define __P010 PAGE_COPY
185#define __P011 PAGE_COPY
186#define __P100 PAGE_READONLY_X
187#define __P101 PAGE_READONLY_X
188#define __P110 PAGE_COPY_X
189#define __P111 PAGE_COPY_X
190
191#define __S000 PAGE_NONE
192#define __S001 PAGE_READONLY
193#define __S010 PAGE_SHARED
194#define __S011 PAGE_SHARED
195#define __S100 PAGE_READONLY_X
196#define __S101 PAGE_READONLY_X
197#define __S110 PAGE_SHARED_X
198#define __S111 PAGE_SHARED_X
199
200/* Permission masks used for kernel mappings */
201#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
202#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
203 _PAGE_TOLERANT)
204#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
205 _PAGE_NON_IDEMPOTENT)
206#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
207#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
208#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
209
210/*
211 * Protection used for kernel text. We want the debuggers to be able to
212 * set breakpoints anywhere, so don't write protect the kernel text
213 * on platforms where such control is possible.
214 */
215#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
216 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
217#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
218#else
219#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
220#endif
221
222/* Make modules code happy. We don't set RO yet */
223#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
224#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 225
dd1842a2
AK		 226#ifndef __ASSEMBLY__
227/*
228 * page table defines
229 */
230extern unsigned long __pte_index_size;
231extern unsigned long __pmd_index_size;
232extern unsigned long __pud_index_size;
233extern unsigned long __pgd_index_size;
234extern unsigned long __pmd_cache_index;
235#define PTE_INDEX_SIZE __pte_index_size
236#define PMD_INDEX_SIZE __pmd_index_size
237#define PUD_INDEX_SIZE __pud_index_size
238#define PGD_INDEX_SIZE __pgd_index_size
239#define PMD_CACHE_INDEX __pmd_cache_index
240/*
241 * Because of use of pte fragments and THP, size of page table
242 * are not always derived out of index size above.
243 */
244extern unsigned long __pte_table_size;
245extern unsigned long __pmd_table_size;
246extern unsigned long __pud_table_size;
247extern unsigned long __pgd_table_size;
248#define PTE_TABLE_SIZE __pte_table_size
249#define PMD_TABLE_SIZE __pmd_table_size
250#define PUD_TABLE_SIZE __pud_table_size
251#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 252
253extern unsigned long __pmd_val_bits;
254extern unsigned long __pud_val_bits;
255extern unsigned long __pgd_val_bits;
256#define PMD_VAL_BITS __pmd_val_bits
257#define PUD_VAL_BITS __pud_val_bits
258#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 259
260extern unsigned long __pte_frag_nr;
261#define PTE_FRAG_NR __pte_frag_nr
262extern unsigned long __pte_frag_size_shift;
263#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
264#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2
AK		 265
266#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
267#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
268#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
269#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
270
271/* PMD_SHIFT determines what a second-level page table entry can map */
272#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
273#define PMD_SIZE (1UL << PMD_SHIFT)
274#define PMD_MASK (~(PMD_SIZE-1))
275
276/* PUD_SHIFT determines what a third-level page table entry can map */
277#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
278#define PUD_SIZE (1UL << PUD_SHIFT)
279#define PUD_MASK (~(PUD_SIZE-1))
280
281/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
282#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
283#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
284#define PGDIR_MASK (~(PGDIR_SIZE-1))
285
286/* Bits to mask out from a PMD to get to the PTE page */
287#define PMD_MASKED_BITS 0xc0000000000000ffUL
288/* Bits to mask out from a PUD to get to the PMD page */
289#define PUD_MASKED_BITS 0xc0000000000000ffUL
290/* Bits to mask out from a PGD to get to the PUD page */
291#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e
AK		 292
293extern unsigned long __vmalloc_start;
294extern unsigned long __vmalloc_end;
295#define VMALLOC_START __vmalloc_start
296#define VMALLOC_END __vmalloc_end
297
298extern unsigned long __kernel_virt_start;
299extern unsigned long __kernel_virt_size;
63ee9b2f 300extern unsigned long __kernel_io_start;
d6a9996e
AK		 301#define KERN_VIRT_START __kernel_virt_start
302#define KERN_VIRT_SIZE __kernel_virt_size
63ee9b2f 303#define KERN_IO_START __kernel_io_start
d6a9996e
AK		 304extern struct page *vmemmap;
305extern unsigned long ioremap_bot;
bfa37087 306extern unsigned long pci_io_base;
dd1842a2 307#endif /* __ASSEMBLY__ */
3dfcb315 308
ab537dca 309#include <asm/book3s/64/hash.h>
b0b5e9b1 310#include <asm/book3s/64/radix.h>
3dfcb315 311
a9252aae
AK		 312#ifdef CONFIG_PPC_64K_PAGES
313#include <asm/book3s/64/pgtable-64k.h>
314#else
315#include <asm/book3s/64/pgtable-4k.h>
316#endif
317
3dfcb315 318#include <asm/barrier.h>
3dfcb315
AK		 319/*
320 * The second half of the kernel virtual space is used for IO mappings,
321 * it's itself carved into the PIO region (ISA and PHB IO space) and
322 * the ioremap space
323 *
324 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
325 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
326 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
327 */
3dfcb315
AK		 328#define FULL_IO_SIZE 0x80000000ul
329#define ISA_IO_BASE (KERN_IO_START)
330#define ISA_IO_END (KERN_IO_START + 0x10000ul)
331#define PHB_IO_BASE (ISA_IO_END)
332#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
333#define IOREMAP_BASE (PHB_IO_END)
334#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
335
b0412ea9 336/* Advertise special mapping type for AGP */
b0412ea9
AK		 337#define HAVE_PAGE_AGP
338
339/* Advertise support for _PAGE_SPECIAL */
340#define __HAVE_ARCH_PTE_SPECIAL
341
3dfcb315
AK		 342#ifndef __ASSEMBLY__
343
344/*
345 * This is the default implementation of various PTE accessors, it's
346 * used in all cases except Book3S with 64K pages where we have a
347 * concept of sub-pages
348 */
349#ifndef __real_pte
350
3dfcb315
AK		 351#define __real_pte(e,p) ((real_pte_t){(e)})
352#define __rpte_to_pte(r) ((r).pte)
945537df 353#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 354
355#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
356 do { \
357 index = 0; \
358 shift = mmu_psize_defs[psize].shift; \
359
360#define pte_iterate_hashed_end() } while(0)
361
362/*
363 * We expect this to be called only for user addresses or kernel virtual
364 * addresses other than the linear mapping.
365 */
366#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
367
368#endif /* __real_pte */
369
ac94ac79
AK		 370static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
371 pte_t *ptep, unsigned long clr,
372 unsigned long set, int huge)
373{
374 if (radix_enabled())
375 return radix__pte_update(mm, addr, ptep, clr, set, huge);
376 return hash__pte_update(mm, addr, ptep, clr, set, huge);
377}
13f829a5
AK		 378/*
379 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
380 * We currently remove entries from the hashtable regardless of whether
381 * the entry was young or dirty.
382 *
383 * We should be more intelligent about this but for the moment we override
384 * these functions and force a tlb flush unconditionally
385 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
386 * function for both hash and radix.
387 */
388static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
389 unsigned long addr, pte_t *ptep)
390{
391 unsigned long old;
392
66c570f5 393 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 394 return 0;
395 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
396 return (old & _PAGE_ACCESSED) != 0;
397}
398
399#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
400#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
401({ \
402 int __r; \
403 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
404 __r; \
405})
406
d19469e8 407static inline int __pte_write(pte_t pte)
52c50ca7
AK		 408{
409 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
410}
411
412#ifdef CONFIG_NUMA_BALANCING
413#define pte_savedwrite pte_savedwrite
414static inline bool pte_savedwrite(pte_t pte)
415{
416 /*
417 * Saved write ptes are prot none ptes that doesn't have
418 * privileged bit sit. We mark prot none as one which has
419 * present and pviliged bit set and RWX cleared. To mark
420 * protnone which used to have _PAGE_WRITE set we clear
421 * the privileged bit.
422 */
423 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
424}
425#else
426#define pte_savedwrite pte_savedwrite
427static inline bool pte_savedwrite(pte_t pte)
428{
429 return false;
430}
431#endif
432
d19469e8
AK		 433static inline int pte_write(pte_t pte)
434{
435 return __pte_write(pte) || pte_savedwrite(pte);
436}
437
ca8afd40
CL		 438static inline int pte_read(pte_t pte)
439{
440 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
441}
442
13f829a5
AK		 443#define __HAVE_ARCH_PTEP_SET_WRPROTECT
444static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
445 pte_t *ptep)
446{
d19469e8 447 if (__pte_write(*ptep))
52c50ca7
AK		 448 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
449 else if (unlikely(pte_savedwrite(*ptep)))
450 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
13f829a5
AK		 451}
452
453static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
454 unsigned long addr, pte_t *ptep)
455{
52c50ca7
AK		 456 /*
457 * We should not find protnone for hugetlb, but this complete the
458 * interface.
459 */
d19469e8 460 if (__pte_write(*ptep))
52c50ca7
AK		 461 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
462 else if (unlikely(pte_savedwrite(*ptep)))
463 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
13f829a5
AK		 464}
465
466#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
467static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
468 unsigned long addr, pte_t *ptep)
469{
470 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
471 return __pte(old);
472}
473
f4894b80
AK		 474#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
475static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
476 unsigned long addr,
477 pte_t *ptep, int full)
478{
479 if (full && radix_enabled()) {
480 /*
481 * Let's skip the DD1 style pte update here. We know that
482 * this is a full mm pte clear and hence can be sure there is
483 * no parallel set_pte.
484 */
485 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
486 }
487 return ptep_get_and_clear(mm, addr, ptep);
488}
489
490
13f829a5
AK		 491static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
492 pte_t * ptep)
493{
494 pte_update(mm, addr, ptep, ~0UL, 0, 0);
495}
66c570f5 496
66c570f5
AK		 497static inline int pte_dirty(pte_t pte)
498{
499 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
500}
501
502static inline int pte_young(pte_t pte)
503{
504 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
505}
506
507static inline int pte_special(pte_t pte)
508{
509 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
510}
511
13f829a5
AK		 512static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
513
514#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
515static inline bool pte_soft_dirty(pte_t pte)
516{
66c570f5 517 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 518}
66c570f5 519
13f829a5
AK		 520static inline pte_t pte_mksoft_dirty(pte_t pte)
521{
522 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
523}
524
525static inline pte_t pte_clear_soft_dirty(pte_t pte)
526{
527 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
528}
529#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
530
531#ifdef CONFIG_NUMA_BALANCING
13f829a5
AK		 532static inline int pte_protnone(pte_t pte)
533{
c137a275
AK		 534 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
535 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
536}
537
538#define pte_mk_savedwrite pte_mk_savedwrite
539static inline pte_t pte_mk_savedwrite(pte_t pte)
540{
541 /*
542 * Used by Autonuma subsystem to preserve the write bit
543 * while marking the pte PROT_NONE. Only allow this
544 * on PROT_NONE pte
545 */
546 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
547 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
548 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
549}
550
551#define pte_clear_savedwrite pte_clear_savedwrite
552static inline pte_t pte_clear_savedwrite(pte_t pte)
553{
554 /*
555 * Used by KSM subsystem to make a protnone pte readonly.
556 */
557 VM_BUG_ON(!pte_protnone(pte));
558 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
559}
d19469e8
AK		 560#else
561#define pte_clear_savedwrite pte_clear_savedwrite
562static inline pte_t pte_clear_savedwrite(pte_t pte)
563{
564 VM_WARN_ON(1);
565 return __pte(pte_val(pte) & ~_PAGE_WRITE);
566}
13f829a5
AK		 567#endif /* CONFIG_NUMA_BALANCING */
568
569static inline int pte_present(pte_t pte)
570{
66c570f5 571 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
13f829a5 572}
f72a85e3
AK		 573
574#define pte_access_permitted pte_access_permitted
575static inline bool pte_access_permitted(pte_t pte, bool write)
576{
577 unsigned long pteval = pte_val(pte);
578 /* Also check for pte_user */
579 unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
580 /*
581 * _PAGE_READ is needed for any access and will be
582 * cleared for PROT_NONE
583 */
584 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
585
586 if (write)
587 need_pte_bits |= _PAGE_WRITE;
588
589 if ((pteval & need_pte_bits) != need_pte_bits)
590 return false;
591
592 if ((pteval & clear_pte_bits) == clear_pte_bits)
593 return false;
594 return true;
595}
596
13f829a5
AK		 597/*
598 * Conversion functions: convert a page and protection to a page entry,
599 * and a page entry and page directory to the page they refer to.
600 *
601 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
602 * long for now.
603 */
604static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
605{
606 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
607 pgprot_val(pgprot));
608}
609
610static inline unsigned long pte_pfn(pte_t pte)
611{
612 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
613}
614
615/* Generic modifiers for PTE bits */
616static inline pte_t pte_wrprotect(pte_t pte)
617{
d19469e8
AK		 618 if (unlikely(pte_savedwrite(pte)))
619 return pte_clear_savedwrite(pte);
13f829a5
AK		 620 return __pte(pte_val(pte) & ~_PAGE_WRITE);
621}
622
623static inline pte_t pte_mkclean(pte_t pte)
624{
625 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
626}
627
628static inline pte_t pte_mkold(pte_t pte)
629{
630 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
631}
632
633static inline pte_t pte_mkwrite(pte_t pte)
634{
635 /*
636 * write implies read, hence set both
637 */
638 return __pte(pte_val(pte) | _PAGE_RW);
639}
640
641static inline pte_t pte_mkdirty(pte_t pte)
642{
643 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
644}
645
646static inline pte_t pte_mkyoung(pte_t pte)
647{
648 return __pte(pte_val(pte) | _PAGE_ACCESSED);
649}
650
651static inline pte_t pte_mkspecial(pte_t pte)
652{
653 return __pte(pte_val(pte) | _PAGE_SPECIAL);
654}
655
656static inline pte_t pte_mkhuge(pte_t pte)
657{
658 return pte;
659}
660
ebd31197
OH		 661static inline pte_t pte_mkdevmap(pte_t pte)
662{
663 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
664}
665
c9c98bc5
OH		 666/*
667 * This is potentially called with a pmd as the argument, in which case it's not
668 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
669 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
670 * use in page directory entries (ie. non-ptes).
671 */
ebd31197
OH		 672static inline int pte_devmap(pte_t pte)
673{
c9c98bc5
OH		 674 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
675
676 return (pte_raw(pte) & mask) == mask;
ebd31197
OH		 677}
678
13f829a5
AK		 679static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
680{
681 /* FIXME!! check whether this need to be a conditional */
682 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
683}
684
34fbadd8
AK		 685static inline bool pte_user(pte_t pte)
686{
66c570f5 687 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
34fbadd8
AK		 688}
689
690/* Encode and de-code a swap entry */
691#define MAX_SWAPFILES_CHECK() do { \
692 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
693 /* \
694 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
695 * We filter HPTEFLAGS on set_pte. \
696 */ \
697 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
698 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
699 } while (0)
700/*
701 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
702 */
703#define SWP_TYPE_BITS 5
704#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
705 & ((1UL << SWP_TYPE_BITS) - 1))
706#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
707#define __swp_entry(type, offset) ((swp_entry_t) { \
708 ((type) << _PAGE_BIT_SWAP_TYPE) \
709 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
710/*
711 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
712 * swap type and offset we get from swap and convert that to pte to find a
713 * matching pte in linux page table.
714 * Clear bits not found in swap entries here.
715 */
716#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
717#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
718
719#ifdef CONFIG_MEM_SOFT_DIRTY
720#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
721#else
722#define _PAGE_SWP_SOFT_DIRTY 0UL
723#endif /* CONFIG_MEM_SOFT_DIRTY */
724
725#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
726static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
727{
728 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
729}
66c570f5 730
34fbadd8
AK		 731static inline bool pte_swp_soft_dirty(pte_t pte)
732{
66c570f5 733 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 734}
66c570f5 735
34fbadd8
AK		 736static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
737{
738 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
739}
740#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
741
742static inline bool check_pte_access(unsigned long access, unsigned long ptev)
743{
744 /*
745 * This check for _PAGE_RWX and _PAGE_PRESENT bits
746 */
747 if (access & ~ptev)
748 return false;
749 /*
750 * This check for access to privilege space
751 */
752 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
753 return false;
754
755 return true;
756}
ac94ac79
AK		 757/*
758 * Generic functions with hash/radix callbacks
759 */
760
c6d1a767 761static inline void __ptep_set_access_flags(struct mm_struct *mm,
b3603e17
AK		 762 pte_t *ptep, pte_t entry,
763 unsigned long address)
ac94ac79
AK		 764{
765 if (radix_enabled())
b3603e17 766 return radix__ptep_set_access_flags(mm, ptep, entry, address);
ac94ac79
AK		 767 return hash__ptep_set_access_flags(ptep, entry);
768}
769
770#define __HAVE_ARCH_PTE_SAME
771static inline int pte_same(pte_t pte_a, pte_t pte_b)
772{
773 if (radix_enabled())
774 return radix__pte_same(pte_a, pte_b);
775 return hash__pte_same(pte_a, pte_b);
776}
777
778static inline int pte_none(pte_t pte)
779{
780 if (radix_enabled())
781 return radix__pte_none(pte);
782 return hash__pte_none(pte);
783}
784
785static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
786 pte_t *ptep, pte_t pte, int percpu)
787{
788 if (radix_enabled())
789 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
790 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
791}
34fbadd8 792
13f829a5
AK		 793#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
794
795#define pgprot_noncached pgprot_noncached
796static inline pgprot_t pgprot_noncached(pgprot_t prot)
797{
798 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
799 _PAGE_NON_IDEMPOTENT);
800}
801
802#define pgprot_noncached_wc pgprot_noncached_wc
803static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
804{
805 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
806 _PAGE_TOLERANT);
807}
808
809#define pgprot_cached pgprot_cached
810static inline pgprot_t pgprot_cached(pgprot_t prot)
811{
812 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
813}
814
815#define pgprot_writecombine pgprot_writecombine
816static inline pgprot_t pgprot_writecombine(pgprot_t prot)
817{
818 return pgprot_noncached_wc(prot);
819}
820/*
821 * check a pte mapping have cache inhibited property
822 */
823static inline bool pte_ci(pte_t pte)
824{
825 unsigned long pte_v = pte_val(pte);
826
827 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
828 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
829 return true;
830 return false;
831}
832
f281b5d5
AK		 833static inline void pmd_set(pmd_t *pmdp, unsigned long val)
834{
835 *pmdp = __pmd(val);
836}
837
838static inline void pmd_clear(pmd_t *pmdp)
839{
840 *pmdp = __pmd(0);
841}
842
66c570f5
AK		 843static inline int pmd_none(pmd_t pmd)
844{
845 return !pmd_raw(pmd);
846}
847
848static inline int pmd_present(pmd_t pmd)
849{
850
851 return !pmd_none(pmd);
852}
3dfcb315 853
ac94ac79
AK		 854static inline int pmd_bad(pmd_t pmd)
855{
856 if (radix_enabled())
857 return radix__pmd_bad(pmd);
858 return hash__pmd_bad(pmd);
859}
860
f281b5d5
AK		 861static inline void pud_set(pud_t *pudp, unsigned long val)
862{
863 *pudp = __pud(val);
864}
865
866static inline void pud_clear(pud_t *pudp)
867{
868 *pudp = __pud(0);
869}
870
66c570f5
AK		 871static inline int pud_none(pud_t pud)
872{
873 return !pud_raw(pud);
874}
875
876static inline int pud_present(pud_t pud)
877{
878 return !pud_none(pud);
879}
3dfcb315
AK		 880
881extern struct page *pud_page(pud_t pud);
371352ca 882extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 883static inline pte_t pud_pte(pud_t pud)
884{
66c570f5 885 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 886}
887
888static inline pud_t pte_pud(pte_t pte)
889{
66c570f5 890 return __pud_raw(pte_raw(pte));
3dfcb315
AK		 891}
892#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 893
894static inline int pud_bad(pud_t pud)
895{
896 if (radix_enabled())
897 return radix__pud_bad(pud);
898 return hash__pud_bad(pud);
899}
900
f72a85e3
AK		 901#define pud_access_permitted pud_access_permitted
902static inline bool pud_access_permitted(pud_t pud, bool write)
903{
904 return pte_access_permitted(pud_pte(pud), write);
905}
ac94ac79 906
3dfcb315 907#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 908static inline void pgd_set(pgd_t *pgdp, unsigned long val)
909{
910 *pgdp = __pgd(val);
911}
3dfcb315 912
368ced78
AK		 913static inline void pgd_clear(pgd_t *pgdp)
914{
915 *pgdp = __pgd(0);
916}
917
66c570f5
AK		 918static inline int pgd_none(pgd_t pgd)
919{
920 return !pgd_raw(pgd);
921}
922
923static inline int pgd_present(pgd_t pgd)
924{
925 return !pgd_none(pgd);
926}
368ced78
AK		 927
928static inline pte_t pgd_pte(pgd_t pgd)
929{
66c570f5 930 return __pte_raw(pgd_raw(pgd));
368ced78
AK		 931}
932
933static inline pgd_t pte_pgd(pte_t pte)
934{
66c570f5 935 return __pgd_raw(pte_raw(pte));
368ced78
AK		 936}
937
ac94ac79
AK		 938static inline int pgd_bad(pgd_t pgd)
939{
940 if (radix_enabled())
941 return radix__pgd_bad(pgd);
942 return hash__pgd_bad(pgd);
943}
944
f72a85e3
AK		 945#define pgd_access_permitted pgd_access_permitted
946static inline bool pgd_access_permitted(pgd_t pgd, bool write)
947{
948 return pte_access_permitted(pgd_pte(pgd), write);
949}
950
368ced78
AK		 951extern struct page *pgd_page(pgd_t pgd);
952
aba480e1
AK		 953/* Pointers in the page table tree are physical addresses */
954#define __pgtable_ptr_val(ptr) __pa(ptr)
955
956#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
957#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
958#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
959
960#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
961#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
962#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
963#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
964
3dfcb315
AK		 965/*
966 * Find an entry in a page-table-directory. We combine the address region
967 * (the high order N bits) and the pgd portion of the address.
968 */
3dfcb315
AK		 969
970#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
971
368ced78
AK		 972#define pud_offset(pgdp, addr) \
973 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 974#define pmd_offset(pudp,addr) \
371352ca 975 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 976#define pte_offset_kernel(dir,addr) \
371352ca 977 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 978
979#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
980#define pte_unmap(pte) do { } while(0)
981
982/* to find an entry in a kernel page-table-directory */
983/* This now only contains the vmalloc pages */
984#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 985
986#define pte_ERROR(e) \
987 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
988#define pmd_ERROR(e) \
989 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 990#define pud_ERROR(e) \
991 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 992#define pgd_ERROR(e) \
993 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
994
31a14fae
AK		 995static inline int map_kernel_page(unsigned long ea, unsigned long pa,
996 unsigned long flags)
7207f436 997{
d9225ad9
AK		 998 if (radix_enabled()) {
999#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1000 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1001 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1002#endif
1003 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
1004 }
31a14fae 1005 return hash__map_kernel_page(ea, pa, flags);
7207f436 1006}
31a14fae
AK		 1007
1008static inline int __meminit vmemmap_create_mapping(unsigned long start,
1009 unsigned long page_size,
1010 unsigned long phys)
7207f436 1011{
d9225ad9
AK		 1012 if (radix_enabled())
1013 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 1014 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 1015}
31a14fae
AK		 1016
1017#ifdef CONFIG_MEMORY_HOTPLUG
1018static inline void vmemmap_remove_mapping(unsigned long start,
1019 unsigned long page_size)
7207f436 1020{
d9225ad9
AK		 1021 if (radix_enabled())
1022 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 1023 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 1024}
31a14fae 1025#endif
3dfcb315
AK		 1026struct page *realmode_pfn_to_page(unsigned long pfn);
1027
3dfcb315
AK		 1028static inline pte_t pmd_pte(pmd_t pmd)
1029{
66c570f5 1030 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 1031}
1032
1033static inline pmd_t pte_pmd(pte_t pte)
1034{
66c570f5 1035 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 1036}
1037
1038static inline pte_t *pmdp_ptep(pmd_t *pmd)
1039{
1040 return (pte_t *)pmd;
1041}
3dfcb315
AK		 1042#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1043#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1044#define pmd_young(pmd) pte_young(pmd_pte(pmd))
1045#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1046#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1047#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 1048#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 1049#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1050#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
c137a275
AK		 1051#define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
1052#define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
7207f436
LD		 1053
1054#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1055#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1056#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1057#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1058#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1059
1ca72129
AK		 1060#ifdef CONFIG_NUMA_BALANCING
1061static inline int pmd_protnone(pmd_t pmd)
1062{
1063 return pte_protnone(pmd_pte(pmd));
1064}
1065#endif /* CONFIG_NUMA_BALANCING */
3dfcb315 1066
3dfcb315 1067#define pmd_write(pmd) pte_write(pmd_pte(pmd))
d19469e8 1068#define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
c137a275 1069#define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
3dfcb315 1070
f72a85e3
AK		 1071#define pmd_access_permitted pmd_access_permitted
1072static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1073{
1074 return pte_access_permitted(pmd_pte(pmd), write);
1075}
1076
6a1ea362
AK		 1077#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1078extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1079extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1080extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1081extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1082 pmd_t *pmdp, pmd_t pmd);
1083extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1084 pmd_t *pmd);
3df33f12
AK		 1085extern int hash__has_transparent_hugepage(void);
1086static inline int has_transparent_hugepage(void)
1087{
bde3eb62
AK		 1088 if (radix_enabled())
1089 return radix__has_transparent_hugepage();
3df33f12
AK		 1090 return hash__has_transparent_hugepage();
1091}
c04a5880 1092#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 1093
3df33f12
AK		 1094static inline unsigned long
1095pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1096 unsigned long clr, unsigned long set)
3dfcb315 1097{
bde3eb62
AK		 1098 if (radix_enabled())
1099 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 1100 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1101}
1102
1103static inline int pmd_large(pmd_t pmd)
1104{
66c570f5 1105 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 1106}
1107
1108static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1109{
1110 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1111}
1112/*
1113 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1114 * the below will work for radix too
1115 */
1116static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1117 unsigned long addr, pmd_t *pmdp)
1118{
1119 unsigned long old;
1120
66c570f5 1121 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 1122 return 0;
1123 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1124 return ((old & _PAGE_ACCESSED) != 0);
1125}
1126
1127#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1128static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1129 pmd_t *pmdp)
1130{
d19469e8 1131 if (__pmd_write((*pmdp)))
52c50ca7
AK		 1132 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1133 else if (unlikely(pmd_savedwrite(*pmdp)))
1134 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
3dfcb315
AK		 1135}
1136
ab624762
AK		 1137static inline int pmd_trans_huge(pmd_t pmd)
1138{
1139 if (radix_enabled())
1140 return radix__pmd_trans_huge(pmd);
1141 return hash__pmd_trans_huge(pmd);
1142}
1143
1144#define __HAVE_ARCH_PMD_SAME
1145static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1146{
1147 if (radix_enabled())
1148 return radix__pmd_same(pmd_a, pmd_b);
1149 return hash__pmd_same(pmd_a, pmd_b);
1150}
1151
3dfcb315
AK		 1152static inline pmd_t pmd_mkhuge(pmd_t pmd)
1153{
ab624762
AK		 1154 if (radix_enabled())
1155 return radix__pmd_mkhuge(pmd);
1156 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 1157}
1158
3dfcb315
AK		 1159#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1160extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1161 unsigned long address, pmd_t *pmdp,
1162 pmd_t entry, int dirty);
1163
3dfcb315
AK		 1164#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1165extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1166 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 1167
1168#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 1169static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1170 unsigned long addr, pmd_t *pmdp)
1171{
bde3eb62
AK		 1172 if (radix_enabled())
1173 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 1174 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1175}
3dfcb315 1176
3df33f12
AK		 1177static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1178 unsigned long address, pmd_t *pmdp)
1179{
bde3eb62
AK		 1180 if (radix_enabled())
1181 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 1182 return hash__pmdp_collapse_flush(vma, address, pmdp);
1183}
3dfcb315
AK		 1184#define pmdp_collapse_flush pmdp_collapse_flush
1185
1186#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 1187static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1188 pmd_t *pmdp, pgtable_t pgtable)
1189{
bde3eb62
AK		 1190 if (radix_enabled())
1191 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 1192 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1193}
1194
3dfcb315 1195#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 1196static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1197 pmd_t *pmdp)
1198{
bde3eb62
AK		 1199 if (radix_enabled())
1200 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 1201 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1202}
3dfcb315
AK		 1203
1204#define __HAVE_ARCH_PMDP_INVALIDATE
1205extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1206 pmd_t *pmdp);
1207
c777e2a8 1208#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
3df33f12
AK		 1209static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
1210 unsigned long address, pmd_t *pmdp)
1211{
bde3eb62
AK		 1212 if (radix_enabled())
1213 return radix__pmdp_huge_split_prepare(vma, address, pmdp);
3df33f12
AK		 1214 return hash__pmdp_huge_split_prepare(vma, address, pmdp);
1215}
c777e2a8 1216
3dfcb315
AK		 1217#define pmd_move_must_withdraw pmd_move_must_withdraw
1218struct spinlock;
1219static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1dd38b6c
AK		 1220 struct spinlock *old_pmd_ptl,
1221 struct vm_area_struct *vma)
3dfcb315 1222{
bde3eb62
AK		 1223 if (radix_enabled())
1224 return false;
3dfcb315
AK		 1225 /*
1226 * Archs like ppc64 use pgtable to store per pmd
1227 * specific information. So when we switch the pmd,
1228 * we should also withdraw and deposit the pgtable
1229 */
1230 return true;
1231}
953c66c2
AK		 1232
1233
1234#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1235static inline bool arch_needs_pgtable_deposit(void)
1236{
1237 if (radix_enabled())
1238 return false;
1239 return true;
1240}
fa4531f7 1241extern void serialize_against_pte_lookup(struct mm_struct *mm);
953c66c2 1242
ebd31197
OH		 1243
1244static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1245{
1246 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1247}
1248
1249static inline int pmd_devmap(pmd_t pmd)
1250{
1251 return pte_devmap(pmd_pte(pmd));
1252}
1253
1254static inline int pud_devmap(pud_t pud)
1255{
1256 return 0;
1257}
1258
1259static inline int pgd_devmap(pgd_t pgd)
1260{
1261 return 0;
1262}
6a1ea362 1263#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
ebd31197
OH		 1264
1265static inline const int pud_pfn(pud_t pud)
1266{
1267 /*
1268 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1269 * check so this should never be used. If it grows another user we
1270 * want to know about it.
1271 */
1272 BUILD_BUG();
1273 return 0;
1274}
029d9252 1275
3dfcb315
AK		 1276#endif /* __ASSEMBLY__ */
1277#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)