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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3dfcb315 AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 | 4 | |
9849a569 KS |
5 | #include <asm-generic/5level-fixup.h> |
6 | ||
c137a275 AK |
7 | #ifndef __ASSEMBLY__ |
8 | #include <linux/mmdebug.h> | |
ebd31197 | 9 | #include <linux/bug.h> |
c137a275 | 10 | #endif |
9849a569 | 11 | |
2e873519 AK |
12 | /* |
13 | * Common bits between hash and Radix page table | |
14 | */ | |
15 | #define _PAGE_BIT_SWAP_TYPE 0 | |
16 | ||
17 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
18 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
19 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
20 | #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) | |
21 | #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) | |
22 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ | |
23 | #define _PAGE_SAO 0x00010 /* Strong access order */ | |
24 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ | |
25 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
26 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
27 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 28 | /* |
2e873519 | 29 | * Software bits |
3dfcb315 | 30 | */ |
69dfbaeb AK |
31 | #define _RPAGE_SW0 0x2000000000000000UL |
32 | #define _RPAGE_SW1 0x00800 | |
33 | #define _RPAGE_SW2 0x00400 | |
34 | #define _RPAGE_SW3 0x00200 | |
049d567a AK |
35 | #define _RPAGE_RSV1 0x1000000000000000UL |
36 | #define _RPAGE_RSV2 0x0800000000000000UL | |
37 | #define _RPAGE_RSV3 0x0400000000000000UL | |
38 | #define _RPAGE_RSV4 0x0200000000000000UL | |
eb95d016 | 39 | #define _RPAGE_RSV5 0x00040UL |
6aa59f51 AK |
40 | |
41 | #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ | |
42 | #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ | |
bd0dbb73 AK |
43 | /* |
44 | * We need to mark a pmd pte invalid while splitting. We can do that by clearing | |
45 | * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to | |
46 | * differentiate between two use a SW field when invalidating. | |
47 | * | |
48 | * We do that temporary invalidate for regular pte entry in ptep_set_access_flags | |
49 | * | |
50 | * This is used only when _PAGE_PRESENT is cleared. | |
51 | */ | |
52 | #define _PAGE_INVALID _RPAGE_SW0 | |
6aa59f51 AK |
53 | |
54 | /* | |
55 | * Top and bottom bits of RPN which can be used by hash | |
56 | * translation mode, because we expect them to be zero | |
57 | * otherwise. | |
58 | */ | |
32789d38 AK |
59 | #define _RPAGE_RPN0 0x01000 |
60 | #define _RPAGE_RPN1 0x02000 | |
6aa59f51 AK |
61 | #define _RPAGE_RPN44 0x0100000000000000UL |
62 | #define _RPAGE_RPN43 0x0080000000000000UL | |
63 | #define _RPAGE_RPN42 0x0040000000000000UL | |
64 | #define _RPAGE_RPN41 0x0020000000000000UL | |
049d567a | 65 | |
2f18d533 AK |
66 | /* Max physical address bit as per radix table */ |
67 | #define _RPAGE_PA_MAX 57 | |
68 | ||
69 | /* | |
70 | * Max physical address bit we will use for now. | |
71 | * | |
72 | * This is mostly a hardware limitation and for now Power9 has | |
73 | * a 51 bit limit. | |
74 | * | |
75 | * This is different from the number of physical bit required to address | |
76 | * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. | |
77 | * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum | |
78 | * number of sections we can support (SECTIONS_SHIFT). | |
79 | * | |
80 | * This is different from Radix page table limitation above and | |
81 | * should always be less than that. The limit is done such that | |
82 | * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX | |
83 | * for hash linux page table specific bits. | |
84 | * | |
85 | * In order to be compatible with future hardware generations we keep | |
86 | * some offsets and limit this for now to 53 | |
87 | */ | |
88 | #define _PAGE_PA_MAX 53 | |
89 | ||
69dfbaeb | 90 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
69dfbaeb | 91 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
ebd31197 OH |
92 | #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ |
93 | #define __HAVE_ARCH_PTE_DEVMAP | |
94 | ||
2e873519 AK |
95 | /* |
96 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
97 | * Instead of fixing all of them, add an alternate define which | |
98 | * maps CI pte mapping. | |
99 | */ | |
100 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
101 | /* | |
2f18d533 AK |
102 | * We support _RPAGE_PA_MAX bit real address in pte. On the linux side |
103 | * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX | |
104 | * and every thing below PAGE_SHIFT; | |
2e873519 | 105 | */ |
2f18d533 | 106 | #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) |
2e873519 AK |
107 | /* |
108 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
109 | * in here, on radix we expect them to be zero. | |
110 | */ | |
111 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
112 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
4628a645 | 113 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
114 | /* |
115 | * user access blocked by key | |
116 | */ | |
117 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
118 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
119 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ | |
120 | _PAGE_RW | _PAGE_EXEC) | |
2e873519 AK |
121 | /* |
122 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
123 | * pgprot changes | |
124 | */ | |
125 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
126 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
4628a645 | 127 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
eb95d016 RP |
128 | |
129 | #define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \ | |
130 | H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4) | |
3dfcb315 | 131 | /* |
2e873519 AK |
132 | * We define 2 sets of base prot bits, one for basic pages (ie, |
133 | * cacheable kernel and user pages) and one for non cacheable | |
134 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
135 | * the processor might need it for DMA coherency. | |
3dfcb315 | 136 | */ |
093d7ca2 | 137 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
2e873519 AK |
138 | #define _PAGE_BASE (_PAGE_BASE_NC) |
139 | ||
140 | /* Permission masks used to generate the __P and __S table, | |
141 | * | |
142 | * Note:__pgprot is defined in arch/powerpc/include/asm/page.h | |
143 | * | |
144 | * Write permissions imply read permissions for now (we could make write-only | |
145 | * pages on BookE but we don't bother for now). Execute permission control is | |
146 | * possible on platforms that define _PAGE_EXEC | |
2e873519 AK |
147 | */ |
148 | #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) | |
149 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) | |
150 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) | |
151 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) | |
152 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
153 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) | |
154 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
155 | ||
2e873519 AK |
156 | /* Permission masks used for kernel mappings */ |
157 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
158 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
159 | _PAGE_TOLERANT) | |
160 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
161 | _PAGE_NON_IDEMPOTENT) | |
162 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) | |
163 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
164 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
165 | ||
166 | /* | |
167 | * Protection used for kernel text. We want the debuggers to be able to | |
168 | * set breakpoints anywhere, so don't write protect the kernel text | |
169 | * on platforms where such control is possible. | |
170 | */ | |
171 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ | |
172 | defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) | |
173 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_X | |
174 | #else | |
175 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX | |
176 | #endif | |
177 | ||
178 | /* Make modules code happy. We don't set RO yet */ | |
179 | #define PAGE_KERNEL_EXEC PAGE_KERNEL_X | |
180 | #define PAGE_AGP (PAGE_KERNEL_NC) | |
3dfcb315 | 181 | |
dd1842a2 AK |
182 | #ifndef __ASSEMBLY__ |
183 | /* | |
184 | * page table defines | |
185 | */ | |
186 | extern unsigned long __pte_index_size; | |
187 | extern unsigned long __pmd_index_size; | |
188 | extern unsigned long __pud_index_size; | |
189 | extern unsigned long __pgd_index_size; | |
fae22116 | 190 | extern unsigned long __pud_cache_index; |
dd1842a2 AK |
191 | #define PTE_INDEX_SIZE __pte_index_size |
192 | #define PMD_INDEX_SIZE __pmd_index_size | |
193 | #define PUD_INDEX_SIZE __pud_index_size | |
194 | #define PGD_INDEX_SIZE __pgd_index_size | |
738f9645 AK |
195 | /* pmd table use page table fragments */ |
196 | #define PMD_CACHE_INDEX 0 | |
fae22116 | 197 | #define PUD_CACHE_INDEX __pud_cache_index |
dd1842a2 AK |
198 | /* |
199 | * Because of use of pte fragments and THP, size of page table | |
200 | * are not always derived out of index size above. | |
201 | */ | |
202 | extern unsigned long __pte_table_size; | |
203 | extern unsigned long __pmd_table_size; | |
204 | extern unsigned long __pud_table_size; | |
205 | extern unsigned long __pgd_table_size; | |
206 | #define PTE_TABLE_SIZE __pte_table_size | |
207 | #define PMD_TABLE_SIZE __pmd_table_size | |
208 | #define PUD_TABLE_SIZE __pud_table_size | |
209 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
210 | |
211 | extern unsigned long __pmd_val_bits; | |
212 | extern unsigned long __pud_val_bits; | |
213 | extern unsigned long __pgd_val_bits; | |
214 | #define PMD_VAL_BITS __pmd_val_bits | |
215 | #define PUD_VAL_BITS __pud_val_bits | |
216 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
217 | |
218 | extern unsigned long __pte_frag_nr; | |
219 | #define PTE_FRAG_NR __pte_frag_nr | |
220 | extern unsigned long __pte_frag_size_shift; | |
221 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
222 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 | 223 | |
8a6c697b AK |
224 | extern unsigned long __pmd_frag_nr; |
225 | #define PMD_FRAG_NR __pmd_frag_nr | |
226 | extern unsigned long __pmd_frag_size_shift; | |
227 | #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift | |
228 | #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) | |
229 | ||
dd1842a2 AK |
230 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) |
231 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
232 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
233 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
234 | ||
235 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
236 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
237 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
238 | #define PMD_MASK (~(PMD_SIZE-1)) | |
239 | ||
240 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
241 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
242 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
243 | #define PUD_MASK (~(PUD_SIZE-1)) | |
244 | ||
245 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
246 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
247 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
248 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
249 | ||
250 | /* Bits to mask out from a PMD to get to the PTE page */ | |
251 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
252 | /* Bits to mask out from a PUD to get to the PMD page */ | |
253 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
254 | /* Bits to mask out from a PGD to get to the PUD page */ | |
255 | #define PGD_MASKED_BITS 0xc0000000000000ffUL | |
d6a9996e | 256 | |
0c4d2680 AK |
257 | /* |
258 | * Used as an indicator for rcu callback functions | |
259 | */ | |
260 | enum pgtable_index { | |
261 | PTE_INDEX = 0, | |
262 | PMD_INDEX, | |
263 | PUD_INDEX, | |
264 | PGD_INDEX, | |
fadd03c6 AK |
265 | /* |
266 | * Below are used with 4k page size and hugetlb | |
267 | */ | |
268 | HTLB_16M_INDEX, | |
269 | HTLB_16G_INDEX, | |
0c4d2680 AK |
270 | }; |
271 | ||
d6a9996e AK |
272 | extern unsigned long __vmalloc_start; |
273 | extern unsigned long __vmalloc_end; | |
274 | #define VMALLOC_START __vmalloc_start | |
275 | #define VMALLOC_END __vmalloc_end | |
276 | ||
277 | extern unsigned long __kernel_virt_start; | |
278 | extern unsigned long __kernel_virt_size; | |
63ee9b2f | 279 | extern unsigned long __kernel_io_start; |
a35a3c6f | 280 | extern unsigned long __kernel_io_end; |
d6a9996e AK |
281 | #define KERN_VIRT_START __kernel_virt_start |
282 | #define KERN_VIRT_SIZE __kernel_virt_size | |
63ee9b2f | 283 | #define KERN_IO_START __kernel_io_start |
a35a3c6f AK |
284 | #define KERN_IO_END __kernel_io_end |
285 | ||
d6a9996e AK |
286 | extern struct page *vmemmap; |
287 | extern unsigned long ioremap_bot; | |
bfa37087 | 288 | extern unsigned long pci_io_base; |
dd1842a2 | 289 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 290 | |
ab537dca | 291 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 292 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 293 | |
a9252aae AK |
294 | #ifdef CONFIG_PPC_64K_PAGES |
295 | #include <asm/book3s/64/pgtable-64k.h> | |
296 | #else | |
297 | #include <asm/book3s/64/pgtable-4k.h> | |
298 | #endif | |
299 | ||
3dfcb315 | 300 | #include <asm/barrier.h> |
3dfcb315 | 301 | /* |
a35a3c6f | 302 | * IO space itself carved into the PIO region (ISA and PHB IO space) and |
3dfcb315 AK |
303 | * the ioremap space |
304 | * | |
305 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
306 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
307 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
308 | */ | |
3dfcb315 AK |
309 | #define FULL_IO_SIZE 0x80000000ul |
310 | #define ISA_IO_BASE (KERN_IO_START) | |
311 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
312 | #define PHB_IO_BASE (ISA_IO_END) | |
313 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
314 | #define IOREMAP_BASE (PHB_IO_END) | |
a35a3c6f | 315 | #define IOREMAP_END (KERN_IO_END) |
3dfcb315 | 316 | |
b0412ea9 | 317 | /* Advertise special mapping type for AGP */ |
b0412ea9 AK |
318 | #define HAVE_PAGE_AGP |
319 | ||
3dfcb315 AK |
320 | #ifndef __ASSEMBLY__ |
321 | ||
322 | /* | |
323 | * This is the default implementation of various PTE accessors, it's | |
324 | * used in all cases except Book3S with 64K pages where we have a | |
325 | * concept of sub-pages | |
326 | */ | |
327 | #ifndef __real_pte | |
328 | ||
ff31e105 | 329 | #define __real_pte(e, p, o) ((real_pte_t){(e)}) |
3dfcb315 | 330 | #define __rpte_to_pte(r) ((r).pte) |
945537df | 331 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
332 | |
333 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
334 | do { \ | |
335 | index = 0; \ | |
336 | shift = mmu_psize_defs[psize].shift; \ | |
337 | ||
338 | #define pte_iterate_hashed_end() } while(0) | |
339 | ||
340 | /* | |
341 | * We expect this to be called only for user addresses or kernel virtual | |
342 | * addresses other than the linear mapping. | |
343 | */ | |
344 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
345 | ||
346 | #endif /* __real_pte */ | |
347 | ||
ac94ac79 AK |
348 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
349 | pte_t *ptep, unsigned long clr, | |
350 | unsigned long set, int huge) | |
351 | { | |
352 | if (radix_enabled()) | |
353 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
354 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
355 | } | |
13f829a5 AK |
356 | /* |
357 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
358 | * We currently remove entries from the hashtable regardless of whether | |
359 | * the entry was young or dirty. | |
360 | * | |
361 | * We should be more intelligent about this but for the moment we override | |
362 | * these functions and force a tlb flush unconditionally | |
363 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
364 | * function for both hash and radix. | |
365 | */ | |
366 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
367 | unsigned long addr, pte_t *ptep) | |
368 | { | |
369 | unsigned long old; | |
370 | ||
66c570f5 | 371 | if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
13f829a5 AK |
372 | return 0; |
373 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
374 | return (old & _PAGE_ACCESSED) != 0; | |
375 | } | |
376 | ||
377 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
378 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
379 | ({ \ | |
380 | int __r; \ | |
381 | __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ | |
382 | __r; \ | |
383 | }) | |
384 | ||
d19469e8 | 385 | static inline int __pte_write(pte_t pte) |
52c50ca7 AK |
386 | { |
387 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); | |
388 | } | |
389 | ||
390 | #ifdef CONFIG_NUMA_BALANCING | |
391 | #define pte_savedwrite pte_savedwrite | |
392 | static inline bool pte_savedwrite(pte_t pte) | |
393 | { | |
394 | /* | |
395 | * Saved write ptes are prot none ptes that doesn't have | |
396 | * privileged bit sit. We mark prot none as one which has | |
397 | * present and pviliged bit set and RWX cleared. To mark | |
398 | * protnone which used to have _PAGE_WRITE set we clear | |
399 | * the privileged bit. | |
400 | */ | |
401 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); | |
402 | } | |
403 | #else | |
404 | #define pte_savedwrite pte_savedwrite | |
405 | static inline bool pte_savedwrite(pte_t pte) | |
406 | { | |
407 | return false; | |
408 | } | |
409 | #endif | |
410 | ||
d19469e8 AK |
411 | static inline int pte_write(pte_t pte) |
412 | { | |
413 | return __pte_write(pte) || pte_savedwrite(pte); | |
414 | } | |
415 | ||
ca8afd40 CL |
416 | static inline int pte_read(pte_t pte) |
417 | { | |
418 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); | |
419 | } | |
420 | ||
13f829a5 AK |
421 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
422 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
423 | pte_t *ptep) | |
424 | { | |
d19469e8 | 425 | if (__pte_write(*ptep)) |
52c50ca7 AK |
426 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); |
427 | else if (unlikely(pte_savedwrite(*ptep))) | |
428 | pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); | |
13f829a5 AK |
429 | } |
430 | ||
8e581d43 | 431 | #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT |
13f829a5 AK |
432 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, |
433 | unsigned long addr, pte_t *ptep) | |
434 | { | |
52c50ca7 AK |
435 | /* |
436 | * We should not find protnone for hugetlb, but this complete the | |
437 | * interface. | |
438 | */ | |
d19469e8 | 439 | if (__pte_write(*ptep)) |
52c50ca7 AK |
440 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); |
441 | else if (unlikely(pte_savedwrite(*ptep))) | |
442 | pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); | |
13f829a5 AK |
443 | } |
444 | ||
445 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
446 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
447 | unsigned long addr, pte_t *ptep) | |
448 | { | |
449 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
450 | return __pte(old); | |
451 | } | |
452 | ||
f4894b80 AK |
453 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
454 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
455 | unsigned long addr, | |
456 | pte_t *ptep, int full) | |
457 | { | |
458 | if (full && radix_enabled()) { | |
459 | /* | |
2bf1071a NP |
460 | * We know that this is a full mm pte clear and |
461 | * hence can be sure there is no parallel set_pte. | |
f4894b80 AK |
462 | */ |
463 | return radix__ptep_get_and_clear_full(mm, addr, ptep, full); | |
464 | } | |
465 | return ptep_get_and_clear(mm, addr, ptep); | |
466 | } | |
467 | ||
468 | ||
13f829a5 AK |
469 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
470 | pte_t * ptep) | |
471 | { | |
472 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
473 | } | |
66c570f5 | 474 | |
66c570f5 AK |
475 | static inline int pte_dirty(pte_t pte) |
476 | { | |
477 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); | |
478 | } | |
479 | ||
480 | static inline int pte_young(pte_t pte) | |
481 | { | |
482 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); | |
483 | } | |
484 | ||
485 | static inline int pte_special(pte_t pte) | |
486 | { | |
487 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); | |
488 | } | |
489 | ||
daba7902 CL |
490 | static inline bool pte_exec(pte_t pte) |
491 | { | |
492 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); | |
493 | } | |
494 | ||
13f829a5 AK |
495 | |
496 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
497 | static inline bool pte_soft_dirty(pte_t pte) | |
498 | { | |
66c570f5 | 499 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 | 500 | } |
66c570f5 | 501 | |
13f829a5 AK |
502 | static inline pte_t pte_mksoft_dirty(pte_t pte) |
503 | { | |
1b2443a5 | 504 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
505 | } |
506 | ||
507 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
508 | { | |
1b2443a5 | 509 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
510 | } |
511 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
512 | ||
513 | #ifdef CONFIG_NUMA_BALANCING | |
13f829a5 AK |
514 | static inline int pte_protnone(pte_t pte) |
515 | { | |
c137a275 AK |
516 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == |
517 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
518 | } | |
519 | ||
520 | #define pte_mk_savedwrite pte_mk_savedwrite | |
521 | static inline pte_t pte_mk_savedwrite(pte_t pte) | |
522 | { | |
523 | /* | |
524 | * Used by Autonuma subsystem to preserve the write bit | |
525 | * while marking the pte PROT_NONE. Only allow this | |
526 | * on PROT_NONE pte | |
527 | */ | |
528 | VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != | |
529 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); | |
1b2443a5 | 530 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); |
c137a275 AK |
531 | } |
532 | ||
533 | #define pte_clear_savedwrite pte_clear_savedwrite | |
534 | static inline pte_t pte_clear_savedwrite(pte_t pte) | |
535 | { | |
536 | /* | |
537 | * Used by KSM subsystem to make a protnone pte readonly. | |
538 | */ | |
539 | VM_BUG_ON(!pte_protnone(pte)); | |
1b2443a5 | 540 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); |
c137a275 | 541 | } |
d19469e8 AK |
542 | #else |
543 | #define pte_clear_savedwrite pte_clear_savedwrite | |
544 | static inline pte_t pte_clear_savedwrite(pte_t pte) | |
545 | { | |
546 | VM_WARN_ON(1); | |
1b2443a5 | 547 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
d19469e8 | 548 | } |
13f829a5 AK |
549 | #endif /* CONFIG_NUMA_BALANCING */ |
550 | ||
551 | static inline int pte_present(pte_t pte) | |
552 | { | |
bd0dbb73 AK |
553 | /* |
554 | * A pte is considerent present if _PAGE_PRESENT is set. | |
555 | * We also need to consider the pte present which is marked | |
556 | * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID | |
557 | * if we find _PAGE_PRESENT cleared. | |
558 | */ | |
559 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)); | |
13f829a5 | 560 | } |
f72a85e3 | 561 | |
daba7902 CL |
562 | static inline bool pte_hw_valid(pte_t pte) |
563 | { | |
564 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT)); | |
565 | } | |
566 | ||
bca7aacf | 567 | #ifdef CONFIG_PPC_MEM_KEYS |
f2407ef3 | 568 | extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); |
bca7aacf RP |
569 | #else |
570 | static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) | |
571 | { | |
572 | return true; | |
573 | } | |
574 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
f2407ef3 | 575 | |
1b2443a5 CL |
576 | static inline bool pte_user(pte_t pte) |
577 | { | |
578 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); | |
579 | } | |
580 | ||
f72a85e3 AK |
581 | #define pte_access_permitted pte_access_permitted |
582 | static inline bool pte_access_permitted(pte_t pte, bool write) | |
583 | { | |
f72a85e3 AK |
584 | /* |
585 | * _PAGE_READ is needed for any access and will be | |
586 | * cleared for PROT_NONE | |
587 | */ | |
1b2443a5 | 588 | if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) |
f72a85e3 AK |
589 | return false; |
590 | ||
1b2443a5 | 591 | if (write && !pte_write(pte)) |
f72a85e3 | 592 | return false; |
bca7aacf RP |
593 | |
594 | return arch_pte_access_permitted(pte_val(pte), write, 0); | |
f72a85e3 AK |
595 | } |
596 | ||
13f829a5 AK |
597 | /* |
598 | * Conversion functions: convert a page and protection to a page entry, | |
599 | * and a page entry and page directory to the page they refer to. | |
600 | * | |
601 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
602 | * long for now. | |
603 | */ | |
604 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
605 | { | |
606 | return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | | |
607 | pgprot_val(pgprot)); | |
608 | } | |
609 | ||
610 | static inline unsigned long pte_pfn(pte_t pte) | |
611 | { | |
612 | return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; | |
613 | } | |
614 | ||
615 | /* Generic modifiers for PTE bits */ | |
616 | static inline pte_t pte_wrprotect(pte_t pte) | |
617 | { | |
d19469e8 AK |
618 | if (unlikely(pte_savedwrite(pte))) |
619 | return pte_clear_savedwrite(pte); | |
1b2443a5 | 620 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
13f829a5 AK |
621 | } |
622 | ||
daba7902 CL |
623 | static inline pte_t pte_exprotect(pte_t pte) |
624 | { | |
1b2443a5 | 625 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); |
13f829a5 AK |
626 | } |
627 | ||
628 | static inline pte_t pte_mkclean(pte_t pte) | |
629 | { | |
1b2443a5 | 630 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); |
13f829a5 AK |
631 | } |
632 | ||
633 | static inline pte_t pte_mkold(pte_t pte) | |
634 | { | |
1b2443a5 | 635 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); |
13f829a5 AK |
636 | } |
637 | ||
daba7902 CL |
638 | static inline pte_t pte_mkexec(pte_t pte) |
639 | { | |
1b2443a5 | 640 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); |
daba7902 CL |
641 | } |
642 | ||
643 | static inline pte_t pte_mkpte(pte_t pte) | |
644 | { | |
1b2443a5 | 645 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); |
13f829a5 AK |
646 | } |
647 | ||
648 | static inline pte_t pte_mkwrite(pte_t pte) | |
649 | { | |
650 | /* | |
651 | * write implies read, hence set both | |
652 | */ | |
1b2443a5 | 653 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); |
13f829a5 AK |
654 | } |
655 | ||
656 | static inline pte_t pte_mkdirty(pte_t pte) | |
657 | { | |
1b2443a5 | 658 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); |
13f829a5 AK |
659 | } |
660 | ||
661 | static inline pte_t pte_mkyoung(pte_t pte) | |
662 | { | |
1b2443a5 | 663 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); |
13f829a5 AK |
664 | } |
665 | ||
666 | static inline pte_t pte_mkspecial(pte_t pte) | |
667 | { | |
1b2443a5 | 668 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); |
13f829a5 AK |
669 | } |
670 | ||
671 | static inline pte_t pte_mkhuge(pte_t pte) | |
672 | { | |
673 | return pte; | |
674 | } | |
675 | ||
ebd31197 OH |
676 | static inline pte_t pte_mkdevmap(pte_t pte) |
677 | { | |
1b2443a5 | 678 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); |
ebd31197 OH |
679 | } |
680 | ||
daba7902 CL |
681 | static inline pte_t pte_mkprivileged(pte_t pte) |
682 | { | |
1b2443a5 | 683 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); |
daba7902 CL |
684 | } |
685 | ||
686 | static inline pte_t pte_mkuser(pte_t pte) | |
687 | { | |
1b2443a5 | 688 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); |
ebd31197 OH |
689 | } |
690 | ||
c9c98bc5 OH |
691 | /* |
692 | * This is potentially called with a pmd as the argument, in which case it's not | |
693 | * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. | |
694 | * That's because the bit we use for _PAGE_DEVMAP is not reserved for software | |
695 | * use in page directory entries (ie. non-ptes). | |
696 | */ | |
ebd31197 OH |
697 | static inline int pte_devmap(pte_t pte) |
698 | { | |
c9c98bc5 OH |
699 | u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); |
700 | ||
701 | return (pte_raw(pte) & mask) == mask; | |
ebd31197 OH |
702 | } |
703 | ||
13f829a5 AK |
704 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
705 | { | |
706 | /* FIXME!! check whether this need to be a conditional */ | |
1b2443a5 CL |
707 | return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | |
708 | cpu_to_be64(pgprot_val(newprot))); | |
34fbadd8 AK |
709 | } |
710 | ||
711 | /* Encode and de-code a swap entry */ | |
712 | #define MAX_SWAPFILES_CHECK() do { \ | |
713 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
714 | /* \ | |
715 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
716 | * We filter HPTEFLAGS on set_pte. \ | |
717 | */ \ | |
718 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ | |
719 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ | |
720 | } while (0) | |
3159f943 | 721 | |
34fbadd8 AK |
722 | #define SWP_TYPE_BITS 5 |
723 | #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ | |
724 | & ((1UL << SWP_TYPE_BITS) - 1)) | |
725 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) | |
726 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
727 | ((type) << _PAGE_BIT_SWAP_TYPE) \ | |
728 | | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) | |
729 | /* | |
730 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
731 | * swap type and offset we get from swap and convert that to pte to find a | |
732 | * matching pte in linux page table. | |
733 | * Clear bits not found in swap entries here. | |
734 | */ | |
735 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
736 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
a0820ff3 AK |
737 | #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) |
738 | #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) | |
34fbadd8 AK |
739 | |
740 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
741 | #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) | |
742 | #else | |
743 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
744 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
745 | ||
746 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
747 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
748 | { | |
1b2443a5 | 749 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 750 | } |
66c570f5 | 751 | |
34fbadd8 AK |
752 | static inline bool pte_swp_soft_dirty(pte_t pte) |
753 | { | |
66c570f5 | 754 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 755 | } |
66c570f5 | 756 | |
34fbadd8 AK |
757 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) |
758 | { | |
1b2443a5 | 759 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 AK |
760 | } |
761 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
762 | ||
763 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) | |
764 | { | |
765 | /* | |
766 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
767 | */ | |
768 | if (access & ~ptev) | |
769 | return false; | |
770 | /* | |
771 | * This check for access to privilege space | |
772 | */ | |
773 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
774 | return false; | |
775 | ||
776 | return true; | |
777 | } | |
ac94ac79 AK |
778 | /* |
779 | * Generic functions with hash/radix callbacks | |
780 | */ | |
781 | ||
e4c1112c | 782 | static inline void __ptep_set_access_flags(struct vm_area_struct *vma, |
b3603e17 | 783 | pte_t *ptep, pte_t entry, |
e4c1112c AK |
784 | unsigned long address, |
785 | int psize) | |
ac94ac79 AK |
786 | { |
787 | if (radix_enabled()) | |
e4c1112c AK |
788 | return radix__ptep_set_access_flags(vma, ptep, entry, |
789 | address, psize); | |
ac94ac79 AK |
790 | return hash__ptep_set_access_flags(ptep, entry); |
791 | } | |
792 | ||
793 | #define __HAVE_ARCH_PTE_SAME | |
794 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
795 | { | |
796 | if (radix_enabled()) | |
797 | return radix__pte_same(pte_a, pte_b); | |
798 | return hash__pte_same(pte_a, pte_b); | |
799 | } | |
800 | ||
801 | static inline int pte_none(pte_t pte) | |
802 | { | |
803 | if (radix_enabled()) | |
804 | return radix__pte_none(pte); | |
805 | return hash__pte_none(pte); | |
806 | } | |
807 | ||
808 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
809 | pte_t *ptep, pte_t pte, int percpu) | |
810 | { | |
811 | if (radix_enabled()) | |
812 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
813 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
814 | } | |
34fbadd8 | 815 | |
865a9432 | 816 | #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
13f829a5 AK |
817 | |
818 | #define pgprot_noncached pgprot_noncached | |
819 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
820 | { | |
821 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
822 | _PAGE_NON_IDEMPOTENT); | |
823 | } | |
824 | ||
825 | #define pgprot_noncached_wc pgprot_noncached_wc | |
826 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
827 | { | |
828 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
829 | _PAGE_TOLERANT); | |
830 | } | |
831 | ||
832 | #define pgprot_cached pgprot_cached | |
833 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
834 | { | |
835 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
836 | } | |
837 | ||
838 | #define pgprot_writecombine pgprot_writecombine | |
839 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
840 | { | |
841 | return pgprot_noncached_wc(prot); | |
842 | } | |
843 | /* | |
844 | * check a pte mapping have cache inhibited property | |
845 | */ | |
846 | static inline bool pte_ci(pte_t pte) | |
847 | { | |
1b2443a5 | 848 | __be64 pte_v = pte_raw(pte); |
13f829a5 | 849 | |
1b2443a5 CL |
850 | if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || |
851 | ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) | |
13f829a5 AK |
852 | return true; |
853 | return false; | |
854 | } | |
855 | ||
f281b5d5 AK |
856 | static inline void pmd_clear(pmd_t *pmdp) |
857 | { | |
858 | *pmdp = __pmd(0); | |
859 | } | |
860 | ||
66c570f5 AK |
861 | static inline int pmd_none(pmd_t pmd) |
862 | { | |
863 | return !pmd_raw(pmd); | |
864 | } | |
865 | ||
866 | static inline int pmd_present(pmd_t pmd) | |
867 | { | |
da7ad366 AK |
868 | /* |
869 | * A pmd is considerent present if _PAGE_PRESENT is set. | |
870 | * We also need to consider the pmd present which is marked | |
871 | * invalid during a split. Hence we look for _PAGE_INVALID | |
872 | * if we find _PAGE_PRESENT cleared. | |
873 | */ | |
874 | if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) | |
875 | return true; | |
66c570f5 | 876 | |
da7ad366 | 877 | return false; |
66c570f5 | 878 | } |
3dfcb315 | 879 | |
ac94ac79 AK |
880 | static inline int pmd_bad(pmd_t pmd) |
881 | { | |
882 | if (radix_enabled()) | |
883 | return radix__pmd_bad(pmd); | |
884 | return hash__pmd_bad(pmd); | |
885 | } | |
886 | ||
f281b5d5 AK |
887 | static inline void pud_clear(pud_t *pudp) |
888 | { | |
889 | *pudp = __pud(0); | |
890 | } | |
891 | ||
66c570f5 AK |
892 | static inline int pud_none(pud_t pud) |
893 | { | |
894 | return !pud_raw(pud); | |
895 | } | |
896 | ||
897 | static inline int pud_present(pud_t pud) | |
898 | { | |
a5800762 | 899 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 900 | } |
3dfcb315 AK |
901 | |
902 | extern struct page *pud_page(pud_t pud); | |
371352ca | 903 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
904 | static inline pte_t pud_pte(pud_t pud) |
905 | { | |
66c570f5 | 906 | return __pte_raw(pud_raw(pud)); |
3dfcb315 AK |
907 | } |
908 | ||
909 | static inline pud_t pte_pud(pte_t pte) | |
910 | { | |
66c570f5 | 911 | return __pud_raw(pte_raw(pte)); |
3dfcb315 AK |
912 | } |
913 | #define pud_write(pud) pte_write(pud_pte(pud)) | |
ac94ac79 AK |
914 | |
915 | static inline int pud_bad(pud_t pud) | |
916 | { | |
917 | if (radix_enabled()) | |
918 | return radix__pud_bad(pud); | |
919 | return hash__pud_bad(pud); | |
920 | } | |
921 | ||
f72a85e3 AK |
922 | #define pud_access_permitted pud_access_permitted |
923 | static inline bool pud_access_permitted(pud_t pud, bool write) | |
924 | { | |
925 | return pte_access_permitted(pud_pte(pud), write); | |
926 | } | |
ac94ac79 | 927 | |
3dfcb315 AK |
928 | #define pgd_write(pgd) pte_write(pgd_pte(pgd)) |
929 | ||
368ced78 AK |
930 | static inline void pgd_clear(pgd_t *pgdp) |
931 | { | |
932 | *pgdp = __pgd(0); | |
933 | } | |
934 | ||
66c570f5 AK |
935 | static inline int pgd_none(pgd_t pgd) |
936 | { | |
937 | return !pgd_raw(pgd); | |
938 | } | |
939 | ||
940 | static inline int pgd_present(pgd_t pgd) | |
941 | { | |
a5800762 | 942 | return !!(pgd_raw(pgd) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 943 | } |
368ced78 AK |
944 | |
945 | static inline pte_t pgd_pte(pgd_t pgd) | |
946 | { | |
66c570f5 | 947 | return __pte_raw(pgd_raw(pgd)); |
368ced78 AK |
948 | } |
949 | ||
950 | static inline pgd_t pte_pgd(pte_t pte) | |
951 | { | |
66c570f5 | 952 | return __pgd_raw(pte_raw(pte)); |
368ced78 AK |
953 | } |
954 | ||
ac94ac79 AK |
955 | static inline int pgd_bad(pgd_t pgd) |
956 | { | |
957 | if (radix_enabled()) | |
958 | return radix__pgd_bad(pgd); | |
959 | return hash__pgd_bad(pgd); | |
960 | } | |
961 | ||
f72a85e3 AK |
962 | #define pgd_access_permitted pgd_access_permitted |
963 | static inline bool pgd_access_permitted(pgd_t pgd, bool write) | |
964 | { | |
965 | return pte_access_permitted(pgd_pte(pgd), write); | |
966 | } | |
967 | ||
368ced78 AK |
968 | extern struct page *pgd_page(pgd_t pgd); |
969 | ||
aba480e1 AK |
970 | /* Pointers in the page table tree are physical addresses */ |
971 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
972 | ||
973 | #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) | |
974 | #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) | |
975 | #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) | |
976 | ||
977 | #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) | |
978 | #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) | |
979 | #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) | |
980 | #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) | |
981 | ||
3dfcb315 AK |
982 | /* |
983 | * Find an entry in a page-table-directory. We combine the address region | |
984 | * (the high order N bits) and the pgd portion of the address. | |
985 | */ | |
3dfcb315 AK |
986 | |
987 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
988 | ||
368ced78 AK |
989 | #define pud_offset(pgdp, addr) \ |
990 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) | |
3dfcb315 | 991 | #define pmd_offset(pudp,addr) \ |
371352ca | 992 | (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) |
3dfcb315 | 993 | #define pte_offset_kernel(dir,addr) \ |
371352ca | 994 | (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) |
3dfcb315 AK |
995 | |
996 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
bff25143 QC |
997 | |
998 | static inline void pte_unmap(pte_t *pte) { } | |
3dfcb315 AK |
999 | |
1000 | /* to find an entry in a kernel page-table-directory */ | |
1001 | /* This now only contains the vmalloc pages */ | |
1002 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
3dfcb315 AK |
1003 | |
1004 | #define pte_ERROR(e) \ | |
1005 | pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | |
1006 | #define pmd_ERROR(e) \ | |
1007 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
1008 | #define pud_ERROR(e) \ |
1009 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
1010 | #define pgd_ERROR(e) \ |
1011 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
1012 | ||
c766ee72 | 1013 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) |
7207f436 | 1014 | { |
d9225ad9 AK |
1015 | if (radix_enabled()) { |
1016 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
1017 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
1018 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
1019 | #endif | |
c766ee72 | 1020 | return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); |
d9225ad9 | 1021 | } |
c766ee72 | 1022 | return hash__map_kernel_page(ea, pa, prot); |
7207f436 | 1023 | } |
31a14fae AK |
1024 | |
1025 | static inline int __meminit vmemmap_create_mapping(unsigned long start, | |
1026 | unsigned long page_size, | |
1027 | unsigned long phys) | |
7207f436 | 1028 | { |
d9225ad9 AK |
1029 | if (radix_enabled()) |
1030 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 1031 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 1032 | } |
31a14fae AK |
1033 | |
1034 | #ifdef CONFIG_MEMORY_HOTPLUG | |
1035 | static inline void vmemmap_remove_mapping(unsigned long start, | |
1036 | unsigned long page_size) | |
7207f436 | 1037 | { |
d9225ad9 AK |
1038 | if (radix_enabled()) |
1039 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 1040 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 1041 | } |
31a14fae | 1042 | #endif |
3dfcb315 | 1043 | |
3dfcb315 AK |
1044 | static inline pte_t pmd_pte(pmd_t pmd) |
1045 | { | |
66c570f5 | 1046 | return __pte_raw(pmd_raw(pmd)); |
3dfcb315 AK |
1047 | } |
1048 | ||
1049 | static inline pmd_t pte_pmd(pte_t pte) | |
1050 | { | |
66c570f5 | 1051 | return __pmd_raw(pte_raw(pte)); |
3dfcb315 AK |
1052 | } |
1053 | ||
1054 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
1055 | { | |
1056 | return (pte_t *)pmd; | |
1057 | } | |
3dfcb315 AK |
1058 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
1059 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
1060 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
1061 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
1062 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
1063 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 1064 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 AK |
1065 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
1066 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
c137a275 AK |
1067 | #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) |
1068 | #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) | |
7207f436 LD |
1069 | |
1070 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
1071 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
1072 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
1073 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
a0820ff3 AK |
1074 | |
1075 | #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION | |
1076 | #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) | |
1077 | #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) | |
1078 | #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) | |
1079 | #endif | |
7207f436 LD |
1080 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ |
1081 | ||
1ca72129 AK |
1082 | #ifdef CONFIG_NUMA_BALANCING |
1083 | static inline int pmd_protnone(pmd_t pmd) | |
1084 | { | |
1085 | return pte_protnone(pmd_pte(pmd)); | |
1086 | } | |
1087 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 | 1088 | |
3dfcb315 | 1089 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
d19469e8 | 1090 | #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) |
c137a275 | 1091 | #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) |
3dfcb315 | 1092 | |
f72a85e3 AK |
1093 | #define pmd_access_permitted pmd_access_permitted |
1094 | static inline bool pmd_access_permitted(pmd_t pmd, bool write) | |
1095 | { | |
1096 | return pte_access_permitted(pmd_pte(pmd), write); | |
1097 | } | |
1098 | ||
6a1ea362 AK |
1099 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1100 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
1101 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); | |
1102 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
1103 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1104 | pmd_t *pmdp, pmd_t pmd); | |
1105 | extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, | |
1106 | pmd_t *pmd); | |
3df33f12 AK |
1107 | extern int hash__has_transparent_hugepage(void); |
1108 | static inline int has_transparent_hugepage(void) | |
1109 | { | |
bde3eb62 AK |
1110 | if (radix_enabled()) |
1111 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
1112 | return hash__has_transparent_hugepage(); |
1113 | } | |
c04a5880 | 1114 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 1115 | |
3df33f12 AK |
1116 | static inline unsigned long |
1117 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
1118 | unsigned long clr, unsigned long set) | |
3dfcb315 | 1119 | { |
bde3eb62 AK |
1120 | if (radix_enabled()) |
1121 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
1122 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
1123 | } | |
1124 | ||
8890e033 AK |
1125 | /* |
1126 | * returns true for pmd migration entries, THP, devmap, hugetlb | |
1127 | * But compile time dependent on THP config | |
1128 | */ | |
3df33f12 AK |
1129 | static inline int pmd_large(pmd_t pmd) |
1130 | { | |
66c570f5 | 1131 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); |
3df33f12 AK |
1132 | } |
1133 | ||
1134 | static inline pmd_t pmd_mknotpresent(pmd_t pmd) | |
1135 | { | |
1136 | return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); | |
1137 | } | |
1138 | /* | |
1139 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
1140 | * the below will work for radix too | |
1141 | */ | |
1142 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
1143 | unsigned long addr, pmd_t *pmdp) | |
1144 | { | |
1145 | unsigned long old; | |
1146 | ||
66c570f5 | 1147 | if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
3df33f12 AK |
1148 | return 0; |
1149 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
1150 | return ((old & _PAGE_ACCESSED) != 0); | |
1151 | } | |
1152 | ||
1153 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
1154 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1155 | pmd_t *pmdp) | |
1156 | { | |
d19469e8 | 1157 | if (__pmd_write((*pmdp))) |
52c50ca7 AK |
1158 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); |
1159 | else if (unlikely(pmd_savedwrite(*pmdp))) | |
1160 | pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); | |
3dfcb315 AK |
1161 | } |
1162 | ||
8890e033 AK |
1163 | /* |
1164 | * Only returns true for a THP. False for pmd migration entry. | |
1165 | * We also need to return true when we come across a pte that | |
1166 | * in between a thp split. While splitting THP, we mark the pmd | |
1167 | * invalid (pmdp_invalidate()) before we set it with pte page | |
1168 | * address. A pmd_trans_huge() check against a pmd entry during that time | |
1169 | * should return true. | |
1170 | * We should not call this on a hugetlb entry. We should check for HugeTLB | |
1171 | * entry using vma->vm_flags | |
1172 | * The page table walk rule is explained in Documentation/vm/transhuge.rst | |
1173 | */ | |
ab624762 AK |
1174 | static inline int pmd_trans_huge(pmd_t pmd) |
1175 | { | |
8890e033 AK |
1176 | if (!pmd_present(pmd)) |
1177 | return false; | |
1178 | ||
ab624762 AK |
1179 | if (radix_enabled()) |
1180 | return radix__pmd_trans_huge(pmd); | |
1181 | return hash__pmd_trans_huge(pmd); | |
1182 | } | |
1183 | ||
1184 | #define __HAVE_ARCH_PMD_SAME | |
1185 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
1186 | { | |
1187 | if (radix_enabled()) | |
1188 | return radix__pmd_same(pmd_a, pmd_b); | |
1189 | return hash__pmd_same(pmd_a, pmd_b); | |
1190 | } | |
1191 | ||
3dfcb315 AK |
1192 | static inline pmd_t pmd_mkhuge(pmd_t pmd) |
1193 | { | |
ab624762 AK |
1194 | if (radix_enabled()) |
1195 | return radix__pmd_mkhuge(pmd); | |
1196 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
1197 | } |
1198 | ||
3dfcb315 AK |
1199 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1200 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1201 | unsigned long address, pmd_t *pmdp, | |
1202 | pmd_t entry, int dirty); | |
1203 | ||
3dfcb315 AK |
1204 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1205 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1206 | unsigned long address, pmd_t *pmdp); | |
3dfcb315 AK |
1207 | |
1208 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
1209 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
1210 | unsigned long addr, pmd_t *pmdp) | |
1211 | { | |
bde3eb62 AK |
1212 | if (radix_enabled()) |
1213 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
1214 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
1215 | } | |
3dfcb315 | 1216 | |
3df33f12 AK |
1217 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1218 | unsigned long address, pmd_t *pmdp) | |
1219 | { | |
bde3eb62 AK |
1220 | if (radix_enabled()) |
1221 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
1222 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
1223 | } | |
3dfcb315 AK |
1224 | #define pmdp_collapse_flush pmdp_collapse_flush |
1225 | ||
1226 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
3df33f12 AK |
1227 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
1228 | pmd_t *pmdp, pgtable_t pgtable) | |
1229 | { | |
bde3eb62 AK |
1230 | if (radix_enabled()) |
1231 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
1232 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
1233 | } | |
1234 | ||
3dfcb315 | 1235 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
1236 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
1237 | pmd_t *pmdp) | |
1238 | { | |
bde3eb62 AK |
1239 | if (radix_enabled()) |
1240 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
1241 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
1242 | } | |
3dfcb315 AK |
1243 | |
1244 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
8cc931e0 AK |
1245 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, |
1246 | pmd_t *pmdp); | |
3dfcb315 AK |
1247 | |
1248 | #define pmd_move_must_withdraw pmd_move_must_withdraw | |
1249 | struct spinlock; | |
579b9239 AK |
1250 | extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, |
1251 | struct spinlock *old_pmd_ptl, | |
1252 | struct vm_area_struct *vma); | |
1253 | /* | |
1254 | * Hash translation mode use the deposited table to store hash pte | |
1255 | * slot information. | |
1256 | */ | |
953c66c2 AK |
1257 | #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit |
1258 | static inline bool arch_needs_pgtable_deposit(void) | |
1259 | { | |
1260 | if (radix_enabled()) | |
1261 | return false; | |
1262 | return true; | |
1263 | } | |
fa4531f7 | 1264 | extern void serialize_against_pte_lookup(struct mm_struct *mm); |
953c66c2 | 1265 | |
ebd31197 OH |
1266 | |
1267 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) | |
1268 | { | |
1269 | return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP)); | |
1270 | } | |
1271 | ||
1272 | static inline int pmd_devmap(pmd_t pmd) | |
1273 | { | |
1274 | return pte_devmap(pmd_pte(pmd)); | |
1275 | } | |
1276 | ||
1277 | static inline int pud_devmap(pud_t pud) | |
1278 | { | |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | static inline int pgd_devmap(pgd_t pgd) | |
1283 | { | |
1284 | return 0; | |
1285 | } | |
6a1ea362 | 1286 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
ebd31197 | 1287 | |
c516886f | 1288 | static inline int pud_pfn(pud_t pud) |
ebd31197 OH |
1289 | { |
1290 | /* | |
1291 | * Currently all calls to pud_pfn() are gated around a pud_devmap() | |
1292 | * check so this should never be used. If it grows another user we | |
1293 | * want to know about it. | |
1294 | */ | |
1295 | BUILD_BUG(); | |
1296 | return 0; | |
1297 | } | |
5b323367 AK |
1298 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1299 | pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); | |
1300 | void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, | |
1301 | pte_t *, pte_t, pte_t); | |
1302 | ||
1303 | /* | |
1304 | * Returns true for a R -> RW upgrade of pte | |
1305 | */ | |
1306 | static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) | |
1307 | { | |
1308 | if (!(old_val & _PAGE_READ)) | |
1309 | return false; | |
1310 | ||
1311 | if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) | |
1312 | return true; | |
1313 | ||
1314 | return false; | |
1315 | } | |
029d9252 | 1316 | |
3dfcb315 AK |
1317 | #endif /* __ASSEMBLY__ */ |
1318 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |