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powerpc/mm: Implement helpers for pagetable fragment support at PMD level
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
3dfcb315
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519 4
9849a569
KS		 5#include <asm-generic/5level-fixup.h>
6
c137a275
AK		 7#ifndef __ASSEMBLY__
8#include <linux/mmdebug.h>
ebd31197 9#include <linux/bug.h>
c137a275 10#endif
9849a569 11
2e873519
AK		 12/*
13 * Common bits between hash and Radix page table
14 */
15#define _PAGE_BIT_SWAP_TYPE 0
16
35175033 17#define _PAGE_NA 0
6b8cb66a 18#define _PAGE_RO 0
812fadcb 19#define _PAGE_USER 0
6b8cb66a 20
2e873519
AK		 21#define _PAGE_EXEC 0x00001 /* execute permission */
22#define _PAGE_WRITE 0x00002 /* write access allowed */
23#define _PAGE_READ 0x00004 /* read access allowed */
24#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
25#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
26#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
27#define _PAGE_SAO 0x00010 /* Strong access order */
28#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
29#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
30#define _PAGE_DIRTY 0x00080 /* C: page changed */
31#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 32/*
2e873519 33 * Software bits
3dfcb315 34 */
69dfbaeb
AK		 35#define _RPAGE_SW0 0x2000000000000000UL
36#define _RPAGE_SW1 0x00800
37#define _RPAGE_SW2 0x00400
38#define _RPAGE_SW3 0x00200
049d567a
AK		 39#define _RPAGE_RSV1 0x1000000000000000UL
40#define _RPAGE_RSV2 0x0800000000000000UL
41#define _RPAGE_RSV3 0x0400000000000000UL
42#define _RPAGE_RSV4 0x0200000000000000UL
eb95d016 43#define _RPAGE_RSV5 0x00040UL
6aa59f51
AK		 44
45#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
46#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
47
48/*
49 * Top and bottom bits of RPN which can be used by hash
50 * translation mode, because we expect them to be zero
51 * otherwise.
52 */
32789d38
AK		 53#define _RPAGE_RPN0 0x01000
54#define _RPAGE_RPN1 0x02000
6aa59f51
AK		 55#define _RPAGE_RPN44 0x0100000000000000UL
56#define _RPAGE_RPN43 0x0080000000000000UL
57#define _RPAGE_RPN42 0x0040000000000000UL
58#define _RPAGE_RPN41 0x0020000000000000UL
049d567a 59
2f18d533
AK		 60/* Max physical address bit as per radix table */
61#define _RPAGE_PA_MAX 57
62
63/*
64 * Max physical address bit we will use for now.
65 *
66 * This is mostly a hardware limitation and for now Power9 has
67 * a 51 bit limit.
68 *
69 * This is different from the number of physical bit required to address
70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
72 * number of sections we can support (SECTIONS_SHIFT).
73 *
74 * This is different from Radix page table limitation above and
75 * should always be less than that. The limit is done such that
76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
77 * for hash linux page table specific bits.
78 *
79 * In order to be compatible with future hardware generations we keep
80 * some offsets and limit this for now to 53
81 */
82#define _PAGE_PA_MAX 53
83
69dfbaeb 84#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
69dfbaeb 85#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
ebd31197
OH		 86#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
87#define __HAVE_ARCH_PTE_DEVMAP
88
2e873519
AK		 89/*
90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
91 * Instead of fixing all of them, add an alternate define which
92 * maps CI pte mapping.
93 */
94#define _PAGE_NO_CACHE _PAGE_TOLERANT
95/*
2f18d533
AK		 96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
98 * and every thing below PAGE_SHIFT;
2e873519 99 */
2f18d533 100#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
2e873519
AK		 101/*
102 * set of bits not changed in pmd_modify. Even though we have hash specific bits
103 * in here, on radix we expect them to be zero.
104 */
105#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
107 _PAGE_SOFT_DIRTY)
108/*
109 * user access blocked by key
110 */
111#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
112#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
113#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
114 _PAGE_RW | _PAGE_EXEC)
115/*
116 * No page size encoding in the linux PTE
117 */
118#define _PAGE_PSIZE 0
119/*
120 * _PAGE_CHG_MASK masks of bits that are to be preserved across
121 * pgprot changes
122 */
123#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
125 _PAGE_SOFT_DIRTY)
eb95d016
RP		 126
127#define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \
128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4)
2e873519
AK		 129/*
130 * Mask of bits returned by pte_pgprot()
131 */
132#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
eb95d016 135 _PAGE_SOFT_DIRTY | H_PTE_PKEY)
3dfcb315 136/*
2e873519
AK		 137 * We define 2 sets of base prot bits, one for basic pages (ie,
138 * cacheable kernel and user pages) and one for non cacheable
139 * pages. We always set _PAGE_COHERENT when SMP is enabled or
140 * the processor might need it for DMA coherency.
3dfcb315 141 */
2e873519
AK		 142#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
143#define _PAGE_BASE (_PAGE_BASE_NC)
144
145/* Permission masks used to generate the __P and __S table,
146 *
147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
148 *
149 * Write permissions imply read permissions for now (we could make write-only
150 * pages on BookE but we don't bother for now). Execute permission control is
151 * possible on platforms that define _PAGE_EXEC
152 *
153 * Note due to the way vm flags are laid out, the bits are XWR
154 */
155#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
156#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
157#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
158#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
159#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
160#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
161#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
162
163#define __P000 PAGE_NONE
164#define __P001 PAGE_READONLY
165#define __P010 PAGE_COPY
166#define __P011 PAGE_COPY
167#define __P100 PAGE_READONLY_X
168#define __P101 PAGE_READONLY_X
169#define __P110 PAGE_COPY_X
170#define __P111 PAGE_COPY_X
171
172#define __S000 PAGE_NONE
173#define __S001 PAGE_READONLY
174#define __S010 PAGE_SHARED
175#define __S011 PAGE_SHARED
176#define __S100 PAGE_READONLY_X
177#define __S101 PAGE_READONLY_X
178#define __S110 PAGE_SHARED_X
179#define __S111 PAGE_SHARED_X
180
181/* Permission masks used for kernel mappings */
182#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
183#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
184 _PAGE_TOLERANT)
185#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
186 _PAGE_NON_IDEMPOTENT)
187#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
188#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
189#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
190
191/*
192 * Protection used for kernel text. We want the debuggers to be able to
193 * set breakpoints anywhere, so don't write protect the kernel text
194 * on platforms where such control is possible.
195 */
196#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
198#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
199#else
200#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
201#endif
202
203/* Make modules code happy. We don't set RO yet */
204#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
205#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 206
dd1842a2
AK		 207#ifndef __ASSEMBLY__
208/*
209 * page table defines
210 */
211extern unsigned long __pte_index_size;
212extern unsigned long __pmd_index_size;
213extern unsigned long __pud_index_size;
214extern unsigned long __pgd_index_size;
215extern unsigned long __pmd_cache_index;
fae22116 216extern unsigned long __pud_cache_index;
dd1842a2
AK		 217#define PTE_INDEX_SIZE __pte_index_size
218#define PMD_INDEX_SIZE __pmd_index_size
219#define PUD_INDEX_SIZE __pud_index_size
220#define PGD_INDEX_SIZE __pgd_index_size
221#define PMD_CACHE_INDEX __pmd_cache_index
fae22116 222#define PUD_CACHE_INDEX __pud_cache_index
dd1842a2
AK		 223/*
224 * Because of use of pte fragments and THP, size of page table
225 * are not always derived out of index size above.
226 */
227extern unsigned long __pte_table_size;
228extern unsigned long __pmd_table_size;
229extern unsigned long __pud_table_size;
230extern unsigned long __pgd_table_size;
231#define PTE_TABLE_SIZE __pte_table_size
232#define PMD_TABLE_SIZE __pmd_table_size
233#define PUD_TABLE_SIZE __pud_table_size
234#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 235
236extern unsigned long __pmd_val_bits;
237extern unsigned long __pud_val_bits;
238extern unsigned long __pgd_val_bits;
239#define PMD_VAL_BITS __pmd_val_bits
240#define PUD_VAL_BITS __pud_val_bits
241#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 242
243extern unsigned long __pte_frag_nr;
244#define PTE_FRAG_NR __pte_frag_nr
245extern unsigned long __pte_frag_size_shift;
246#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
247#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2 248
8a6c697b
AK		 249extern unsigned long __pmd_frag_nr;
250#define PMD_FRAG_NR __pmd_frag_nr
251extern unsigned long __pmd_frag_size_shift;
252#define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
253#define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
254
dd1842a2
AK		 255#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
256#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
257#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
258#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
259
260/* PMD_SHIFT determines what a second-level page table entry can map */
261#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
262#define PMD_SIZE (1UL << PMD_SHIFT)
263#define PMD_MASK (~(PMD_SIZE-1))
264
265/* PUD_SHIFT determines what a third-level page table entry can map */
266#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
267#define PUD_SIZE (1UL << PUD_SHIFT)
268#define PUD_MASK (~(PUD_SIZE-1))
269
270/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
271#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
272#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
273#define PGDIR_MASK (~(PGDIR_SIZE-1))
274
275/* Bits to mask out from a PMD to get to the PTE page */
276#define PMD_MASKED_BITS 0xc0000000000000ffUL
277/* Bits to mask out from a PUD to get to the PMD page */
278#define PUD_MASKED_BITS 0xc0000000000000ffUL
279/* Bits to mask out from a PGD to get to the PUD page */
280#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e 281
0c4d2680
AK		 282/*
283 * Used as an indicator for rcu callback functions
284 */
285enum pgtable_index {
286 PTE_INDEX = 0,
287 PMD_INDEX,
288 PUD_INDEX,
289 PGD_INDEX,
290};
291
d6a9996e
AK		 292extern unsigned long __vmalloc_start;
293extern unsigned long __vmalloc_end;
294#define VMALLOC_START __vmalloc_start
295#define VMALLOC_END __vmalloc_end
296
297extern unsigned long __kernel_virt_start;
298extern unsigned long __kernel_virt_size;
63ee9b2f 299extern unsigned long __kernel_io_start;
d6a9996e
AK		 300#define KERN_VIRT_START __kernel_virt_start
301#define KERN_VIRT_SIZE __kernel_virt_size
63ee9b2f 302#define KERN_IO_START __kernel_io_start
d6a9996e
AK		 303extern struct page *vmemmap;
304extern unsigned long ioremap_bot;
bfa37087 305extern unsigned long pci_io_base;
dd1842a2 306#endif /* __ASSEMBLY__ */
3dfcb315 307
ab537dca 308#include <asm/book3s/64/hash.h>
b0b5e9b1 309#include <asm/book3s/64/radix.h>
3dfcb315 310
a9252aae
AK		 311#ifdef CONFIG_PPC_64K_PAGES
312#include <asm/book3s/64/pgtable-64k.h>
313#else
314#include <asm/book3s/64/pgtable-4k.h>
315#endif
316
3dfcb315 317#include <asm/barrier.h>
3dfcb315
AK		 318/*
319 * The second half of the kernel virtual space is used for IO mappings,
320 * it's itself carved into the PIO region (ISA and PHB IO space) and
321 * the ioremap space
322 *
323 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
324 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
325 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
326 */
3dfcb315
AK		 327#define FULL_IO_SIZE 0x80000000ul
328#define ISA_IO_BASE (KERN_IO_START)
329#define ISA_IO_END (KERN_IO_START + 0x10000ul)
330#define PHB_IO_BASE (ISA_IO_END)
331#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
332#define IOREMAP_BASE (PHB_IO_END)
333#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
334
b0412ea9 335/* Advertise special mapping type for AGP */
b0412ea9
AK		 336#define HAVE_PAGE_AGP
337
338/* Advertise support for _PAGE_SPECIAL */
339#define __HAVE_ARCH_PTE_SPECIAL
340
3dfcb315
AK		 341#ifndef __ASSEMBLY__
342
343/*
344 * This is the default implementation of various PTE accessors, it's
345 * used in all cases except Book3S with 64K pages where we have a
346 * concept of sub-pages
347 */
348#ifndef __real_pte
349
ff31e105 350#define __real_pte(e, p, o) ((real_pte_t){(e)})
3dfcb315 351#define __rpte_to_pte(r) ((r).pte)
945537df 352#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 353
354#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
355 do { \
356 index = 0; \
357 shift = mmu_psize_defs[psize].shift; \
358
359#define pte_iterate_hashed_end() } while(0)
360
361/*
362 * We expect this to be called only for user addresses or kernel virtual
363 * addresses other than the linear mapping.
364 */
365#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
366
367#endif /* __real_pte */
368
ac94ac79
AK		 369static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
370 pte_t *ptep, unsigned long clr,
371 unsigned long set, int huge)
372{
373 if (radix_enabled())
374 return radix__pte_update(mm, addr, ptep, clr, set, huge);
375 return hash__pte_update(mm, addr, ptep, clr, set, huge);
376}
13f829a5
AK		 377/*
378 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
379 * We currently remove entries from the hashtable regardless of whether
380 * the entry was young or dirty.
381 *
382 * We should be more intelligent about this but for the moment we override
383 * these functions and force a tlb flush unconditionally
384 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
385 * function for both hash and radix.
386 */
387static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
388 unsigned long addr, pte_t *ptep)
389{
390 unsigned long old;
391
66c570f5 392 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 393 return 0;
394 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
395 return (old & _PAGE_ACCESSED) != 0;
396}
397
398#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
399#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
400({ \
401 int __r; \
402 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
403 __r; \
404})
405
d19469e8 406static inline int __pte_write(pte_t pte)
52c50ca7
AK		 407{
408 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
409}
410
411#ifdef CONFIG_NUMA_BALANCING
412#define pte_savedwrite pte_savedwrite
413static inline bool pte_savedwrite(pte_t pte)
414{
415 /*
416 * Saved write ptes are prot none ptes that doesn't have
417 * privileged bit sit. We mark prot none as one which has
418 * present and pviliged bit set and RWX cleared. To mark
419 * protnone which used to have _PAGE_WRITE set we clear
420 * the privileged bit.
421 */
422 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
423}
424#else
425#define pte_savedwrite pte_savedwrite
426static inline bool pte_savedwrite(pte_t pte)
427{
428 return false;
429}
430#endif
431
d19469e8
AK		 432static inline int pte_write(pte_t pte)
433{
434 return __pte_write(pte) || pte_savedwrite(pte);
435}
436
ca8afd40
CL		 437static inline int pte_read(pte_t pte)
438{
439 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
440}
441
13f829a5
AK		 442#define __HAVE_ARCH_PTEP_SET_WRPROTECT
443static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
444 pte_t *ptep)
445{
d19469e8 446 if (__pte_write(*ptep))
52c50ca7
AK		 447 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
448 else if (unlikely(pte_savedwrite(*ptep)))
449 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
13f829a5
AK		 450}
451
452static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
453 unsigned long addr, pte_t *ptep)
454{
52c50ca7
AK		 455 /*
456 * We should not find protnone for hugetlb, but this complete the
457 * interface.
458 */
d19469e8 459 if (__pte_write(*ptep))
52c50ca7
AK		 460 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
461 else if (unlikely(pte_savedwrite(*ptep)))
462 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
13f829a5
AK		 463}
464
465#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
466static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
467 unsigned long addr, pte_t *ptep)
468{
469 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
470 return __pte(old);
471}
472
f4894b80
AK		 473#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
474static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
475 unsigned long addr,
476 pte_t *ptep, int full)
477{
478 if (full && radix_enabled()) {
479 /*
480 * Let's skip the DD1 style pte update here. We know that
481 * this is a full mm pte clear and hence can be sure there is
482 * no parallel set_pte.
483 */
484 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
485 }
486 return ptep_get_and_clear(mm, addr, ptep);
487}
488
489
13f829a5
AK		 490static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
491 pte_t * ptep)
492{
493 pte_update(mm, addr, ptep, ~0UL, 0, 0);
494}
66c570f5 495
66c570f5
AK		 496static inline int pte_dirty(pte_t pte)
497{
498 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
499}
500
501static inline int pte_young(pte_t pte)
502{
503 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
504}
505
506static inline int pte_special(pte_t pte)
507{
508 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
509}
510
13f829a5
AK		 511static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
512
513#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
514static inline bool pte_soft_dirty(pte_t pte)
515{
66c570f5 516 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 517}
66c570f5 518
13f829a5
AK		 519static inline pte_t pte_mksoft_dirty(pte_t pte)
520{
521 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
522}
523
524static inline pte_t pte_clear_soft_dirty(pte_t pte)
525{
526 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
527}
528#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
529
530#ifdef CONFIG_NUMA_BALANCING
13f829a5
AK		 531static inline int pte_protnone(pte_t pte)
532{
c137a275
AK		 533 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
534 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
535}
536
537#define pte_mk_savedwrite pte_mk_savedwrite
538static inline pte_t pte_mk_savedwrite(pte_t pte)
539{
540 /*
541 * Used by Autonuma subsystem to preserve the write bit
542 * while marking the pte PROT_NONE. Only allow this
543 * on PROT_NONE pte
544 */
545 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
546 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
547 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
548}
549
550#define pte_clear_savedwrite pte_clear_savedwrite
551static inline pte_t pte_clear_savedwrite(pte_t pte)
552{
553 /*
554 * Used by KSM subsystem to make a protnone pte readonly.
555 */
556 VM_BUG_ON(!pte_protnone(pte));
557 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
558}
d19469e8
AK		 559#else
560#define pte_clear_savedwrite pte_clear_savedwrite
561static inline pte_t pte_clear_savedwrite(pte_t pte)
562{
563 VM_WARN_ON(1);
564 return __pte(pte_val(pte) & ~_PAGE_WRITE);
565}
13f829a5
AK		 566#endif /* CONFIG_NUMA_BALANCING */
567
568static inline int pte_present(pte_t pte)
569{
66c570f5 570 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
13f829a5 571}
f72a85e3 572
bca7aacf 573#ifdef CONFIG_PPC_MEM_KEYS
f2407ef3 574extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
bca7aacf
RP		 575#else
576static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
577{
578 return true;
579}
580#endif /* CONFIG_PPC_MEM_KEYS */
f2407ef3 581
f72a85e3
AK		 582#define pte_access_permitted pte_access_permitted
583static inline bool pte_access_permitted(pte_t pte, bool write)
584{
585 unsigned long pteval = pte_val(pte);
586 /* Also check for pte_user */
587 unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
588 /*
589 * _PAGE_READ is needed for any access and will be
590 * cleared for PROT_NONE
591 */
592 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
593
594 if (write)
595 need_pte_bits |= _PAGE_WRITE;
596
597 if ((pteval & need_pte_bits) != need_pte_bits)
598 return false;
599
600 if ((pteval & clear_pte_bits) == clear_pte_bits)
601 return false;
bca7aacf
RP		 602
603 return arch_pte_access_permitted(pte_val(pte), write, 0);
f72a85e3
AK		 604}
605
13f829a5
AK		 606/*
607 * Conversion functions: convert a page and protection to a page entry,
608 * and a page entry and page directory to the page they refer to.
609 *
610 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
611 * long for now.
612 */
613static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
614{
615 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
616 pgprot_val(pgprot));
617}
618
619static inline unsigned long pte_pfn(pte_t pte)
620{
621 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
622}
623
624/* Generic modifiers for PTE bits */
625static inline pte_t pte_wrprotect(pte_t pte)
626{
d19469e8
AK		 627 if (unlikely(pte_savedwrite(pte)))
628 return pte_clear_savedwrite(pte);
13f829a5
AK		 629 return __pte(pte_val(pte) & ~_PAGE_WRITE);
630}
631
632static inline pte_t pte_mkclean(pte_t pte)
633{
634 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
635}
636
637static inline pte_t pte_mkold(pte_t pte)
638{
639 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
640}
641
642static inline pte_t pte_mkwrite(pte_t pte)
643{
644 /*
645 * write implies read, hence set both
646 */
647 return __pte(pte_val(pte) | _PAGE_RW);
648}
649
650static inline pte_t pte_mkdirty(pte_t pte)
651{
652 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
653}
654
655static inline pte_t pte_mkyoung(pte_t pte)
656{
657 return __pte(pte_val(pte) | _PAGE_ACCESSED);
658}
659
660static inline pte_t pte_mkspecial(pte_t pte)
661{
662 return __pte(pte_val(pte) | _PAGE_SPECIAL);
663}
664
665static inline pte_t pte_mkhuge(pte_t pte)
666{
667 return pte;
668}
669
ebd31197
OH		 670static inline pte_t pte_mkdevmap(pte_t pte)
671{
672 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
673}
674
c9c98bc5
OH		 675/*
676 * This is potentially called with a pmd as the argument, in which case it's not
677 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
678 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
679 * use in page directory entries (ie. non-ptes).
680 */
ebd31197
OH		 681static inline int pte_devmap(pte_t pte)
682{
c9c98bc5
OH		 683 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
684
685 return (pte_raw(pte) & mask) == mask;
ebd31197
OH		 686}
687
13f829a5
AK		 688static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
689{
690 /* FIXME!! check whether this need to be a conditional */
691 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
692}
693
34fbadd8
AK		 694static inline bool pte_user(pte_t pte)
695{
66c570f5 696 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
34fbadd8
AK		 697}
698
699/* Encode and de-code a swap entry */
700#define MAX_SWAPFILES_CHECK() do { \
701 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
702 /* \
703 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
704 * We filter HPTEFLAGS on set_pte. \
705 */ \
706 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
707 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
708 } while (0)
709/*
710 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
711 */
712#define SWP_TYPE_BITS 5
713#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
714 & ((1UL << SWP_TYPE_BITS) - 1))
715#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
716#define __swp_entry(type, offset) ((swp_entry_t) { \
717 ((type) << _PAGE_BIT_SWAP_TYPE) \
718 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
719/*
720 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
721 * swap type and offset we get from swap and convert that to pte to find a
722 * matching pte in linux page table.
723 * Clear bits not found in swap entries here.
724 */
725#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
726#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
727
728#ifdef CONFIG_MEM_SOFT_DIRTY
729#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
730#else
731#define _PAGE_SWP_SOFT_DIRTY 0UL
732#endif /* CONFIG_MEM_SOFT_DIRTY */
733
734#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
735static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
736{
737 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
738}
66c570f5 739
34fbadd8
AK		 740static inline bool pte_swp_soft_dirty(pte_t pte)
741{
66c570f5 742 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 743}
66c570f5 744
34fbadd8
AK		 745static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
746{
747 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
748}
749#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
750
751static inline bool check_pte_access(unsigned long access, unsigned long ptev)
752{
753 /*
754 * This check for _PAGE_RWX and _PAGE_PRESENT bits
755 */
756 if (access & ~ptev)
757 return false;
758 /*
759 * This check for access to privilege space
760 */
761 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
762 return false;
763
764 return true;
765}
ac94ac79
AK		 766/*
767 * Generic functions with hash/radix callbacks
768 */
769
c6d1a767 770static inline void __ptep_set_access_flags(struct mm_struct *mm,
b3603e17
AK		 771 pte_t *ptep, pte_t entry,
772 unsigned long address)
ac94ac79
AK		 773{
774 if (radix_enabled())
b3603e17 775 return radix__ptep_set_access_flags(mm, ptep, entry, address);
ac94ac79
AK		 776 return hash__ptep_set_access_flags(ptep, entry);
777}
778
779#define __HAVE_ARCH_PTE_SAME
780static inline int pte_same(pte_t pte_a, pte_t pte_b)
781{
782 if (radix_enabled())
783 return radix__pte_same(pte_a, pte_b);
784 return hash__pte_same(pte_a, pte_b);
785}
786
787static inline int pte_none(pte_t pte)
788{
789 if (radix_enabled())
790 return radix__pte_none(pte);
791 return hash__pte_none(pte);
792}
793
794static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
795 pte_t *ptep, pte_t pte, int percpu)
796{
797 if (radix_enabled())
798 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
799 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
800}
34fbadd8 801
13f829a5
AK		 802#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
803
804#define pgprot_noncached pgprot_noncached
805static inline pgprot_t pgprot_noncached(pgprot_t prot)
806{
807 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
808 _PAGE_NON_IDEMPOTENT);
809}
810
811#define pgprot_noncached_wc pgprot_noncached_wc
812static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
813{
814 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
815 _PAGE_TOLERANT);
816}
817
818#define pgprot_cached pgprot_cached
819static inline pgprot_t pgprot_cached(pgprot_t prot)
820{
821 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
822}
823
824#define pgprot_writecombine pgprot_writecombine
825static inline pgprot_t pgprot_writecombine(pgprot_t prot)
826{
827 return pgprot_noncached_wc(prot);
828}
829/*
830 * check a pte mapping have cache inhibited property
831 */
832static inline bool pte_ci(pte_t pte)
833{
834 unsigned long pte_v = pte_val(pte);
835
836 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
837 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
838 return true;
839 return false;
840}
841
f281b5d5
AK		 842static inline void pmd_set(pmd_t *pmdp, unsigned long val)
843{
844 *pmdp = __pmd(val);
845}
846
847static inline void pmd_clear(pmd_t *pmdp)
848{
849 *pmdp = __pmd(0);
850}
851
66c570f5
AK		 852static inline int pmd_none(pmd_t pmd)
853{
854 return !pmd_raw(pmd);
855}
856
857static inline int pmd_present(pmd_t pmd)
858{
859
860 return !pmd_none(pmd);
861}
3dfcb315 862
ac94ac79
AK		 863static inline int pmd_bad(pmd_t pmd)
864{
865 if (radix_enabled())
866 return radix__pmd_bad(pmd);
867 return hash__pmd_bad(pmd);
868}
869
f281b5d5
AK		 870static inline void pud_set(pud_t *pudp, unsigned long val)
871{
872 *pudp = __pud(val);
873}
874
875static inline void pud_clear(pud_t *pudp)
876{
877 *pudp = __pud(0);
878}
879
66c570f5
AK		 880static inline int pud_none(pud_t pud)
881{
882 return !pud_raw(pud);
883}
884
885static inline int pud_present(pud_t pud)
886{
887 return !pud_none(pud);
888}
3dfcb315
AK		 889
890extern struct page *pud_page(pud_t pud);
371352ca 891extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 892static inline pte_t pud_pte(pud_t pud)
893{
66c570f5 894 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 895}
896
897static inline pud_t pte_pud(pte_t pte)
898{
66c570f5 899 return __pud_raw(pte_raw(pte));
3dfcb315
AK		 900}
901#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 902
903static inline int pud_bad(pud_t pud)
904{
905 if (radix_enabled())
906 return radix__pud_bad(pud);
907 return hash__pud_bad(pud);
908}
909
f72a85e3
AK		 910#define pud_access_permitted pud_access_permitted
911static inline bool pud_access_permitted(pud_t pud, bool write)
912{
913 return pte_access_permitted(pud_pte(pud), write);
914}
ac94ac79 915
3dfcb315 916#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 917static inline void pgd_set(pgd_t *pgdp, unsigned long val)
918{
919 *pgdp = __pgd(val);
920}
3dfcb315 921
368ced78
AK		 922static inline void pgd_clear(pgd_t *pgdp)
923{
924 *pgdp = __pgd(0);
925}
926
66c570f5
AK		 927static inline int pgd_none(pgd_t pgd)
928{
929 return !pgd_raw(pgd);
930}
931
932static inline int pgd_present(pgd_t pgd)
933{
934 return !pgd_none(pgd);
935}
368ced78
AK		 936
937static inline pte_t pgd_pte(pgd_t pgd)
938{
66c570f5 939 return __pte_raw(pgd_raw(pgd));
368ced78
AK		 940}
941
942static inline pgd_t pte_pgd(pte_t pte)
943{
66c570f5 944 return __pgd_raw(pte_raw(pte));
368ced78
AK		 945}
946
ac94ac79
AK		 947static inline int pgd_bad(pgd_t pgd)
948{
949 if (radix_enabled())
950 return radix__pgd_bad(pgd);
951 return hash__pgd_bad(pgd);
952}
953
f72a85e3
AK		 954#define pgd_access_permitted pgd_access_permitted
955static inline bool pgd_access_permitted(pgd_t pgd, bool write)
956{
957 return pte_access_permitted(pgd_pte(pgd), write);
958}
959
368ced78
AK		 960extern struct page *pgd_page(pgd_t pgd);
961
aba480e1
AK		 962/* Pointers in the page table tree are physical addresses */
963#define __pgtable_ptr_val(ptr) __pa(ptr)
964
965#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
966#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
967#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
968
969#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
970#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
971#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
972#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
973
3dfcb315
AK		 974/*
975 * Find an entry in a page-table-directory. We combine the address region
976 * (the high order N bits) and the pgd portion of the address.
977 */
3dfcb315
AK		 978
979#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
980
368ced78
AK		 981#define pud_offset(pgdp, addr) \
982 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 983#define pmd_offset(pudp,addr) \
371352ca 984 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 985#define pte_offset_kernel(dir,addr) \
371352ca 986 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 987
988#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
989#define pte_unmap(pte) do { } while(0)
990
991/* to find an entry in a kernel page-table-directory */
992/* This now only contains the vmalloc pages */
993#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 994
995#define pte_ERROR(e) \
996 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
997#define pmd_ERROR(e) \
998 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 999#define pud_ERROR(e) \
1000 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 1001#define pgd_ERROR(e) \
1002 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1003
31a14fae
AK		 1004static inline int map_kernel_page(unsigned long ea, unsigned long pa,
1005 unsigned long flags)
7207f436 1006{
d9225ad9
AK		 1007 if (radix_enabled()) {
1008#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1009 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1010 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1011#endif
1012 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
1013 }
31a14fae 1014 return hash__map_kernel_page(ea, pa, flags);
7207f436 1015}
31a14fae
AK		 1016
1017static inline int __meminit vmemmap_create_mapping(unsigned long start,
1018 unsigned long page_size,
1019 unsigned long phys)
7207f436 1020{
d9225ad9
AK		 1021 if (radix_enabled())
1022 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 1023 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 1024}
31a14fae
AK		 1025
1026#ifdef CONFIG_MEMORY_HOTPLUG
1027static inline void vmemmap_remove_mapping(unsigned long start,
1028 unsigned long page_size)
7207f436 1029{
d9225ad9
AK		 1030 if (radix_enabled())
1031 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 1032 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 1033}
31a14fae 1034#endif
3dfcb315
AK		 1035struct page *realmode_pfn_to_page(unsigned long pfn);
1036
3dfcb315
AK		 1037static inline pte_t pmd_pte(pmd_t pmd)
1038{
66c570f5 1039 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 1040}
1041
1042static inline pmd_t pte_pmd(pte_t pte)
1043{
66c570f5 1044 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 1045}
1046
1047static inline pte_t *pmdp_ptep(pmd_t *pmd)
1048{
1049 return (pte_t *)pmd;
1050}
3dfcb315
AK		 1051#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1052#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1053#define pmd_young(pmd) pte_young(pmd_pte(pmd))
1054#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1055#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1056#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 1057#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 1058#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1059#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
c137a275
AK		 1060#define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
1061#define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
7207f436
LD		 1062
1063#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1064#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1065#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1066#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1067#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1068
1ca72129
AK		 1069#ifdef CONFIG_NUMA_BALANCING
1070static inline int pmd_protnone(pmd_t pmd)
1071{
1072 return pte_protnone(pmd_pte(pmd));
1073}
1074#endif /* CONFIG_NUMA_BALANCING */
3dfcb315 1075
3dfcb315 1076#define pmd_write(pmd) pte_write(pmd_pte(pmd))
d19469e8 1077#define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
c137a275 1078#define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
3dfcb315 1079
f72a85e3
AK		 1080#define pmd_access_permitted pmd_access_permitted
1081static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1082{
1083 return pte_access_permitted(pmd_pte(pmd), write);
1084}
1085
6a1ea362
AK		 1086#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1087extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1088extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1089extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1090extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1091 pmd_t *pmdp, pmd_t pmd);
1092extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1093 pmd_t *pmd);
3df33f12
AK		 1094extern int hash__has_transparent_hugepage(void);
1095static inline int has_transparent_hugepage(void)
1096{
bde3eb62
AK		 1097 if (radix_enabled())
1098 return radix__has_transparent_hugepage();
3df33f12
AK		 1099 return hash__has_transparent_hugepage();
1100}
c04a5880 1101#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 1102
3df33f12
AK		 1103static inline unsigned long
1104pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1105 unsigned long clr, unsigned long set)
3dfcb315 1106{
bde3eb62
AK		 1107 if (radix_enabled())
1108 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 1109 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1110}
1111
1112static inline int pmd_large(pmd_t pmd)
1113{
66c570f5 1114 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 1115}
1116
1117static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1118{
1119 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1120}
1121/*
1122 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1123 * the below will work for radix too
1124 */
1125static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1126 unsigned long addr, pmd_t *pmdp)
1127{
1128 unsigned long old;
1129
66c570f5 1130 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 1131 return 0;
1132 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1133 return ((old & _PAGE_ACCESSED) != 0);
1134}
1135
1136#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1137static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1138 pmd_t *pmdp)
1139{
d19469e8 1140 if (__pmd_write((*pmdp)))
52c50ca7
AK		 1141 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1142 else if (unlikely(pmd_savedwrite(*pmdp)))
1143 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
3dfcb315
AK		 1144}
1145
ab624762
AK		 1146static inline int pmd_trans_huge(pmd_t pmd)
1147{
1148 if (radix_enabled())
1149 return radix__pmd_trans_huge(pmd);
1150 return hash__pmd_trans_huge(pmd);
1151}
1152
1153#define __HAVE_ARCH_PMD_SAME
1154static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1155{
1156 if (radix_enabled())
1157 return radix__pmd_same(pmd_a, pmd_b);
1158 return hash__pmd_same(pmd_a, pmd_b);
1159}
1160
3dfcb315
AK		 1161static inline pmd_t pmd_mkhuge(pmd_t pmd)
1162{
ab624762
AK		 1163 if (radix_enabled())
1164 return radix__pmd_mkhuge(pmd);
1165 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 1166}
1167
3dfcb315
AK		 1168#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1169extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1170 unsigned long address, pmd_t *pmdp,
1171 pmd_t entry, int dirty);
1172
3dfcb315
AK		 1173#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1174extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1175 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 1176
1177#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 1178static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1179 unsigned long addr, pmd_t *pmdp)
1180{
bde3eb62
AK		 1181 if (radix_enabled())
1182 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 1183 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1184}
3dfcb315 1185
3df33f12
AK		 1186static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1187 unsigned long address, pmd_t *pmdp)
1188{
bde3eb62
AK		 1189 if (radix_enabled())
1190 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 1191 return hash__pmdp_collapse_flush(vma, address, pmdp);
1192}
3dfcb315
AK		 1193#define pmdp_collapse_flush pmdp_collapse_flush
1194
1195#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 1196static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1197 pmd_t *pmdp, pgtable_t pgtable)
1198{
bde3eb62
AK		 1199 if (radix_enabled())
1200 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 1201 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1202}
1203
3dfcb315 1204#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 1205static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1206 pmd_t *pmdp)
1207{
bde3eb62
AK		 1208 if (radix_enabled())
1209 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 1210 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1211}
3dfcb315
AK		 1212
1213#define __HAVE_ARCH_PMDP_INVALIDATE
8cc931e0
AK		 1214extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1215 pmd_t *pmdp);
3dfcb315
AK		 1216
1217#define pmd_move_must_withdraw pmd_move_must_withdraw
1218struct spinlock;
1219static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1dd38b6c
AK		 1220 struct spinlock *old_pmd_ptl,
1221 struct vm_area_struct *vma)
3dfcb315 1222{
bde3eb62
AK		 1223 if (radix_enabled())
1224 return false;
3dfcb315
AK		 1225 /*
1226 * Archs like ppc64 use pgtable to store per pmd
1227 * specific information. So when we switch the pmd,
1228 * we should also withdraw and deposit the pgtable
1229 */
1230 return true;
1231}
953c66c2
AK		 1232
1233
1234#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1235static inline bool arch_needs_pgtable_deposit(void)
1236{
1237 if (radix_enabled())
1238 return false;
1239 return true;
1240}
fa4531f7 1241extern void serialize_against_pte_lookup(struct mm_struct *mm);
953c66c2 1242
ebd31197
OH		 1243
1244static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1245{
1246 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1247}
1248
1249static inline int pmd_devmap(pmd_t pmd)
1250{
1251 return pte_devmap(pmd_pte(pmd));
1252}
1253
1254static inline int pud_devmap(pud_t pud)
1255{
1256 return 0;
1257}
1258
1259static inline int pgd_devmap(pgd_t pgd)
1260{
1261 return 0;
1262}
6a1ea362 1263#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
ebd31197
OH		 1264
1265static inline const int pud_pfn(pud_t pud)
1266{
1267 /*
1268 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1269 * check so this should never be used. If it grows another user we
1270 * want to know about it.
1271 */
1272 BUILD_BUG();
1273 return 0;
1274}
029d9252 1275
3dfcb315
AK		 1276#endif /* __ASSEMBLY__ */
1277#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)