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powerpc/nohash: fix pte_access_permitted()
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
3dfcb315
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
3#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519 4
9849a569
KS		 5#include <asm-generic/5level-fixup.h>
6
c137a275
AK		 7#ifndef __ASSEMBLY__
8#include <linux/mmdebug.h>
ebd31197 9#include <linux/bug.h>
c137a275 10#endif
9849a569 11
2e873519
AK		 12/*
13 * Common bits between hash and Radix page table
14 */
15#define _PAGE_BIT_SWAP_TYPE 0
16
35175033 17#define _PAGE_NA 0
6b8cb66a 18#define _PAGE_RO 0
812fadcb 19#define _PAGE_USER 0
6b8cb66a 20
2e873519
AK		 21#define _PAGE_EXEC 0x00001 /* execute permission */
22#define _PAGE_WRITE 0x00002 /* write access allowed */
23#define _PAGE_READ 0x00004 /* read access allowed */
24#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
25#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
26#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
27#define _PAGE_SAO 0x00010 /* Strong access order */
28#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
29#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
30#define _PAGE_DIRTY 0x00080 /* C: page changed */
31#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 32/*
2e873519 33 * Software bits
3dfcb315 34 */
69dfbaeb
AK		 35#define _RPAGE_SW0 0x2000000000000000UL
36#define _RPAGE_SW1 0x00800
37#define _RPAGE_SW2 0x00400
38#define _RPAGE_SW3 0x00200
049d567a
AK		 39#define _RPAGE_RSV1 0x1000000000000000UL
40#define _RPAGE_RSV2 0x0800000000000000UL
41#define _RPAGE_RSV3 0x0400000000000000UL
42#define _RPAGE_RSV4 0x0200000000000000UL
eb95d016 43#define _RPAGE_RSV5 0x00040UL
6aa59f51
AK		 44
45#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
46#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
47
48/*
49 * Top and bottom bits of RPN which can be used by hash
50 * translation mode, because we expect them to be zero
51 * otherwise.
52 */
32789d38
AK		 53#define _RPAGE_RPN0 0x01000
54#define _RPAGE_RPN1 0x02000
6aa59f51
AK		 55#define _RPAGE_RPN44 0x0100000000000000UL
56#define _RPAGE_RPN43 0x0080000000000000UL
57#define _RPAGE_RPN42 0x0040000000000000UL
58#define _RPAGE_RPN41 0x0020000000000000UL
049d567a 59
2f18d533
AK		 60/* Max physical address bit as per radix table */
61#define _RPAGE_PA_MAX 57
62
63/*
64 * Max physical address bit we will use for now.
65 *
66 * This is mostly a hardware limitation and for now Power9 has
67 * a 51 bit limit.
68 *
69 * This is different from the number of physical bit required to address
70 * the last byte of memory. That is defined by MAX_PHYSMEM_BITS.
71 * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum
72 * number of sections we can support (SECTIONS_SHIFT).
73 *
74 * This is different from Radix page table limitation above and
75 * should always be less than that. The limit is done such that
76 * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX
77 * for hash linux page table specific bits.
78 *
79 * In order to be compatible with future hardware generations we keep
80 * some offsets and limit this for now to 53
81 */
82#define _PAGE_PA_MAX 53
83
69dfbaeb 84#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
69dfbaeb 85#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
ebd31197
OH		 86#define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */
87#define __HAVE_ARCH_PTE_DEVMAP
88
2e873519
AK		 89/*
90 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
91 * Instead of fixing all of them, add an alternate define which
92 * maps CI pte mapping.
93 */
94#define _PAGE_NO_CACHE _PAGE_TOLERANT
95/*
2f18d533
AK		 96 * We support _RPAGE_PA_MAX bit real address in pte. On the linux side
97 * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX
98 * and every thing below PAGE_SHIFT;
2e873519 99 */
2f18d533 100#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK))
2e873519
AK		 101/*
102 * set of bits not changed in pmd_modify. Even though we have hash specific bits
103 * in here, on radix we expect them to be zero.
104 */
105#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
106 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
107 _PAGE_SOFT_DIRTY)
108/*
109 * user access blocked by key
110 */
111#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
112#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
113#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
114 _PAGE_RW | _PAGE_EXEC)
115/*
116 * No page size encoding in the linux PTE
117 */
118#define _PAGE_PSIZE 0
119/*
120 * _PAGE_CHG_MASK masks of bits that are to be preserved across
121 * pgprot changes
122 */
123#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
124 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
125 _PAGE_SOFT_DIRTY)
eb95d016
RP		 126
127#define H_PTE_PKEY (H_PTE_PKEY_BIT0 | H_PTE_PKEY_BIT1 | H_PTE_PKEY_BIT2 | \
128 H_PTE_PKEY_BIT3 | H_PTE_PKEY_BIT4)
2e873519
AK		 129/*
130 * Mask of bits returned by pte_pgprot()
131 */
132#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
133 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
134 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
eb95d016 135 _PAGE_SOFT_DIRTY | H_PTE_PKEY)
3dfcb315 136/*
2e873519
AK		 137 * We define 2 sets of base prot bits, one for basic pages (ie,
138 * cacheable kernel and user pages) and one for non cacheable
139 * pages. We always set _PAGE_COHERENT when SMP is enabled or
140 * the processor might need it for DMA coherency.
3dfcb315 141 */
2e873519
AK		 142#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
143#define _PAGE_BASE (_PAGE_BASE_NC)
144
145/* Permission masks used to generate the __P and __S table,
146 *
147 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
148 *
149 * Write permissions imply read permissions for now (we could make write-only
150 * pages on BookE but we don't bother for now). Execute permission control is
151 * possible on platforms that define _PAGE_EXEC
152 *
153 * Note due to the way vm flags are laid out, the bits are XWR
154 */
155#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
156#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
157#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
158#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
159#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
160#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
161#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
162
163#define __P000 PAGE_NONE
164#define __P001 PAGE_READONLY
165#define __P010 PAGE_COPY
166#define __P011 PAGE_COPY
167#define __P100 PAGE_READONLY_X
168#define __P101 PAGE_READONLY_X
169#define __P110 PAGE_COPY_X
170#define __P111 PAGE_COPY_X
171
172#define __S000 PAGE_NONE
173#define __S001 PAGE_READONLY
174#define __S010 PAGE_SHARED
175#define __S011 PAGE_SHARED
176#define __S100 PAGE_READONLY_X
177#define __S101 PAGE_READONLY_X
178#define __S110 PAGE_SHARED_X
179#define __S111 PAGE_SHARED_X
180
181/* Permission masks used for kernel mappings */
182#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
183#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
184 _PAGE_TOLERANT)
185#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
186 _PAGE_NON_IDEMPOTENT)
187#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
188#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
189#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
190
191/*
192 * Protection used for kernel text. We want the debuggers to be able to
193 * set breakpoints anywhere, so don't write protect the kernel text
194 * on platforms where such control is possible.
195 */
196#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
197 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
198#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
199#else
200#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
201#endif
202
203/* Make modules code happy. We don't set RO yet */
204#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
205#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 206
dd1842a2
AK		 207#ifndef __ASSEMBLY__
208/*
209 * page table defines
210 */
211extern unsigned long __pte_index_size;
212extern unsigned long __pmd_index_size;
213extern unsigned long __pud_index_size;
214extern unsigned long __pgd_index_size;
fae22116 215extern unsigned long __pud_cache_index;
dd1842a2
AK		 216#define PTE_INDEX_SIZE __pte_index_size
217#define PMD_INDEX_SIZE __pmd_index_size
218#define PUD_INDEX_SIZE __pud_index_size
219#define PGD_INDEX_SIZE __pgd_index_size
738f9645
AK		 220/* pmd table use page table fragments */
221#define PMD_CACHE_INDEX 0
fae22116 222#define PUD_CACHE_INDEX __pud_cache_index
dd1842a2
AK		 223/*
224 * Because of use of pte fragments and THP, size of page table
225 * are not always derived out of index size above.
226 */
227extern unsigned long __pte_table_size;
228extern unsigned long __pmd_table_size;
229extern unsigned long __pud_table_size;
230extern unsigned long __pgd_table_size;
231#define PTE_TABLE_SIZE __pte_table_size
232#define PMD_TABLE_SIZE __pmd_table_size
233#define PUD_TABLE_SIZE __pud_table_size
234#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 235
236extern unsigned long __pmd_val_bits;
237extern unsigned long __pud_val_bits;
238extern unsigned long __pgd_val_bits;
239#define PMD_VAL_BITS __pmd_val_bits
240#define PUD_VAL_BITS __pud_val_bits
241#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 242
243extern unsigned long __pte_frag_nr;
244#define PTE_FRAG_NR __pte_frag_nr
245extern unsigned long __pte_frag_size_shift;
246#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
247#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2 248
8a6c697b
AK		 249extern unsigned long __pmd_frag_nr;
250#define PMD_FRAG_NR __pmd_frag_nr
251extern unsigned long __pmd_frag_size_shift;
252#define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift
253#define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT)
254
dd1842a2
AK		 255#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
256#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
257#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
258#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
259
260/* PMD_SHIFT determines what a second-level page table entry can map */
261#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
262#define PMD_SIZE (1UL << PMD_SHIFT)
263#define PMD_MASK (~(PMD_SIZE-1))
264
265/* PUD_SHIFT determines what a third-level page table entry can map */
266#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
267#define PUD_SIZE (1UL << PUD_SHIFT)
268#define PUD_MASK (~(PUD_SIZE-1))
269
270/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
271#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
272#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
273#define PGDIR_MASK (~(PGDIR_SIZE-1))
274
275/* Bits to mask out from a PMD to get to the PTE page */
276#define PMD_MASKED_BITS 0xc0000000000000ffUL
277/* Bits to mask out from a PUD to get to the PMD page */
278#define PUD_MASKED_BITS 0xc0000000000000ffUL
279/* Bits to mask out from a PGD to get to the PUD page */
280#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e 281
0c4d2680
AK		 282/*
283 * Used as an indicator for rcu callback functions
284 */
285enum pgtable_index {
286 PTE_INDEX = 0,
287 PMD_INDEX,
288 PUD_INDEX,
289 PGD_INDEX,
fadd03c6
AK		 290 /*
291 * Below are used with 4k page size and hugetlb
292 */
293 HTLB_16M_INDEX,
294 HTLB_16G_INDEX,
0c4d2680
AK		 295};
296
d6a9996e
AK		 297extern unsigned long __vmalloc_start;
298extern unsigned long __vmalloc_end;
299#define VMALLOC_START __vmalloc_start
300#define VMALLOC_END __vmalloc_end
301
302extern unsigned long __kernel_virt_start;
303extern unsigned long __kernel_virt_size;
63ee9b2f 304extern unsigned long __kernel_io_start;
d6a9996e
AK		 305#define KERN_VIRT_START __kernel_virt_start
306#define KERN_VIRT_SIZE __kernel_virt_size
63ee9b2f 307#define KERN_IO_START __kernel_io_start
d6a9996e
AK		 308extern struct page *vmemmap;
309extern unsigned long ioremap_bot;
bfa37087 310extern unsigned long pci_io_base;
dd1842a2 311#endif /* __ASSEMBLY__ */
3dfcb315 312
ab537dca 313#include <asm/book3s/64/hash.h>
b0b5e9b1 314#include <asm/book3s/64/radix.h>
3dfcb315 315
a9252aae
AK		 316#ifdef CONFIG_PPC_64K_PAGES
317#include <asm/book3s/64/pgtable-64k.h>
318#else
319#include <asm/book3s/64/pgtable-4k.h>
320#endif
321
3dfcb315 322#include <asm/barrier.h>
3dfcb315
AK		 323/*
324 * The second half of the kernel virtual space is used for IO mappings,
325 * it's itself carved into the PIO region (ISA and PHB IO space) and
326 * the ioremap space
327 *
328 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
329 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
330 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
331 */
3dfcb315
AK		 332#define FULL_IO_SIZE 0x80000000ul
333#define ISA_IO_BASE (KERN_IO_START)
334#define ISA_IO_END (KERN_IO_START + 0x10000ul)
335#define PHB_IO_BASE (ISA_IO_END)
336#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
337#define IOREMAP_BASE (PHB_IO_END)
338#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
339
b0412ea9 340/* Advertise special mapping type for AGP */
b0412ea9
AK		 341#define HAVE_PAGE_AGP
342
3dfcb315
AK		 343#ifndef __ASSEMBLY__
344
345/*
346 * This is the default implementation of various PTE accessors, it's
347 * used in all cases except Book3S with 64K pages where we have a
348 * concept of sub-pages
349 */
350#ifndef __real_pte
351
ff31e105 352#define __real_pte(e, p, o) ((real_pte_t){(e)})
3dfcb315 353#define __rpte_to_pte(r) ((r).pte)
945537df 354#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 355
356#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
357 do { \
358 index = 0; \
359 shift = mmu_psize_defs[psize].shift; \
360
361#define pte_iterate_hashed_end() } while(0)
362
363/*
364 * We expect this to be called only for user addresses or kernel virtual
365 * addresses other than the linear mapping.
366 */
367#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
368
369#endif /* __real_pte */
370
ac94ac79
AK		 371static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
372 pte_t *ptep, unsigned long clr,
373 unsigned long set, int huge)
374{
375 if (radix_enabled())
376 return radix__pte_update(mm, addr, ptep, clr, set, huge);
377 return hash__pte_update(mm, addr, ptep, clr, set, huge);
378}
13f829a5
AK		 379/*
380 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
381 * We currently remove entries from the hashtable regardless of whether
382 * the entry was young or dirty.
383 *
384 * We should be more intelligent about this but for the moment we override
385 * these functions and force a tlb flush unconditionally
386 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
387 * function for both hash and radix.
388 */
389static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
390 unsigned long addr, pte_t *ptep)
391{
392 unsigned long old;
393
66c570f5 394 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 395 return 0;
396 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
397 return (old & _PAGE_ACCESSED) != 0;
398}
399
400#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
401#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
402({ \
403 int __r; \
404 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
405 __r; \
406})
407
d19469e8 408static inline int __pte_write(pte_t pte)
52c50ca7
AK		 409{
410 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
411}
412
413#ifdef CONFIG_NUMA_BALANCING
414#define pte_savedwrite pte_savedwrite
415static inline bool pte_savedwrite(pte_t pte)
416{
417 /*
418 * Saved write ptes are prot none ptes that doesn't have
419 * privileged bit sit. We mark prot none as one which has
420 * present and pviliged bit set and RWX cleared. To mark
421 * protnone which used to have _PAGE_WRITE set we clear
422 * the privileged bit.
423 */
424 return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED));
425}
426#else
427#define pte_savedwrite pte_savedwrite
428static inline bool pte_savedwrite(pte_t pte)
429{
430 return false;
431}
432#endif
433
d19469e8
AK		 434static inline int pte_write(pte_t pte)
435{
436 return __pte_write(pte) || pte_savedwrite(pte);
437}
438
ca8afd40
CL		 439static inline int pte_read(pte_t pte)
440{
441 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ));
442}
443
13f829a5
AK		 444#define __HAVE_ARCH_PTEP_SET_WRPROTECT
445static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
446 pte_t *ptep)
447{
d19469e8 448 if (__pte_write(*ptep))
52c50ca7
AK		 449 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
450 else if (unlikely(pte_savedwrite(*ptep)))
451 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0);
13f829a5
AK		 452}
453
454static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
455 unsigned long addr, pte_t *ptep)
456{
52c50ca7
AK		 457 /*
458 * We should not find protnone for hugetlb, but this complete the
459 * interface.
460 */
d19469e8 461 if (__pte_write(*ptep))
52c50ca7
AK		 462 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
463 else if (unlikely(pte_savedwrite(*ptep)))
464 pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1);
13f829a5
AK		 465}
466
467#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
468static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
469 unsigned long addr, pte_t *ptep)
470{
471 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
472 return __pte(old);
473}
474
f4894b80
AK		 475#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
476static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
477 unsigned long addr,
478 pte_t *ptep, int full)
479{
480 if (full && radix_enabled()) {
481 /*
2bf1071a
NP		 482 * We know that this is a full mm pte clear and
483 * hence can be sure there is no parallel set_pte.
f4894b80
AK		 484 */
485 return radix__ptep_get_and_clear_full(mm, addr, ptep, full);
486 }
487 return ptep_get_and_clear(mm, addr, ptep);
488}
489
490
13f829a5
AK		 491static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
492 pte_t * ptep)
493{
494 pte_update(mm, addr, ptep, ~0UL, 0, 0);
495}
66c570f5 496
66c570f5
AK		 497static inline int pte_dirty(pte_t pte)
498{
499 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
500}
501
502static inline int pte_young(pte_t pte)
503{
504 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
505}
506
507static inline int pte_special(pte_t pte)
508{
509 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
510}
511
13f829a5
AK		 512static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
513
514#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
515static inline bool pte_soft_dirty(pte_t pte)
516{
66c570f5 517 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 518}
66c570f5 519
13f829a5
AK		 520static inline pte_t pte_mksoft_dirty(pte_t pte)
521{
522 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
523}
524
525static inline pte_t pte_clear_soft_dirty(pte_t pte)
526{
527 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
528}
529#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
530
531#ifdef CONFIG_NUMA_BALANCING
13f829a5
AK		 532static inline int pte_protnone(pte_t pte)
533{
c137a275
AK		 534 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) ==
535 cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE);
536}
537
538#define pte_mk_savedwrite pte_mk_savedwrite
539static inline pte_t pte_mk_savedwrite(pte_t pte)
540{
541 /*
542 * Used by Autonuma subsystem to preserve the write bit
543 * while marking the pte PROT_NONE. Only allow this
544 * on PROT_NONE pte
545 */
546 VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
547 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
548 return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
549}
550
551#define pte_clear_savedwrite pte_clear_savedwrite
552static inline pte_t pte_clear_savedwrite(pte_t pte)
553{
554 /*
555 * Used by KSM subsystem to make a protnone pte readonly.
556 */
557 VM_BUG_ON(!pte_protnone(pte));
558 return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
559}
d19469e8
AK		 560#else
561#define pte_clear_savedwrite pte_clear_savedwrite
562static inline pte_t pte_clear_savedwrite(pte_t pte)
563{
564 VM_WARN_ON(1);
565 return __pte(pte_val(pte) & ~_PAGE_WRITE);
566}
13f829a5
AK		 567#endif /* CONFIG_NUMA_BALANCING */
568
569static inline int pte_present(pte_t pte)
570{
66c570f5 571 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
13f829a5 572}
f72a85e3 573
bca7aacf 574#ifdef CONFIG_PPC_MEM_KEYS
f2407ef3 575extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);
bca7aacf
RP		 576#else
577static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
578{
579 return true;
580}
581#endif /* CONFIG_PPC_MEM_KEYS */
f2407ef3 582
f72a85e3
AK		 583#define pte_access_permitted pte_access_permitted
584static inline bool pte_access_permitted(pte_t pte, bool write)
585{
586 unsigned long pteval = pte_val(pte);
587 /* Also check for pte_user */
588 unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
589 /*
590 * _PAGE_READ is needed for any access and will be
591 * cleared for PROT_NONE
592 */
593 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
594
595 if (write)
596 need_pte_bits |= _PAGE_WRITE;
597
598 if ((pteval & need_pte_bits) != need_pte_bits)
599 return false;
600
601 if ((pteval & clear_pte_bits) == clear_pte_bits)
602 return false;
bca7aacf
RP		 603
604 return arch_pte_access_permitted(pte_val(pte), write, 0);
f72a85e3
AK		 605}
606
13f829a5
AK		 607/*
608 * Conversion functions: convert a page and protection to a page entry,
609 * and a page entry and page directory to the page they refer to.
610 *
611 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
612 * long for now.
613 */
614static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
615{
616 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
617 pgprot_val(pgprot));
618}
619
620static inline unsigned long pte_pfn(pte_t pte)
621{
622 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
623}
624
625/* Generic modifiers for PTE bits */
626static inline pte_t pte_wrprotect(pte_t pte)
627{
d19469e8
AK		 628 if (unlikely(pte_savedwrite(pte)))
629 return pte_clear_savedwrite(pte);
13f829a5
AK		 630 return __pte(pte_val(pte) & ~_PAGE_WRITE);
631}
632
633static inline pte_t pte_mkclean(pte_t pte)
634{
635 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
636}
637
638static inline pte_t pte_mkold(pte_t pte)
639{
640 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
641}
642
643static inline pte_t pte_mkwrite(pte_t pte)
644{
645 /*
646 * write implies read, hence set both
647 */
648 return __pte(pte_val(pte) | _PAGE_RW);
649}
650
651static inline pte_t pte_mkdirty(pte_t pte)
652{
653 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
654}
655
656static inline pte_t pte_mkyoung(pte_t pte)
657{
658 return __pte(pte_val(pte) | _PAGE_ACCESSED);
659}
660
661static inline pte_t pte_mkspecial(pte_t pte)
662{
663 return __pte(pte_val(pte) | _PAGE_SPECIAL);
664}
665
666static inline pte_t pte_mkhuge(pte_t pte)
667{
668 return pte;
669}
670
ebd31197
OH		 671static inline pte_t pte_mkdevmap(pte_t pte)
672{
673 return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
674}
675
c9c98bc5
OH		 676/*
677 * This is potentially called with a pmd as the argument, in which case it's not
678 * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set.
679 * That's because the bit we use for _PAGE_DEVMAP is not reserved for software
680 * use in page directory entries (ie. non-ptes).
681 */
ebd31197
OH		 682static inline int pte_devmap(pte_t pte)
683{
c9c98bc5
OH		 684 u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE);
685
686 return (pte_raw(pte) & mask) == mask;
ebd31197
OH		 687}
688
13f829a5
AK		 689static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
690{
691 /* FIXME!! check whether this need to be a conditional */
692 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
693}
694
34fbadd8
AK		 695static inline bool pte_user(pte_t pte)
696{
66c570f5 697 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
34fbadd8
AK		 698}
699
700/* Encode and de-code a swap entry */
701#define MAX_SWAPFILES_CHECK() do { \
702 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
703 /* \
704 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
705 * We filter HPTEFLAGS on set_pte. \
706 */ \
707 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
708 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
709 } while (0)
710/*
711 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
712 */
713#define SWP_TYPE_BITS 5
714#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
715 & ((1UL << SWP_TYPE_BITS) - 1))
716#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
717#define __swp_entry(type, offset) ((swp_entry_t) { \
718 ((type) << _PAGE_BIT_SWAP_TYPE) \
719 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
720/*
721 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
722 * swap type and offset we get from swap and convert that to pte to find a
723 * matching pte in linux page table.
724 * Clear bits not found in swap entries here.
725 */
726#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
727#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
728
729#ifdef CONFIG_MEM_SOFT_DIRTY
730#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
731#else
732#define _PAGE_SWP_SOFT_DIRTY 0UL
733#endif /* CONFIG_MEM_SOFT_DIRTY */
734
735#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
736static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
737{
738 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
739}
66c570f5 740
34fbadd8
AK		 741static inline bool pte_swp_soft_dirty(pte_t pte)
742{
66c570f5 743 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 744}
66c570f5 745
34fbadd8
AK		 746static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
747{
748 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
749}
750#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
751
752static inline bool check_pte_access(unsigned long access, unsigned long ptev)
753{
754 /*
755 * This check for _PAGE_RWX and _PAGE_PRESENT bits
756 */
757 if (access & ~ptev)
758 return false;
759 /*
760 * This check for access to privilege space
761 */
762 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
763 return false;
764
765 return true;
766}
ac94ac79
AK		 767/*
768 * Generic functions with hash/radix callbacks
769 */
770
e4c1112c 771static inline void __ptep_set_access_flags(struct vm_area_struct *vma,
b3603e17 772 pte_t *ptep, pte_t entry,
e4c1112c
AK		 773 unsigned long address,
774 int psize)
ac94ac79
AK		 775{
776 if (radix_enabled())
e4c1112c
AK		 777 return radix__ptep_set_access_flags(vma, ptep, entry,
778 address, psize);
ac94ac79
AK		 779 return hash__ptep_set_access_flags(ptep, entry);
780}
781
782#define __HAVE_ARCH_PTE_SAME
783static inline int pte_same(pte_t pte_a, pte_t pte_b)
784{
785 if (radix_enabled())
786 return radix__pte_same(pte_a, pte_b);
787 return hash__pte_same(pte_a, pte_b);
788}
789
790static inline int pte_none(pte_t pte)
791{
792 if (radix_enabled())
793 return radix__pte_none(pte);
794 return hash__pte_none(pte);
795}
796
797static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
798 pte_t *ptep, pte_t pte, int percpu)
799{
800 if (radix_enabled())
801 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
802 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
803}
34fbadd8 804
13f829a5
AK		 805#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
806
807#define pgprot_noncached pgprot_noncached
808static inline pgprot_t pgprot_noncached(pgprot_t prot)
809{
810 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
811 _PAGE_NON_IDEMPOTENT);
812}
813
814#define pgprot_noncached_wc pgprot_noncached_wc
815static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
816{
817 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
818 _PAGE_TOLERANT);
819}
820
821#define pgprot_cached pgprot_cached
822static inline pgprot_t pgprot_cached(pgprot_t prot)
823{
824 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
825}
826
827#define pgprot_writecombine pgprot_writecombine
828static inline pgprot_t pgprot_writecombine(pgprot_t prot)
829{
830 return pgprot_noncached_wc(prot);
831}
832/*
833 * check a pte mapping have cache inhibited property
834 */
835static inline bool pte_ci(pte_t pte)
836{
837 unsigned long pte_v = pte_val(pte);
838
839 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
840 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
841 return true;
842 return false;
843}
844
f281b5d5
AK		 845static inline void pmd_set(pmd_t *pmdp, unsigned long val)
846{
847 *pmdp = __pmd(val);
848}
849
850static inline void pmd_clear(pmd_t *pmdp)
851{
852 *pmdp = __pmd(0);
853}
854
66c570f5
AK		 855static inline int pmd_none(pmd_t pmd)
856{
857 return !pmd_raw(pmd);
858}
859
860static inline int pmd_present(pmd_t pmd)
861{
862
863 return !pmd_none(pmd);
864}
3dfcb315 865
ac94ac79
AK		 866static inline int pmd_bad(pmd_t pmd)
867{
868 if (radix_enabled())
869 return radix__pmd_bad(pmd);
870 return hash__pmd_bad(pmd);
871}
872
f281b5d5
AK		 873static inline void pud_set(pud_t *pudp, unsigned long val)
874{
875 *pudp = __pud(val);
876}
877
878static inline void pud_clear(pud_t *pudp)
879{
880 *pudp = __pud(0);
881}
882
66c570f5
AK		 883static inline int pud_none(pud_t pud)
884{
885 return !pud_raw(pud);
886}
887
888static inline int pud_present(pud_t pud)
889{
890 return !pud_none(pud);
891}
3dfcb315
AK		 892
893extern struct page *pud_page(pud_t pud);
371352ca 894extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 895static inline pte_t pud_pte(pud_t pud)
896{
66c570f5 897 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 898}
899
900static inline pud_t pte_pud(pte_t pte)
901{
66c570f5 902 return __pud_raw(pte_raw(pte));
3dfcb315
AK		 903}
904#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 905
906static inline int pud_bad(pud_t pud)
907{
908 if (radix_enabled())
909 return radix__pud_bad(pud);
910 return hash__pud_bad(pud);
911}
912
f72a85e3
AK		 913#define pud_access_permitted pud_access_permitted
914static inline bool pud_access_permitted(pud_t pud, bool write)
915{
916 return pte_access_permitted(pud_pte(pud), write);
917}
ac94ac79 918
3dfcb315 919#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 920static inline void pgd_set(pgd_t *pgdp, unsigned long val)
921{
922 *pgdp = __pgd(val);
923}
3dfcb315 924
368ced78
AK		 925static inline void pgd_clear(pgd_t *pgdp)
926{
927 *pgdp = __pgd(0);
928}
929
66c570f5
AK		 930static inline int pgd_none(pgd_t pgd)
931{
932 return !pgd_raw(pgd);
933}
934
935static inline int pgd_present(pgd_t pgd)
936{
937 return !pgd_none(pgd);
938}
368ced78
AK		 939
940static inline pte_t pgd_pte(pgd_t pgd)
941{
66c570f5 942 return __pte_raw(pgd_raw(pgd));
368ced78
AK		 943}
944
945static inline pgd_t pte_pgd(pte_t pte)
946{
66c570f5 947 return __pgd_raw(pte_raw(pte));
368ced78
AK		 948}
949
ac94ac79
AK		 950static inline int pgd_bad(pgd_t pgd)
951{
952 if (radix_enabled())
953 return radix__pgd_bad(pgd);
954 return hash__pgd_bad(pgd);
955}
956
f72a85e3
AK		 957#define pgd_access_permitted pgd_access_permitted
958static inline bool pgd_access_permitted(pgd_t pgd, bool write)
959{
960 return pte_access_permitted(pgd_pte(pgd), write);
961}
962
368ced78
AK		 963extern struct page *pgd_page(pgd_t pgd);
964
aba480e1
AK		 965/* Pointers in the page table tree are physical addresses */
966#define __pgtable_ptr_val(ptr) __pa(ptr)
967
968#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
969#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
970#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
971
972#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
973#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
974#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
975#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
976
3dfcb315
AK		 977/*
978 * Find an entry in a page-table-directory. We combine the address region
979 * (the high order N bits) and the pgd portion of the address.
980 */
3dfcb315
AK		 981
982#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
983
368ced78
AK		 984#define pud_offset(pgdp, addr) \
985 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 986#define pmd_offset(pudp,addr) \
371352ca 987 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 988#define pte_offset_kernel(dir,addr) \
371352ca 989 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 990
991#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
992#define pte_unmap(pte) do { } while(0)
993
994/* to find an entry in a kernel page-table-directory */
995/* This now only contains the vmalloc pages */
996#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 997
998#define pte_ERROR(e) \
999 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
1000#define pmd_ERROR(e) \
1001 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 1002#define pud_ERROR(e) \
1003 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 1004#define pgd_ERROR(e) \
1005 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
1006
31a14fae
AK		 1007static inline int map_kernel_page(unsigned long ea, unsigned long pa,
1008 unsigned long flags)
7207f436 1009{
d9225ad9
AK		 1010 if (radix_enabled()) {
1011#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
1012 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
1013 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
1014#endif
1015 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
1016 }
31a14fae 1017 return hash__map_kernel_page(ea, pa, flags);
7207f436 1018}
31a14fae
AK		 1019
1020static inline int __meminit vmemmap_create_mapping(unsigned long start,
1021 unsigned long page_size,
1022 unsigned long phys)
7207f436 1023{
d9225ad9
AK		 1024 if (radix_enabled())
1025 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 1026 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 1027}
31a14fae
AK		 1028
1029#ifdef CONFIG_MEMORY_HOTPLUG
1030static inline void vmemmap_remove_mapping(unsigned long start,
1031 unsigned long page_size)
7207f436 1032{
d9225ad9
AK		 1033 if (radix_enabled())
1034 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 1035 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 1036}
31a14fae 1037#endif
3dfcb315
AK		 1038struct page *realmode_pfn_to_page(unsigned long pfn);
1039
3dfcb315
AK		 1040static inline pte_t pmd_pte(pmd_t pmd)
1041{
66c570f5 1042 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 1043}
1044
1045static inline pmd_t pte_pmd(pte_t pte)
1046{
66c570f5 1047 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 1048}
1049
1050static inline pte_t *pmdp_ptep(pmd_t *pmd)
1051{
1052 return (pte_t *)pmd;
1053}
3dfcb315
AK		 1054#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
1055#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
1056#define pmd_young(pmd) pte_young(pmd_pte(pmd))
1057#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
1058#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
1059#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 1060#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 1061#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
1062#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
c137a275
AK		 1063#define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd)))
1064#define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd)))
7207f436
LD		 1065
1066#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
1067#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
1068#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
1069#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
1070#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
1071
1ca72129
AK		 1072#ifdef CONFIG_NUMA_BALANCING
1073static inline int pmd_protnone(pmd_t pmd)
1074{
1075 return pte_protnone(pmd_pte(pmd));
1076}
1077#endif /* CONFIG_NUMA_BALANCING */
3dfcb315 1078
3dfcb315 1079#define pmd_write(pmd) pte_write(pmd_pte(pmd))
d19469e8 1080#define __pmd_write(pmd) __pte_write(pmd_pte(pmd))
c137a275 1081#define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd))
3dfcb315 1082
f72a85e3
AK		 1083#define pmd_access_permitted pmd_access_permitted
1084static inline bool pmd_access_permitted(pmd_t pmd, bool write)
1085{
1086 return pte_access_permitted(pmd_pte(pmd), write);
1087}
1088
6a1ea362
AK		 1089#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1090extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
1091extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
1092extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
1093extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1094 pmd_t *pmdp, pmd_t pmd);
1095extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
1096 pmd_t *pmd);
3df33f12
AK		 1097extern int hash__has_transparent_hugepage(void);
1098static inline int has_transparent_hugepage(void)
1099{
bde3eb62
AK		 1100 if (radix_enabled())
1101 return radix__has_transparent_hugepage();
3df33f12
AK		 1102 return hash__has_transparent_hugepage();
1103}
c04a5880 1104#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 1105
3df33f12
AK		 1106static inline unsigned long
1107pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
1108 unsigned long clr, unsigned long set)
3dfcb315 1109{
bde3eb62
AK		 1110 if (radix_enabled())
1111 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 1112 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
1113}
1114
1115static inline int pmd_large(pmd_t pmd)
1116{
66c570f5 1117 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 1118}
1119
1120static inline pmd_t pmd_mknotpresent(pmd_t pmd)
1121{
1122 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
1123}
1124/*
1125 * For radix we should always find H_PAGE_HASHPTE zero. Hence
1126 * the below will work for radix too
1127 */
1128static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
1129 unsigned long addr, pmd_t *pmdp)
1130{
1131 unsigned long old;
1132
66c570f5 1133 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 1134 return 0;
1135 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
1136 return ((old & _PAGE_ACCESSED) != 0);
1137}
1138
1139#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1140static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
1141 pmd_t *pmdp)
1142{
d19469e8 1143 if (__pmd_write((*pmdp)))
52c50ca7
AK		 1144 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
1145 else if (unlikely(pmd_savedwrite(*pmdp)))
1146 pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED);
3dfcb315
AK		 1147}
1148
ab624762
AK		 1149static inline int pmd_trans_huge(pmd_t pmd)
1150{
1151 if (radix_enabled())
1152 return radix__pmd_trans_huge(pmd);
1153 return hash__pmd_trans_huge(pmd);
1154}
1155
1156#define __HAVE_ARCH_PMD_SAME
1157static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
1158{
1159 if (radix_enabled())
1160 return radix__pmd_same(pmd_a, pmd_b);
1161 return hash__pmd_same(pmd_a, pmd_b);
1162}
1163
3dfcb315
AK		 1164static inline pmd_t pmd_mkhuge(pmd_t pmd)
1165{
ab624762
AK		 1166 if (radix_enabled())
1167 return radix__pmd_mkhuge(pmd);
1168 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 1169}
1170
3dfcb315
AK		 1171#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1172extern int pmdp_set_access_flags(struct vm_area_struct *vma,
1173 unsigned long address, pmd_t *pmdp,
1174 pmd_t entry, int dirty);
1175
3dfcb315
AK		 1176#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1177extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1178 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 1179
1180#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 1181static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1182 unsigned long addr, pmd_t *pmdp)
1183{
bde3eb62
AK		 1184 if (radix_enabled())
1185 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 1186 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
1187}
3dfcb315 1188
3df33f12
AK		 1189static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1190 unsigned long address, pmd_t *pmdp)
1191{
bde3eb62
AK		 1192 if (radix_enabled())
1193 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 1194 return hash__pmdp_collapse_flush(vma, address, pmdp);
1195}
3dfcb315
AK		 1196#define pmdp_collapse_flush pmdp_collapse_flush
1197
1198#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 1199static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
1200 pmd_t *pmdp, pgtable_t pgtable)
1201{
bde3eb62
AK		 1202 if (radix_enabled())
1203 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 1204 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
1205}
1206
3dfcb315 1207#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 1208static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
1209 pmd_t *pmdp)
1210{
bde3eb62
AK		 1211 if (radix_enabled())
1212 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 1213 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
1214}
3dfcb315
AK		 1215
1216#define __HAVE_ARCH_PMDP_INVALIDATE
8cc931e0
AK		 1217extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
1218 pmd_t *pmdp);
3dfcb315
AK		 1219
1220#define pmd_move_must_withdraw pmd_move_must_withdraw
1221struct spinlock;
1222static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1dd38b6c
AK		 1223 struct spinlock *old_pmd_ptl,
1224 struct vm_area_struct *vma)
3dfcb315 1225{
bde3eb62
AK		 1226 if (radix_enabled())
1227 return false;
3dfcb315
AK		 1228 /*
1229 * Archs like ppc64 use pgtable to store per pmd
1230 * specific information. So when we switch the pmd,
1231 * we should also withdraw and deposit the pgtable
1232 */
1233 return true;
1234}
953c66c2
AK		 1235
1236
1237#define arch_needs_pgtable_deposit arch_needs_pgtable_deposit
1238static inline bool arch_needs_pgtable_deposit(void)
1239{
1240 if (radix_enabled())
1241 return false;
1242 return true;
1243}
fa4531f7 1244extern void serialize_against_pte_lookup(struct mm_struct *mm);
953c66c2 1245
ebd31197
OH		 1246
1247static inline pmd_t pmd_mkdevmap(pmd_t pmd)
1248{
1249 return __pmd(pmd_val(pmd) | (_PAGE_PTE | _PAGE_DEVMAP));
1250}
1251
1252static inline int pmd_devmap(pmd_t pmd)
1253{
1254 return pte_devmap(pmd_pte(pmd));
1255}
1256
1257static inline int pud_devmap(pud_t pud)
1258{
1259 return 0;
1260}
1261
1262static inline int pgd_devmap(pgd_t pgd)
1263{
1264 return 0;
1265}
6a1ea362 1266#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
ebd31197
OH		 1267
1268static inline const int pud_pfn(pud_t pud)
1269{
1270 /*
1271 * Currently all calls to pud_pfn() are gated around a pud_devmap()
1272 * check so this should never be used. If it grows another user we
1273 * want to know about it.
1274 */
1275 BUILD_BUG();
1276 return 0;
1277}
029d9252 1278
3dfcb315
AK		 1279#endif /* __ASSEMBLY__ */
1280#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)