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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3dfcb315 AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 | 4 | |
2fb47060 | 5 | #include <asm-generic/pgtable-nop4d.h> |
9849a569 | 6 | |
c137a275 AK |
7 | #ifndef __ASSEMBLY__ |
8 | #include <linux/mmdebug.h> | |
ebd31197 | 9 | #include <linux/bug.h> |
9ccba66d | 10 | #include <linux/sizes.h> |
c137a275 | 11 | #endif |
9849a569 | 12 | |
2e873519 AK |
13 | /* |
14 | * Common bits between hash and Radix page table | |
15 | */ | |
2e873519 AK |
16 | |
17 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
18 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
19 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
20 | #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) | |
21 | #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) | |
22 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ | |
12564485 | 23 | #define _PAGE_SAO 0x00010 /* Strong access order */ |
2e873519 AK |
24 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ |
25 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
26 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
27 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 28 | /* |
2e873519 | 29 | * Software bits |
3dfcb315 | 30 | */ |
69dfbaeb AK |
31 | #define _RPAGE_SW0 0x2000000000000000UL |
32 | #define _RPAGE_SW1 0x00800 | |
33 | #define _RPAGE_SW2 0x00400 | |
34 | #define _RPAGE_SW3 0x00200 | |
ee8b3933 AK |
35 | #define _RPAGE_RSV1 0x00040UL |
36 | ||
37 | #define _RPAGE_PKEY_BIT4 0x1000000000000000UL | |
38 | #define _RPAGE_PKEY_BIT3 0x0800000000000000UL | |
39 | #define _RPAGE_PKEY_BIT2 0x0400000000000000UL | |
40 | #define _RPAGE_PKEY_BIT1 0x0200000000000000UL | |
41 | #define _RPAGE_PKEY_BIT0 0x0100000000000000UL | |
6aa59f51 AK |
42 | |
43 | #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ | |
44 | #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ | |
bd0dbb73 AK |
45 | /* |
46 | * We need to mark a pmd pte invalid while splitting. We can do that by clearing | |
47 | * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to | |
48 | * differentiate between two use a SW field when invalidating. | |
49 | * | |
50 | * We do that temporary invalidate for regular pte entry in ptep_set_access_flags | |
51 | * | |
52 | * This is used only when _PAGE_PRESENT is cleared. | |
53 | */ | |
54 | #define _PAGE_INVALID _RPAGE_SW0 | |
6aa59f51 AK |
55 | |
56 | /* | |
57 | * Top and bottom bits of RPN which can be used by hash | |
58 | * translation mode, because we expect them to be zero | |
59 | * otherwise. | |
60 | */ | |
32789d38 AK |
61 | #define _RPAGE_RPN0 0x01000 |
62 | #define _RPAGE_RPN1 0x02000 | |
6aa59f51 AK |
63 | #define _RPAGE_RPN43 0x0080000000000000UL |
64 | #define _RPAGE_RPN42 0x0040000000000000UL | |
65 | #define _RPAGE_RPN41 0x0020000000000000UL | |
049d567a | 66 | |
2f18d533 | 67 | /* Max physical address bit as per radix table */ |
ee8b3933 | 68 | #define _RPAGE_PA_MAX 56 |
2f18d533 AK |
69 | |
70 | /* | |
71 | * Max physical address bit we will use for now. | |
72 | * | |
73 | * This is mostly a hardware limitation and for now Power9 has | |
74 | * a 51 bit limit. | |
75 | * | |
76 | * This is different from the number of physical bit required to address | |
77 | * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. | |
78 | * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum | |
79 | * number of sections we can support (SECTIONS_SHIFT). | |
80 | * | |
81 | * This is different from Radix page table limitation above and | |
82 | * should always be less than that. The limit is done such that | |
83 | * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX | |
84 | * for hash linux page table specific bits. | |
85 | * | |
86 | * In order to be compatible with future hardware generations we keep | |
87 | * some offsets and limit this for now to 53 | |
88 | */ | |
89 | #define _PAGE_PA_MAX 53 | |
90 | ||
69dfbaeb | 91 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
69dfbaeb | 92 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
ebd31197 | 93 | #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ |
ebd31197 | 94 | |
2e873519 AK |
95 | /* |
96 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
97 | * Instead of fixing all of them, add an alternate define which | |
98 | * maps CI pte mapping. | |
99 | */ | |
100 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
101 | /* | |
2f18d533 AK |
102 | * We support _RPAGE_PA_MAX bit real address in pte. On the linux side |
103 | * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX | |
104 | * and every thing below PAGE_SHIFT; | |
2e873519 | 105 | */ |
2f18d533 | 106 | #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) |
2e873519 AK |
107 | /* |
108 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
109 | * in here, on radix we expect them to be zero. | |
110 | */ | |
111 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
112 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
4628a645 | 113 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
114 | /* |
115 | * user access blocked by key | |
116 | */ | |
117 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
118 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
56bec2f9 | 119 | #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) |
6cc07821 | 120 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) |
2e873519 AK |
121 | /* |
122 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
123 | * pgprot changes | |
124 | */ | |
125 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
126 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
4628a645 | 127 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
eb95d016 | 128 | |
3dfcb315 | 129 | /* |
2e873519 AK |
130 | * We define 2 sets of base prot bits, one for basic pages (ie, |
131 | * cacheable kernel and user pages) and one for non cacheable | |
132 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
133 | * the processor might need it for DMA coherency. | |
3dfcb315 | 134 | */ |
093d7ca2 | 135 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
2e873519 AK |
136 | #define _PAGE_BASE (_PAGE_BASE_NC) |
137 | ||
138 | /* Permission masks used to generate the __P and __S table, | |
139 | * | |
140 | * Note:__pgprot is defined in arch/powerpc/include/asm/page.h | |
141 | * | |
142 | * Write permissions imply read permissions for now (we could make write-only | |
143 | * pages on BookE but we don't bother for now). Execute permission control is | |
144 | * possible on platforms that define _PAGE_EXEC | |
2e873519 AK |
145 | */ |
146 | #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) | |
147 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) | |
148 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) | |
149 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) | |
150 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
151 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) | |
152 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
395cac77 RC |
153 | /* Radix only, Hash uses PAGE_READONLY_X + execute-only pkey instead */ |
154 | #define PAGE_EXECONLY __pgprot(_PAGE_BASE | _PAGE_EXEC) | |
2e873519 | 155 | |
2e873519 AK |
156 | /* Permission masks used for kernel mappings */ |
157 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
6cc07821 CL |
158 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) |
159 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) | |
2e873519 AK |
160 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) |
161 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
162 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
163 | ||
dd1842a2 AK |
164 | #ifndef __ASSEMBLY__ |
165 | /* | |
166 | * page table defines | |
167 | */ | |
168 | extern unsigned long __pte_index_size; | |
169 | extern unsigned long __pmd_index_size; | |
170 | extern unsigned long __pud_index_size; | |
171 | extern unsigned long __pgd_index_size; | |
fae22116 | 172 | extern unsigned long __pud_cache_index; |
dd1842a2 AK |
173 | #define PTE_INDEX_SIZE __pte_index_size |
174 | #define PMD_INDEX_SIZE __pmd_index_size | |
175 | #define PUD_INDEX_SIZE __pud_index_size | |
176 | #define PGD_INDEX_SIZE __pgd_index_size | |
738f9645 AK |
177 | /* pmd table use page table fragments */ |
178 | #define PMD_CACHE_INDEX 0 | |
fae22116 | 179 | #define PUD_CACHE_INDEX __pud_cache_index |
dd1842a2 AK |
180 | /* |
181 | * Because of use of pte fragments and THP, size of page table | |
182 | * are not always derived out of index size above. | |
183 | */ | |
184 | extern unsigned long __pte_table_size; | |
185 | extern unsigned long __pmd_table_size; | |
186 | extern unsigned long __pud_table_size; | |
187 | extern unsigned long __pgd_table_size; | |
188 | #define PTE_TABLE_SIZE __pte_table_size | |
189 | #define PMD_TABLE_SIZE __pmd_table_size | |
190 | #define PUD_TABLE_SIZE __pud_table_size | |
191 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
192 | |
193 | extern unsigned long __pmd_val_bits; | |
194 | extern unsigned long __pud_val_bits; | |
195 | extern unsigned long __pgd_val_bits; | |
196 | #define PMD_VAL_BITS __pmd_val_bits | |
197 | #define PUD_VAL_BITS __pud_val_bits | |
198 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
199 | |
200 | extern unsigned long __pte_frag_nr; | |
201 | #define PTE_FRAG_NR __pte_frag_nr | |
202 | extern unsigned long __pte_frag_size_shift; | |
203 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
204 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 | 205 | |
8a6c697b AK |
206 | extern unsigned long __pmd_frag_nr; |
207 | #define PMD_FRAG_NR __pmd_frag_nr | |
208 | extern unsigned long __pmd_frag_size_shift; | |
209 | #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift | |
210 | #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) | |
211 | ||
dd1842a2 AK |
212 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) |
213 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
214 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
215 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
216 | ||
41b7a347 DA |
217 | #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) |
218 | #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) | |
219 | #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) | |
e72421a0 CL |
220 | #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ |
221 | H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) | |
222 | ||
dd1842a2 AK |
223 | /* PMD_SHIFT determines what a second-level page table entry can map */ |
224 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
225 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
226 | #define PMD_MASK (~(PMD_SIZE-1)) | |
227 | ||
228 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
229 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
230 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
231 | #define PUD_MASK (~(PUD_SIZE-1)) | |
232 | ||
233 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
234 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
235 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
236 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
237 | ||
238 | /* Bits to mask out from a PMD to get to the PTE page */ | |
239 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
240 | /* Bits to mask out from a PUD to get to the PMD page */ | |
241 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
242 | /* Bits to mask out from a PGD to get to the PUD page */ | |
2fb47060 | 243 | #define P4D_MASKED_BITS 0xc0000000000000ffUL |
d6a9996e | 244 | |
0c4d2680 AK |
245 | /* |
246 | * Used as an indicator for rcu callback functions | |
247 | */ | |
248 | enum pgtable_index { | |
249 | PTE_INDEX = 0, | |
250 | PMD_INDEX, | |
251 | PUD_INDEX, | |
252 | PGD_INDEX, | |
fadd03c6 AK |
253 | /* |
254 | * Below are used with 4k page size and hugetlb | |
255 | */ | |
256 | HTLB_16M_INDEX, | |
257 | HTLB_16G_INDEX, | |
0c4d2680 AK |
258 | }; |
259 | ||
d6a9996e AK |
260 | extern unsigned long __vmalloc_start; |
261 | extern unsigned long __vmalloc_end; | |
262 | #define VMALLOC_START __vmalloc_start | |
263 | #define VMALLOC_END __vmalloc_end | |
264 | ||
d909f910 NP |
265 | static inline unsigned int ioremap_max_order(void) |
266 | { | |
267 | if (radix_enabled()) | |
268 | return PUD_SHIFT; | |
269 | return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ | |
270 | } | |
271 | #define IOREMAP_MAX_ORDER ioremap_max_order() | |
272 | ||
d6a9996e | 273 | extern unsigned long __kernel_virt_start; |
63ee9b2f | 274 | extern unsigned long __kernel_io_start; |
a35a3c6f | 275 | extern unsigned long __kernel_io_end; |
d6a9996e | 276 | #define KERN_VIRT_START __kernel_virt_start |
63ee9b2f | 277 | #define KERN_IO_START __kernel_io_start |
a35a3c6f AK |
278 | #define KERN_IO_END __kernel_io_end |
279 | ||
d6a9996e | 280 | extern struct page *vmemmap; |
bfa37087 | 281 | extern unsigned long pci_io_base; |
dd1842a2 | 282 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 283 | |
ab537dca | 284 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 285 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 286 | |
b32d5d7e AK |
287 | #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS |
288 | #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS | |
289 | #else | |
290 | #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS | |
291 | #endif | |
292 | ||
293 | ||
a9252aae AK |
294 | #ifdef CONFIG_PPC_64K_PAGES |
295 | #include <asm/book3s/64/pgtable-64k.h> | |
296 | #else | |
297 | #include <asm/book3s/64/pgtable-4k.h> | |
298 | #endif | |
299 | ||
3dfcb315 | 300 | #include <asm/barrier.h> |
3dfcb315 | 301 | /* |
a35a3c6f | 302 | * IO space itself carved into the PIO region (ISA and PHB IO space) and |
3dfcb315 AK |
303 | * the ioremap space |
304 | * | |
305 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
306 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
307 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
308 | */ | |
3dfcb315 AK |
309 | #define FULL_IO_SIZE 0x80000000ul |
310 | #define ISA_IO_BASE (KERN_IO_START) | |
311 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
312 | #define PHB_IO_BASE (ISA_IO_END) | |
313 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
314 | #define IOREMAP_BASE (PHB_IO_END) | |
4a45b746 | 315 | #define IOREMAP_START (ioremap_bot) |
9ccba66d CL |
316 | #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) |
317 | #define FIXADDR_SIZE SZ_32M | |
3dfcb315 | 318 | |
3dfcb315 AK |
319 | #ifndef __ASSEMBLY__ |
320 | ||
321 | /* | |
322 | * This is the default implementation of various PTE accessors, it's | |
323 | * used in all cases except Book3S with 64K pages where we have a | |
324 | * concept of sub-pages | |
325 | */ | |
326 | #ifndef __real_pte | |
327 | ||
ff31e105 | 328 | #define __real_pte(e, p, o) ((real_pte_t){(e)}) |
3dfcb315 | 329 | #define __rpte_to_pte(r) ((r).pte) |
945537df | 330 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
331 | |
332 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
333 | do { \ | |
334 | index = 0; \ | |
335 | shift = mmu_psize_defs[psize].shift; \ | |
336 | ||
337 | #define pte_iterate_hashed_end() } while(0) | |
338 | ||
339 | /* | |
340 | * We expect this to be called only for user addresses or kernel virtual | |
341 | * addresses other than the linear mapping. | |
342 | */ | |
343 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
344 | ||
345 | #endif /* __real_pte */ | |
346 | ||
ac94ac79 AK |
347 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
348 | pte_t *ptep, unsigned long clr, | |
349 | unsigned long set, int huge) | |
350 | { | |
351 | if (radix_enabled()) | |
352 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
353 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
354 | } | |
13f829a5 AK |
355 | /* |
356 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
357 | * We currently remove entries from the hashtable regardless of whether | |
358 | * the entry was young or dirty. | |
359 | * | |
360 | * We should be more intelligent about this but for the moment we override | |
361 | * these functions and force a tlb flush unconditionally | |
362 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
363 | * function for both hash and radix. | |
364 | */ | |
365 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
366 | unsigned long addr, pte_t *ptep) | |
367 | { | |
368 | unsigned long old; | |
369 | ||
66c570f5 | 370 | if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
13f829a5 AK |
371 | return 0; |
372 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
373 | return (old & _PAGE_ACCESSED) != 0; | |
374 | } | |
375 | ||
376 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
377 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
378 | ({ \ | |
3cb1aa7a | 379 | __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ |
13f829a5 AK |
380 | }) |
381 | ||
3cb1aa7a NP |
382 | /* |
383 | * On Book3S CPUs, clearing the accessed bit without a TLB flush | |
384 | * doesn't cause data corruption. [ It could cause incorrect | |
385 | * page aging and the (mistaken) reclaim of hot pages, but the | |
386 | * chance of that should be relatively low. ] | |
387 | * | |
388 | * So as a performance optimization don't flush the TLB when | |
389 | * clearing the accessed bit, it will eventually be flushed by | |
390 | * a context switch or a VM operation anyway. [ In the rare | |
391 | * event of it not getting flushed for a long time the delay | |
392 | * shouldn't really matter because there's no real memory | |
393 | * pressure for swapout to react to. ] | |
b11931e9 NP |
394 | * |
395 | * Note: this optimisation also exists in pte_needs_flush() and | |
396 | * huge_pmd_needs_flush(). | |
3cb1aa7a NP |
397 | */ |
398 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
399 | #define ptep_clear_flush_young ptep_test_and_clear_young | |
400 | ||
401 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
402 | #define pmdp_clear_flush_young pmdp_test_and_clear_young | |
403 | ||
d19469e8 | 404 | static inline int __pte_write(pte_t pte) |
52c50ca7 AK |
405 | { |
406 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); | |
407 | } | |
408 | ||
409 | #ifdef CONFIG_NUMA_BALANCING | |
410 | #define pte_savedwrite pte_savedwrite | |
411 | static inline bool pte_savedwrite(pte_t pte) | |
412 | { | |
413 | /* | |
414 | * Saved write ptes are prot none ptes that doesn't have | |
415 | * privileged bit sit. We mark prot none as one which has | |
416 | * present and pviliged bit set and RWX cleared. To mark | |
417 | * protnone which used to have _PAGE_WRITE set we clear | |
418 | * the privileged bit. | |
419 | */ | |
420 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_RWX | _PAGE_PRIVILEGED)); | |
421 | } | |
422 | #else | |
423 | #define pte_savedwrite pte_savedwrite | |
424 | static inline bool pte_savedwrite(pte_t pte) | |
425 | { | |
426 | return false; | |
427 | } | |
428 | #endif | |
429 | ||
d19469e8 AK |
430 | static inline int pte_write(pte_t pte) |
431 | { | |
432 | return __pte_write(pte) || pte_savedwrite(pte); | |
433 | } | |
434 | ||
ca8afd40 CL |
435 | static inline int pte_read(pte_t pte) |
436 | { | |
437 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); | |
438 | } | |
439 | ||
13f829a5 AK |
440 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
441 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
442 | pte_t *ptep) | |
443 | { | |
d19469e8 | 444 | if (__pte_write(*ptep)) |
52c50ca7 AK |
445 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); |
446 | else if (unlikely(pte_savedwrite(*ptep))) | |
447 | pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 0); | |
13f829a5 AK |
448 | } |
449 | ||
8e581d43 | 450 | #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT |
13f829a5 AK |
451 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, |
452 | unsigned long addr, pte_t *ptep) | |
453 | { | |
52c50ca7 AK |
454 | /* |
455 | * We should not find protnone for hugetlb, but this complete the | |
456 | * interface. | |
457 | */ | |
d19469e8 | 458 | if (__pte_write(*ptep)) |
52c50ca7 AK |
459 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); |
460 | else if (unlikely(pte_savedwrite(*ptep))) | |
461 | pte_update(mm, addr, ptep, 0, _PAGE_PRIVILEGED, 1); | |
13f829a5 AK |
462 | } |
463 | ||
464 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
465 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
466 | unsigned long addr, pte_t *ptep) | |
467 | { | |
468 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
469 | return __pte(old); | |
470 | } | |
471 | ||
f4894b80 AK |
472 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
473 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
474 | unsigned long addr, | |
475 | pte_t *ptep, int full) | |
476 | { | |
477 | if (full && radix_enabled()) { | |
478 | /* | |
2bf1071a NP |
479 | * We know that this is a full mm pte clear and |
480 | * hence can be sure there is no parallel set_pte. | |
f4894b80 AK |
481 | */ |
482 | return radix__ptep_get_and_clear_full(mm, addr, ptep, full); | |
483 | } | |
484 | return ptep_get_and_clear(mm, addr, ptep); | |
485 | } | |
486 | ||
487 | ||
13f829a5 AK |
488 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
489 | pte_t * ptep) | |
490 | { | |
491 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
492 | } | |
66c570f5 | 493 | |
66c570f5 AK |
494 | static inline int pte_dirty(pte_t pte) |
495 | { | |
496 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); | |
497 | } | |
498 | ||
499 | static inline int pte_young(pte_t pte) | |
500 | { | |
501 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); | |
502 | } | |
503 | ||
504 | static inline int pte_special(pte_t pte) | |
505 | { | |
506 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); | |
507 | } | |
508 | ||
daba7902 CL |
509 | static inline bool pte_exec(pte_t pte) |
510 | { | |
511 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); | |
512 | } | |
513 | ||
13f829a5 AK |
514 | |
515 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
516 | static inline bool pte_soft_dirty(pte_t pte) | |
517 | { | |
66c570f5 | 518 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 | 519 | } |
66c570f5 | 520 | |
13f829a5 AK |
521 | static inline pte_t pte_mksoft_dirty(pte_t pte) |
522 | { | |
1b2443a5 | 523 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
524 | } |
525 | ||
526 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
527 | { | |
1b2443a5 | 528 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
529 | } |
530 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
531 | ||
532 | #ifdef CONFIG_NUMA_BALANCING | |
13f829a5 AK |
533 | static inline int pte_protnone(pte_t pte) |
534 | { | |
c137a275 AK |
535 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == |
536 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
537 | } | |
538 | ||
539 | #define pte_mk_savedwrite pte_mk_savedwrite | |
540 | static inline pte_t pte_mk_savedwrite(pte_t pte) | |
541 | { | |
542 | /* | |
543 | * Used by Autonuma subsystem to preserve the write bit | |
544 | * while marking the pte PROT_NONE. Only allow this | |
545 | * on PROT_NONE pte | |
546 | */ | |
547 | VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) != | |
548 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)); | |
1b2443a5 | 549 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); |
c137a275 AK |
550 | } |
551 | ||
552 | #define pte_clear_savedwrite pte_clear_savedwrite | |
553 | static inline pte_t pte_clear_savedwrite(pte_t pte) | |
554 | { | |
555 | /* | |
556 | * Used by KSM subsystem to make a protnone pte readonly. | |
557 | */ | |
558 | VM_BUG_ON(!pte_protnone(pte)); | |
1b2443a5 | 559 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); |
c137a275 | 560 | } |
d19469e8 AK |
561 | #else |
562 | #define pte_clear_savedwrite pte_clear_savedwrite | |
563 | static inline pte_t pte_clear_savedwrite(pte_t pte) | |
564 | { | |
565 | VM_WARN_ON(1); | |
1b2443a5 | 566 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
d19469e8 | 567 | } |
13f829a5 AK |
568 | #endif /* CONFIG_NUMA_BALANCING */ |
569 | ||
ec4abf1e AK |
570 | static inline bool pte_hw_valid(pte_t pte) |
571 | { | |
572 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == | |
573 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
574 | } | |
575 | ||
13f829a5 AK |
576 | static inline int pte_present(pte_t pte) |
577 | { | |
bd0dbb73 AK |
578 | /* |
579 | * A pte is considerent present if _PAGE_PRESENT is set. | |
580 | * We also need to consider the pte present which is marked | |
581 | * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID | |
582 | * if we find _PAGE_PRESENT cleared. | |
583 | */ | |
f72a85e3 | 584 | |
ec4abf1e AK |
585 | if (pte_hw_valid(pte)) |
586 | return true; | |
587 | return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == | |
588 | cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); | |
daba7902 CL |
589 | } |
590 | ||
bca7aacf | 591 | #ifdef CONFIG_PPC_MEM_KEYS |
f2407ef3 | 592 | extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); |
bca7aacf RP |
593 | #else |
594 | static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) | |
595 | { | |
596 | return true; | |
597 | } | |
598 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
f2407ef3 | 599 | |
1b2443a5 CL |
600 | static inline bool pte_user(pte_t pte) |
601 | { | |
602 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); | |
603 | } | |
604 | ||
f72a85e3 AK |
605 | #define pte_access_permitted pte_access_permitted |
606 | static inline bool pte_access_permitted(pte_t pte, bool write) | |
607 | { | |
f72a85e3 AK |
608 | /* |
609 | * _PAGE_READ is needed for any access and will be | |
610 | * cleared for PROT_NONE | |
611 | */ | |
1b2443a5 | 612 | if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) |
f72a85e3 AK |
613 | return false; |
614 | ||
1b2443a5 | 615 | if (write && !pte_write(pte)) |
f72a85e3 | 616 | return false; |
bca7aacf RP |
617 | |
618 | return arch_pte_access_permitted(pte_val(pte), write, 0); | |
f72a85e3 AK |
619 | } |
620 | ||
13f829a5 AK |
621 | /* |
622 | * Conversion functions: convert a page and protection to a page entry, | |
623 | * and a page entry and page directory to the page they refer to. | |
624 | * | |
625 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
626 | * long for now. | |
627 | */ | |
628 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
629 | { | |
6bb25170 NP |
630 | VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); |
631 | VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); | |
632 | ||
379c926d | 633 | return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); |
13f829a5 AK |
634 | } |
635 | ||
636 | static inline unsigned long pte_pfn(pte_t pte) | |
637 | { | |
638 | return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; | |
639 | } | |
640 | ||
641 | /* Generic modifiers for PTE bits */ | |
642 | static inline pte_t pte_wrprotect(pte_t pte) | |
643 | { | |
d19469e8 AK |
644 | if (unlikely(pte_savedwrite(pte))) |
645 | return pte_clear_savedwrite(pte); | |
1b2443a5 | 646 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
13f829a5 AK |
647 | } |
648 | ||
daba7902 CL |
649 | static inline pte_t pte_exprotect(pte_t pte) |
650 | { | |
1b2443a5 | 651 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); |
13f829a5 AK |
652 | } |
653 | ||
654 | static inline pte_t pte_mkclean(pte_t pte) | |
655 | { | |
1b2443a5 | 656 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); |
13f829a5 AK |
657 | } |
658 | ||
659 | static inline pte_t pte_mkold(pte_t pte) | |
660 | { | |
1b2443a5 | 661 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); |
13f829a5 AK |
662 | } |
663 | ||
daba7902 CL |
664 | static inline pte_t pte_mkexec(pte_t pte) |
665 | { | |
1b2443a5 | 666 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); |
daba7902 CL |
667 | } |
668 | ||
13f829a5 AK |
669 | static inline pte_t pte_mkwrite(pte_t pte) |
670 | { | |
671 | /* | |
672 | * write implies read, hence set both | |
673 | */ | |
1b2443a5 | 674 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); |
13f829a5 AK |
675 | } |
676 | ||
677 | static inline pte_t pte_mkdirty(pte_t pte) | |
678 | { | |
1b2443a5 | 679 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); |
13f829a5 AK |
680 | } |
681 | ||
682 | static inline pte_t pte_mkyoung(pte_t pte) | |
683 | { | |
1b2443a5 | 684 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); |
13f829a5 AK |
685 | } |
686 | ||
687 | static inline pte_t pte_mkspecial(pte_t pte) | |
688 | { | |
1b2443a5 | 689 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); |
13f829a5 AK |
690 | } |
691 | ||
692 | static inline pte_t pte_mkhuge(pte_t pte) | |
693 | { | |
694 | return pte; | |
695 | } | |
696 | ||
ebd31197 OH |
697 | static inline pte_t pte_mkdevmap(pte_t pte) |
698 | { | |
1b2443a5 | 699 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); |
ebd31197 OH |
700 | } |
701 | ||
daba7902 CL |
702 | static inline pte_t pte_mkprivileged(pte_t pte) |
703 | { | |
1b2443a5 | 704 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED)); |
daba7902 CL |
705 | } |
706 | ||
707 | static inline pte_t pte_mkuser(pte_t pte) | |
708 | { | |
1b2443a5 | 709 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED)); |
ebd31197 OH |
710 | } |
711 | ||
c9c98bc5 OH |
712 | /* |
713 | * This is potentially called with a pmd as the argument, in which case it's not | |
714 | * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. | |
715 | * That's because the bit we use for _PAGE_DEVMAP is not reserved for software | |
716 | * use in page directory entries (ie. non-ptes). | |
717 | */ | |
ebd31197 OH |
718 | static inline int pte_devmap(pte_t pte) |
719 | { | |
c9c98bc5 OH |
720 | u64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); |
721 | ||
722 | return (pte_raw(pte) & mask) == mask; | |
ebd31197 OH |
723 | } |
724 | ||
13f829a5 AK |
725 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
726 | { | |
727 | /* FIXME!! check whether this need to be a conditional */ | |
1b2443a5 CL |
728 | return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | |
729 | cpu_to_be64(pgprot_val(newprot))); | |
34fbadd8 AK |
730 | } |
731 | ||
732 | /* Encode and de-code a swap entry */ | |
733 | #define MAX_SWAPFILES_CHECK() do { \ | |
734 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
735 | /* \ | |
736 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
737 | * We filter HPTEFLAGS on set_pte. \ | |
738 | */ \ | |
03ac1b71 | 739 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ |
34fbadd8 | 740 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ |
bff9beaa | 741 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ |
34fbadd8 | 742 | } while (0) |
3159f943 | 743 | |
34fbadd8 | 744 | #define SWP_TYPE_BITS 5 |
03ac1b71 DH |
745 | #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) |
746 | #define __swp_type(x) ((x).val & SWP_TYPE_MASK) | |
34fbadd8 AK |
747 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) |
748 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
03ac1b71 | 749 | (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) |
34fbadd8 AK |
750 | /* |
751 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
752 | * swap type and offset we get from swap and convert that to pte to find a | |
753 | * matching pte in linux page table. | |
754 | * Clear bits not found in swap entries here. | |
755 | */ | |
756 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
757 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
a0820ff3 AK |
758 | #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) |
759 | #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) | |
34fbadd8 AK |
760 | |
761 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
bff9beaa | 762 | #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY |
34fbadd8 AK |
763 | #else |
764 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
765 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
766 | ||
bff9beaa DH |
767 | #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT |
768 | ||
34fbadd8 AK |
769 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
770 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
771 | { | |
1b2443a5 | 772 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 773 | } |
66c570f5 | 774 | |
34fbadd8 AK |
775 | static inline bool pte_swp_soft_dirty(pte_t pte) |
776 | { | |
66c570f5 | 777 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 778 | } |
66c570f5 | 779 | |
34fbadd8 AK |
780 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) |
781 | { | |
1b2443a5 | 782 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 AK |
783 | } |
784 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
785 | ||
bff9beaa DH |
786 | #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE |
787 | static inline pte_t pte_swp_mkexclusive(pte_t pte) | |
788 | { | |
789 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
790 | } | |
791 | ||
792 | static inline int pte_swp_exclusive(pte_t pte) | |
793 | { | |
794 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
795 | } | |
796 | ||
797 | static inline pte_t pte_swp_clear_exclusive(pte_t pte) | |
798 | { | |
799 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); | |
800 | } | |
801 | ||
34fbadd8 AK |
802 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) |
803 | { | |
804 | /* | |
805 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
806 | */ | |
807 | if (access & ~ptev) | |
808 | return false; | |
809 | /* | |
810 | * This check for access to privilege space | |
811 | */ | |
812 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
813 | return false; | |
814 | ||
815 | return true; | |
816 | } | |
ac94ac79 AK |
817 | /* |
818 | * Generic functions with hash/radix callbacks | |
819 | */ | |
820 | ||
e4c1112c | 821 | static inline void __ptep_set_access_flags(struct vm_area_struct *vma, |
b3603e17 | 822 | pte_t *ptep, pte_t entry, |
e4c1112c AK |
823 | unsigned long address, |
824 | int psize) | |
ac94ac79 AK |
825 | { |
826 | if (radix_enabled()) | |
e4c1112c AK |
827 | return radix__ptep_set_access_flags(vma, ptep, entry, |
828 | address, psize); | |
ac94ac79 AK |
829 | return hash__ptep_set_access_flags(ptep, entry); |
830 | } | |
831 | ||
832 | #define __HAVE_ARCH_PTE_SAME | |
833 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
834 | { | |
835 | if (radix_enabled()) | |
836 | return radix__pte_same(pte_a, pte_b); | |
837 | return hash__pte_same(pte_a, pte_b); | |
838 | } | |
839 | ||
840 | static inline int pte_none(pte_t pte) | |
841 | { | |
842 | if (radix_enabled()) | |
843 | return radix__pte_none(pte); | |
844 | return hash__pte_none(pte); | |
845 | } | |
846 | ||
847 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
848 | pte_t *ptep, pte_t pte, int percpu) | |
849 | { | |
379c926d AK |
850 | |
851 | VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); | |
852 | /* | |
853 | * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE | |
854 | * in all the callers. | |
855 | */ | |
856 | pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); | |
857 | ||
ac94ac79 AK |
858 | if (radix_enabled()) |
859 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
860 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
861 | } | |
34fbadd8 | 862 | |
12564485 SA |
863 | #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
864 | ||
13f829a5 AK |
865 | #define pgprot_noncached pgprot_noncached |
866 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
867 | { | |
868 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
869 | _PAGE_NON_IDEMPOTENT); | |
870 | } | |
871 | ||
872 | #define pgprot_noncached_wc pgprot_noncached_wc | |
873 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
874 | { | |
875 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
876 | _PAGE_TOLERANT); | |
877 | } | |
878 | ||
879 | #define pgprot_cached pgprot_cached | |
880 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
881 | { | |
882 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
883 | } | |
884 | ||
885 | #define pgprot_writecombine pgprot_writecombine | |
886 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
887 | { | |
888 | return pgprot_noncached_wc(prot); | |
889 | } | |
890 | /* | |
891 | * check a pte mapping have cache inhibited property | |
892 | */ | |
893 | static inline bool pte_ci(pte_t pte) | |
894 | { | |
1b2443a5 | 895 | __be64 pte_v = pte_raw(pte); |
13f829a5 | 896 | |
1b2443a5 CL |
897 | if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || |
898 | ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) | |
13f829a5 AK |
899 | return true; |
900 | return false; | |
901 | } | |
902 | ||
f281b5d5 AK |
903 | static inline void pmd_clear(pmd_t *pmdp) |
904 | { | |
392b4669 AK |
905 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
906 | /* | |
907 | * Don't use this if we can possibly have a hash page table | |
908 | * entry mapping this. | |
909 | */ | |
910 | WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
911 | } | |
f281b5d5 AK |
912 | *pmdp = __pmd(0); |
913 | } | |
914 | ||
66c570f5 AK |
915 | static inline int pmd_none(pmd_t pmd) |
916 | { | |
917 | return !pmd_raw(pmd); | |
918 | } | |
919 | ||
920 | static inline int pmd_present(pmd_t pmd) | |
921 | { | |
da7ad366 AK |
922 | /* |
923 | * A pmd is considerent present if _PAGE_PRESENT is set. | |
924 | * We also need to consider the pmd present which is marked | |
925 | * invalid during a split. Hence we look for _PAGE_INVALID | |
926 | * if we find _PAGE_PRESENT cleared. | |
927 | */ | |
928 | if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) | |
929 | return true; | |
66c570f5 | 930 | |
da7ad366 | 931 | return false; |
66c570f5 | 932 | } |
3dfcb315 | 933 | |
33258a1d NP |
934 | static inline int pmd_is_serializing(pmd_t pmd) |
935 | { | |
936 | /* | |
937 | * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear | |
938 | * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). | |
939 | * | |
940 | * This condition may also occur when flushing a pmd while flushing | |
941 | * it (see ptep_modify_prot_start), so callers must ensure this | |
942 | * case is fine as well. | |
943 | */ | |
944 | if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == | |
945 | cpu_to_be64(_PAGE_INVALID)) | |
946 | return true; | |
947 | ||
948 | return false; | |
949 | } | |
950 | ||
ac94ac79 AK |
951 | static inline int pmd_bad(pmd_t pmd) |
952 | { | |
953 | if (radix_enabled()) | |
954 | return radix__pmd_bad(pmd); | |
955 | return hash__pmd_bad(pmd); | |
956 | } | |
957 | ||
f281b5d5 AK |
958 | static inline void pud_clear(pud_t *pudp) |
959 | { | |
392b4669 AK |
960 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
961 | /* | |
962 | * Don't use this if we can possibly have a hash page table | |
963 | * entry mapping this. | |
964 | */ | |
965 | WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
966 | } | |
f281b5d5 AK |
967 | *pudp = __pud(0); |
968 | } | |
969 | ||
66c570f5 AK |
970 | static inline int pud_none(pud_t pud) |
971 | { | |
972 | return !pud_raw(pud); | |
973 | } | |
974 | ||
975 | static inline int pud_present(pud_t pud) | |
976 | { | |
a5800762 | 977 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 978 | } |
3dfcb315 AK |
979 | |
980 | extern struct page *pud_page(pud_t pud); | |
371352ca | 981 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
982 | static inline pte_t pud_pte(pud_t pud) |
983 | { | |
66c570f5 | 984 | return __pte_raw(pud_raw(pud)); |
3dfcb315 AK |
985 | } |
986 | ||
987 | static inline pud_t pte_pud(pte_t pte) | |
988 | { | |
66c570f5 | 989 | return __pud_raw(pte_raw(pte)); |
3dfcb315 AK |
990 | } |
991 | #define pud_write(pud) pte_write(pud_pte(pud)) | |
ac94ac79 AK |
992 | |
993 | static inline int pud_bad(pud_t pud) | |
994 | { | |
995 | if (radix_enabled()) | |
996 | return radix__pud_bad(pud); | |
997 | return hash__pud_bad(pud); | |
998 | } | |
999 | ||
f72a85e3 AK |
1000 | #define pud_access_permitted pud_access_permitted |
1001 | static inline bool pud_access_permitted(pud_t pud, bool write) | |
1002 | { | |
1003 | return pte_access_permitted(pud_pte(pud), write); | |
1004 | } | |
ac94ac79 | 1005 | |
2fb47060 MR |
1006 | #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) |
1007 | static inline __be64 p4d_raw(p4d_t x) | |
1008 | { | |
1009 | return pgd_raw(x.pgd); | |
1010 | } | |
1011 | ||
1012 | #define p4d_write(p4d) pte_write(p4d_pte(p4d)) | |
3dfcb315 | 1013 | |
2fb47060 | 1014 | static inline void p4d_clear(p4d_t *p4dp) |
368ced78 | 1015 | { |
2fb47060 | 1016 | *p4dp = __p4d(0); |
368ced78 AK |
1017 | } |
1018 | ||
2fb47060 | 1019 | static inline int p4d_none(p4d_t p4d) |
66c570f5 | 1020 | { |
2fb47060 | 1021 | return !p4d_raw(p4d); |
66c570f5 AK |
1022 | } |
1023 | ||
2fb47060 | 1024 | static inline int p4d_present(p4d_t p4d) |
66c570f5 | 1025 | { |
2fb47060 | 1026 | return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 1027 | } |
368ced78 | 1028 | |
2fb47060 | 1029 | static inline pte_t p4d_pte(p4d_t p4d) |
368ced78 | 1030 | { |
2fb47060 | 1031 | return __pte_raw(p4d_raw(p4d)); |
368ced78 AK |
1032 | } |
1033 | ||
2fb47060 | 1034 | static inline p4d_t pte_p4d(pte_t pte) |
368ced78 | 1035 | { |
2fb47060 | 1036 | return __p4d_raw(pte_raw(pte)); |
368ced78 AK |
1037 | } |
1038 | ||
2fb47060 | 1039 | static inline int p4d_bad(p4d_t p4d) |
ac94ac79 AK |
1040 | { |
1041 | if (radix_enabled()) | |
2fb47060 MR |
1042 | return radix__p4d_bad(p4d); |
1043 | return hash__p4d_bad(p4d); | |
ac94ac79 AK |
1044 | } |
1045 | ||
2fb47060 MR |
1046 | #define p4d_access_permitted p4d_access_permitted |
1047 | static inline bool p4d_access_permitted(p4d_t p4d, bool write) | |
f72a85e3 | 1048 | { |
2fb47060 | 1049 | return pte_access_permitted(p4d_pte(p4d), write); |
f72a85e3 AK |
1050 | } |
1051 | ||
2fb47060 | 1052 | extern struct page *p4d_page(p4d_t p4d); |
368ced78 | 1053 | |
aba480e1 AK |
1054 | /* Pointers in the page table tree are physical addresses */ |
1055 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
1056 | ||
dc4875f0 AK |
1057 | static inline pud_t *p4d_pgtable(p4d_t p4d) |
1058 | { | |
1059 | return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); | |
1060 | } | |
aba480e1 | 1061 | |
9cf6fa24 AK |
1062 | static inline pmd_t *pud_pgtable(pud_t pud) |
1063 | { | |
1064 | return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); | |
1065 | } | |
1066 | ||
3dfcb315 AK |
1067 | #define pte_ERROR(e) \ |
1068 | pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | |
1069 | #define pmd_ERROR(e) \ | |
1070 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
1071 | #define pud_ERROR(e) \ |
1072 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
1073 | #define pgd_ERROR(e) \ |
1074 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
1075 | ||
c766ee72 | 1076 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) |
7207f436 | 1077 | { |
d9225ad9 AK |
1078 | if (radix_enabled()) { |
1079 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
1080 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
1081 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
1082 | #endif | |
c766ee72 | 1083 | return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); |
d9225ad9 | 1084 | } |
c766ee72 | 1085 | return hash__map_kernel_page(ea, pa, prot); |
7207f436 | 1086 | } |
31a14fae | 1087 | |
aec98260 CL |
1088 | void unmap_kernel_page(unsigned long va); |
1089 | ||
31a14fae AK |
1090 | static inline int __meminit vmemmap_create_mapping(unsigned long start, |
1091 | unsigned long page_size, | |
1092 | unsigned long phys) | |
7207f436 | 1093 | { |
d9225ad9 AK |
1094 | if (radix_enabled()) |
1095 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 1096 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 1097 | } |
31a14fae AK |
1098 | |
1099 | #ifdef CONFIG_MEMORY_HOTPLUG | |
1100 | static inline void vmemmap_remove_mapping(unsigned long start, | |
1101 | unsigned long page_size) | |
7207f436 | 1102 | { |
d9225ad9 AK |
1103 | if (radix_enabled()) |
1104 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 1105 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 1106 | } |
31a14fae | 1107 | #endif |
3dfcb315 | 1108 | |
4f703e7f JS |
1109 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1110 | static inline void __kernel_map_pages(struct page *page, int numpages, int enable) | |
1111 | { | |
1112 | if (radix_enabled()) | |
1113 | radix__kernel_map_pages(page, numpages, enable); | |
1114 | else | |
1115 | hash__kernel_map_pages(page, numpages, enable); | |
1116 | } | |
1117 | #endif | |
1118 | ||
3dfcb315 AK |
1119 | static inline pte_t pmd_pte(pmd_t pmd) |
1120 | { | |
66c570f5 | 1121 | return __pte_raw(pmd_raw(pmd)); |
3dfcb315 AK |
1122 | } |
1123 | ||
1124 | static inline pmd_t pte_pmd(pte_t pte) | |
1125 | { | |
66c570f5 | 1126 | return __pmd_raw(pte_raw(pte)); |
3dfcb315 AK |
1127 | } |
1128 | ||
1129 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
1130 | { | |
1131 | return (pte_t *)pmd; | |
1132 | } | |
3dfcb315 AK |
1133 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
1134 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
1135 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
1136 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
1137 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
1138 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 1139 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 AK |
1140 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
1141 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
c137a275 AK |
1142 | #define pmd_mk_savedwrite(pmd) pte_pmd(pte_mk_savedwrite(pmd_pte(pmd))) |
1143 | #define pmd_clear_savedwrite(pmd) pte_pmd(pte_clear_savedwrite(pmd_pte(pmd))) | |
7207f436 LD |
1144 | |
1145 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
1146 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
1147 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
1148 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
a0820ff3 AK |
1149 | |
1150 | #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION | |
1151 | #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) | |
1152 | #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) | |
1153 | #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) | |
1154 | #endif | |
7207f436 LD |
1155 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ |
1156 | ||
1ca72129 AK |
1157 | #ifdef CONFIG_NUMA_BALANCING |
1158 | static inline int pmd_protnone(pmd_t pmd) | |
1159 | { | |
1160 | return pte_protnone(pmd_pte(pmd)); | |
1161 | } | |
1162 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 | 1163 | |
3dfcb315 | 1164 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
d19469e8 | 1165 | #define __pmd_write(pmd) __pte_write(pmd_pte(pmd)) |
c137a275 | 1166 | #define pmd_savedwrite(pmd) pte_savedwrite(pmd_pte(pmd)) |
3dfcb315 | 1167 | |
f72a85e3 AK |
1168 | #define pmd_access_permitted pmd_access_permitted |
1169 | static inline bool pmd_access_permitted(pmd_t pmd, bool write) | |
1170 | { | |
33258a1d NP |
1171 | /* |
1172 | * pmdp_invalidate sets this combination (which is not caught by | |
1173 | * !pte_present() check in pte_access_permitted), to prevent | |
1174 | * lock-free lookups, as part of the serialize_against_pte_lookup() | |
1175 | * synchronisation. | |
1176 | * | |
1177 | * This also catches the case where the PTE's hardware PRESENT bit is | |
1178 | * cleared while TLB is flushed, which is suboptimal but should not | |
1179 | * be frequent. | |
1180 | */ | |
1181 | if (pmd_is_serializing(pmd)) | |
1182 | return false; | |
1183 | ||
f72a85e3 AK |
1184 | return pte_access_permitted(pmd_pte(pmd), write); |
1185 | } | |
1186 | ||
6a1ea362 AK |
1187 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1188 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
1189 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); | |
1190 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
1191 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1192 | pmd_t *pmdp, pmd_t pmd); | |
18594f9b NP |
1193 | static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, |
1194 | unsigned long addr, pmd_t *pmd) | |
1195 | { | |
1196 | } | |
1197 | ||
3df33f12 AK |
1198 | extern int hash__has_transparent_hugepage(void); |
1199 | static inline int has_transparent_hugepage(void) | |
1200 | { | |
bde3eb62 AK |
1201 | if (radix_enabled()) |
1202 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
1203 | return hash__has_transparent_hugepage(); |
1204 | } | |
c04a5880 | 1205 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 1206 | |
3df33f12 AK |
1207 | static inline unsigned long |
1208 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
1209 | unsigned long clr, unsigned long set) | |
3dfcb315 | 1210 | { |
bde3eb62 AK |
1211 | if (radix_enabled()) |
1212 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
1213 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
1214 | } | |
1215 | ||
8890e033 AK |
1216 | /* |
1217 | * returns true for pmd migration entries, THP, devmap, hugetlb | |
1218 | * But compile time dependent on THP config | |
1219 | */ | |
3df33f12 AK |
1220 | static inline int pmd_large(pmd_t pmd) |
1221 | { | |
66c570f5 | 1222 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); |
3df33f12 AK |
1223 | } |
1224 | ||
3df33f12 AK |
1225 | /* |
1226 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
1227 | * the below will work for radix too | |
1228 | */ | |
1229 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
1230 | unsigned long addr, pmd_t *pmdp) | |
1231 | { | |
1232 | unsigned long old; | |
1233 | ||
66c570f5 | 1234 | if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
3df33f12 AK |
1235 | return 0; |
1236 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
1237 | return ((old & _PAGE_ACCESSED) != 0); | |
1238 | } | |
1239 | ||
1240 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
1241 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1242 | pmd_t *pmdp) | |
1243 | { | |
d19469e8 | 1244 | if (__pmd_write((*pmdp))) |
52c50ca7 AK |
1245 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); |
1246 | else if (unlikely(pmd_savedwrite(*pmdp))) | |
1247 | pmd_hugepage_update(mm, addr, pmdp, 0, _PAGE_PRIVILEGED); | |
3dfcb315 AK |
1248 | } |
1249 | ||
8890e033 AK |
1250 | /* |
1251 | * Only returns true for a THP. False for pmd migration entry. | |
1252 | * We also need to return true when we come across a pte that | |
1253 | * in between a thp split. While splitting THP, we mark the pmd | |
1254 | * invalid (pmdp_invalidate()) before we set it with pte page | |
1255 | * address. A pmd_trans_huge() check against a pmd entry during that time | |
1256 | * should return true. | |
1257 | * We should not call this on a hugetlb entry. We should check for HugeTLB | |
1258 | * entry using vma->vm_flags | |
ee65728e | 1259 | * The page table walk rule is explained in Documentation/mm/transhuge.rst |
8890e033 | 1260 | */ |
ab624762 AK |
1261 | static inline int pmd_trans_huge(pmd_t pmd) |
1262 | { | |
8890e033 AK |
1263 | if (!pmd_present(pmd)) |
1264 | return false; | |
1265 | ||
ab624762 AK |
1266 | if (radix_enabled()) |
1267 | return radix__pmd_trans_huge(pmd); | |
1268 | return hash__pmd_trans_huge(pmd); | |
1269 | } | |
1270 | ||
1271 | #define __HAVE_ARCH_PMD_SAME | |
1272 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
1273 | { | |
1274 | if (radix_enabled()) | |
1275 | return radix__pmd_same(pmd_a, pmd_b); | |
1276 | return hash__pmd_same(pmd_a, pmd_b); | |
1277 | } | |
1278 | ||
53f45ecc | 1279 | static inline pmd_t __pmd_mkhuge(pmd_t pmd) |
3dfcb315 | 1280 | { |
ab624762 AK |
1281 | if (radix_enabled()) |
1282 | return radix__pmd_mkhuge(pmd); | |
1283 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
1284 | } |
1285 | ||
53f45ecc AK |
1286 | /* |
1287 | * pfn_pmd return a pmd_t that can be used as pmd pte entry. | |
1288 | */ | |
1289 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1290 | { | |
1291 | #ifdef CONFIG_DEBUG_VM | |
1292 | if (radix_enabled()) | |
1293 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1294 | else | |
1295 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != | |
1296 | cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); | |
1297 | #endif | |
1298 | return pmd; | |
1299 | } | |
1300 | ||
3dfcb315 AK |
1301 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1302 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1303 | unsigned long address, pmd_t *pmdp, | |
1304 | pmd_t entry, int dirty); | |
1305 | ||
3dfcb315 AK |
1306 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1307 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1308 | unsigned long address, pmd_t *pmdp); | |
3dfcb315 AK |
1309 | |
1310 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
1311 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
1312 | unsigned long addr, pmd_t *pmdp) | |
1313 | { | |
bde3eb62 AK |
1314 | if (radix_enabled()) |
1315 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
1316 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
1317 | } | |
3dfcb315 | 1318 | |
3df33f12 AK |
1319 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1320 | unsigned long address, pmd_t *pmdp) | |
1321 | { | |
bde3eb62 AK |
1322 | if (radix_enabled()) |
1323 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
1324 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
1325 | } | |
3dfcb315 AK |
1326 | #define pmdp_collapse_flush pmdp_collapse_flush |
1327 | ||
75358ea3 AK |
1328 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1329 | pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1330 | unsigned long addr, | |
1331 | pmd_t *pmdp, int full); | |
1332 | ||
3dfcb315 | 1333 | #define __HAVE_ARCH_PGTABLE_DEPOSIT |
3df33f12 AK |
1334 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
1335 | pmd_t *pmdp, pgtable_t pgtable) | |
1336 | { | |
bde3eb62 AK |
1337 | if (radix_enabled()) |
1338 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
1339 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
1340 | } | |
1341 | ||
3dfcb315 | 1342 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
1343 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
1344 | pmd_t *pmdp) | |
1345 | { | |
bde3eb62 AK |
1346 | if (radix_enabled()) |
1347 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
1348 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
1349 | } | |
3dfcb315 AK |
1350 | |
1351 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
8cc931e0 AK |
1352 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, |
1353 | pmd_t *pmdp); | |
3dfcb315 AK |
1354 | |
1355 | #define pmd_move_must_withdraw pmd_move_must_withdraw | |
1356 | struct spinlock; | |
579b9239 AK |
1357 | extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, |
1358 | struct spinlock *old_pmd_ptl, | |
1359 | struct vm_area_struct *vma); | |
1360 | /* | |
1361 | * Hash translation mode use the deposited table to store hash pte | |
1362 | * slot information. | |
1363 | */ | |
953c66c2 AK |
1364 | #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit |
1365 | static inline bool arch_needs_pgtable_deposit(void) | |
1366 | { | |
1367 | if (radix_enabled()) | |
1368 | return false; | |
1369 | return true; | |
1370 | } | |
fa4531f7 | 1371 | extern void serialize_against_pte_lookup(struct mm_struct *mm); |
953c66c2 | 1372 | |
ebd31197 OH |
1373 | |
1374 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) | |
1375 | { | |
36b78402 AK |
1376 | if (radix_enabled()) |
1377 | return radix__pmd_mkdevmap(pmd); | |
1378 | return hash__pmd_mkdevmap(pmd); | |
ebd31197 OH |
1379 | } |
1380 | ||
1381 | static inline int pmd_devmap(pmd_t pmd) | |
1382 | { | |
1383 | return pte_devmap(pmd_pte(pmd)); | |
1384 | } | |
1385 | ||
1386 | static inline int pud_devmap(pud_t pud) | |
1387 | { | |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | static inline int pgd_devmap(pgd_t pgd) | |
1392 | { | |
1393 | return 0; | |
1394 | } | |
6a1ea362 | 1395 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
ebd31197 | 1396 | |
c516886f | 1397 | static inline int pud_pfn(pud_t pud) |
ebd31197 OH |
1398 | { |
1399 | /* | |
1400 | * Currently all calls to pud_pfn() are gated around a pud_devmap() | |
1401 | * check so this should never be used. If it grows another user we | |
1402 | * want to know about it. | |
1403 | */ | |
1404 | BUILD_BUG(); | |
1405 | return 0; | |
1406 | } | |
5b323367 AK |
1407 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1408 | pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); | |
1409 | void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, | |
1410 | pte_t *, pte_t, pte_t); | |
1411 | ||
1412 | /* | |
1413 | * Returns true for a R -> RW upgrade of pte | |
1414 | */ | |
1415 | static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) | |
1416 | { | |
1417 | if (!(old_val & _PAGE_READ)) | |
1418 | return false; | |
1419 | ||
1420 | if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) | |
1421 | return true; | |
1422 | ||
1423 | return false; | |
1424 | } | |
029d9252 | 1425 | |
d6eacedd AK |
1426 | /* |
1427 | * Like pmd_huge() and pmd_large(), but works regardless of config options | |
1428 | */ | |
1429 | #define pmd_is_leaf pmd_is_leaf | |
070434b1 | 1430 | #define pmd_leaf pmd_is_leaf |
d6eacedd AK |
1431 | static inline bool pmd_is_leaf(pmd_t pmd) |
1432 | { | |
1433 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); | |
1434 | } | |
1435 | ||
1436 | #define pud_is_leaf pud_is_leaf | |
070434b1 | 1437 | #define pud_leaf pud_is_leaf |
d6eacedd AK |
1438 | static inline bool pud_is_leaf(pud_t pud) |
1439 | { | |
1440 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); | |
1441 | } | |
1442 | ||
3dfcb315 AK |
1443 | #endif /* __ASSEMBLY__ */ |
1444 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |