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powerpc/mm/radix: Add dummy radix_enabled()
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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3dfcb315
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519
AK		 3
4/*
5 * Common bits between hash and Radix page table
6 */
7#define _PAGE_BIT_SWAP_TYPE 0
8
9#define _PAGE_EXEC 0x00001 /* execute permission */
10#define _PAGE_WRITE 0x00002 /* write access allowed */
11#define _PAGE_READ 0x00004 /* read access allowed */
12#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
13#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
14#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
15#define _PAGE_SAO 0x00010 /* Strong access order */
16#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
17#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
18#define _PAGE_DIRTY 0x00080 /* C: page changed */
19#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
20/*
21 * Software bits
22 */
23#ifdef CONFIG_MEM_SOFT_DIRTY
24#define _PAGE_SOFT_DIRTY 0x00200 /* software: software dirty tracking */
25#else
26#define _PAGE_SOFT_DIRTY 0x00000
27#endif
28#define _PAGE_SPECIAL 0x00400 /* software: special page */
29
30
31#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
32#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
33/*
34 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
35 * Instead of fixing all of them, add an alternate define which
36 * maps CI pte mapping.
37 */
38#define _PAGE_NO_CACHE _PAGE_TOLERANT
39/*
40 * We support 57 bit real address in pte. Clear everything above 57, and
41 * every thing below PAGE_SHIFT;
42 */
43#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
44/*
45 * set of bits not changed in pmd_modify. Even though we have hash specific bits
46 * in here, on radix we expect them to be zero.
47 */
48#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
49 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
50 _PAGE_SOFT_DIRTY)
51/*
52 * user access blocked by key
53 */
54#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
55#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
56#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
57 _PAGE_RW | _PAGE_EXEC)
58/*
59 * No page size encoding in the linux PTE
60 */
61#define _PAGE_PSIZE 0
62/*
63 * _PAGE_CHG_MASK masks of bits that are to be preserved across
64 * pgprot changes
65 */
66#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
67 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
68 _PAGE_SOFT_DIRTY)
69/*
70 * Mask of bits returned by pte_pgprot()
71 */
72#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
73 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
74 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
75 _PAGE_SOFT_DIRTY)
3dfcb315 76/*
2e873519
AK		 77 * We define 2 sets of base prot bits, one for basic pages (ie,
78 * cacheable kernel and user pages) and one for non cacheable
79 * pages. We always set _PAGE_COHERENT when SMP is enabled or
80 * the processor might need it for DMA coherency.
3dfcb315 81 */
2e873519
AK		 82#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
83#define _PAGE_BASE (_PAGE_BASE_NC)
84
85/* Permission masks used to generate the __P and __S table,
86 *
87 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
88 *
89 * Write permissions imply read permissions for now (we could make write-only
90 * pages on BookE but we don't bother for now). Execute permission control is
91 * possible on platforms that define _PAGE_EXEC
92 *
93 * Note due to the way vm flags are laid out, the bits are XWR
94 */
95#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
96#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
97#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
98#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
99#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
100#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
101#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
102
103#define __P000 PAGE_NONE
104#define __P001 PAGE_READONLY
105#define __P010 PAGE_COPY
106#define __P011 PAGE_COPY
107#define __P100 PAGE_READONLY_X
108#define __P101 PAGE_READONLY_X
109#define __P110 PAGE_COPY_X
110#define __P111 PAGE_COPY_X
111
112#define __S000 PAGE_NONE
113#define __S001 PAGE_READONLY
114#define __S010 PAGE_SHARED
115#define __S011 PAGE_SHARED
116#define __S100 PAGE_READONLY_X
117#define __S101 PAGE_READONLY_X
118#define __S110 PAGE_SHARED_X
119#define __S111 PAGE_SHARED_X
120
121/* Permission masks used for kernel mappings */
122#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
123#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
124 _PAGE_TOLERANT)
125#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
126 _PAGE_NON_IDEMPOTENT)
127#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
128#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
129#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
130
131/*
132 * Protection used for kernel text. We want the debuggers to be able to
133 * set breakpoints anywhere, so don't write protect the kernel text
134 * on platforms where such control is possible.
135 */
136#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
137 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
138#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
139#else
140#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
141#endif
142
143/* Make modules code happy. We don't set RO yet */
144#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
145#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 146
dd1842a2
AK		 147#ifndef __ASSEMBLY__
148/*
149 * page table defines
150 */
151extern unsigned long __pte_index_size;
152extern unsigned long __pmd_index_size;
153extern unsigned long __pud_index_size;
154extern unsigned long __pgd_index_size;
155extern unsigned long __pmd_cache_index;
156#define PTE_INDEX_SIZE __pte_index_size
157#define PMD_INDEX_SIZE __pmd_index_size
158#define PUD_INDEX_SIZE __pud_index_size
159#define PGD_INDEX_SIZE __pgd_index_size
160#define PMD_CACHE_INDEX __pmd_cache_index
161/*
162 * Because of use of pte fragments and THP, size of page table
163 * are not always derived out of index size above.
164 */
165extern unsigned long __pte_table_size;
166extern unsigned long __pmd_table_size;
167extern unsigned long __pud_table_size;
168extern unsigned long __pgd_table_size;
169#define PTE_TABLE_SIZE __pte_table_size
170#define PMD_TABLE_SIZE __pmd_table_size
171#define PUD_TABLE_SIZE __pud_table_size
172#define PGD_TABLE_SIZE __pgd_table_size
173/*
174 * Pgtable size used by swapper, init in asm code
175 * We will switch this later to radix PGD
176 */
177#define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
178
179#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
180#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
181#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
182#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
183
184/* PMD_SHIFT determines what a second-level page table entry can map */
185#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
186#define PMD_SIZE (1UL << PMD_SHIFT)
187#define PMD_MASK (~(PMD_SIZE-1))
188
189/* PUD_SHIFT determines what a third-level page table entry can map */
190#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
191#define PUD_SIZE (1UL << PUD_SHIFT)
192#define PUD_MASK (~(PUD_SIZE-1))
193
194/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
195#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
196#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
197#define PGDIR_MASK (~(PGDIR_SIZE-1))
198
199/* Bits to mask out from a PMD to get to the PTE page */
200#define PMD_MASKED_BITS 0xc0000000000000ffUL
201/* Bits to mask out from a PUD to get to the PMD page */
202#define PUD_MASKED_BITS 0xc0000000000000ffUL
203/* Bits to mask out from a PGD to get to the PUD page */
204#define PGD_MASKED_BITS 0xc0000000000000ffUL
205#endif /* __ASSEMBLY__ */
206
ab537dca 207#include <asm/book3s/64/hash.h>
b0b5e9b1 208#include <asm/book3s/64/radix.h>
3dfcb315
AK		 209#include <asm/barrier.h>
210
3dfcb315
AK		 211/*
212 * The second half of the kernel virtual space is used for IO mappings,
213 * it's itself carved into the PIO region (ISA and PHB IO space) and
214 * the ioremap space
215 *
216 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
217 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
218 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
219 */
220#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
221#define FULL_IO_SIZE 0x80000000ul
222#define ISA_IO_BASE (KERN_IO_START)
223#define ISA_IO_END (KERN_IO_START + 0x10000ul)
224#define PHB_IO_BASE (ISA_IO_END)
225#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
226#define IOREMAP_BASE (PHB_IO_END)
227#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
228
3dfcb315
AK		 229#define vmemmap ((struct page *)VMEMMAP_BASE)
230
b0412ea9 231/* Advertise special mapping type for AGP */
b0412ea9
AK		 232#define HAVE_PAGE_AGP
233
234/* Advertise support for _PAGE_SPECIAL */
235#define __HAVE_ARCH_PTE_SPECIAL
236
3dfcb315
AK		 237#ifndef __ASSEMBLY__
238
239/*
240 * This is the default implementation of various PTE accessors, it's
241 * used in all cases except Book3S with 64K pages where we have a
242 * concept of sub-pages
243 */
244#ifndef __real_pte
245
3dfcb315
AK		 246#define __real_pte(e,p) ((real_pte_t){(e)})
247#define __rpte_to_pte(r) ((r).pte)
945537df 248#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 249
250#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
251 do { \
252 index = 0; \
253 shift = mmu_psize_defs[psize].shift; \
254
255#define pte_iterate_hashed_end() } while(0)
256
257/*
258 * We expect this to be called only for user addresses or kernel virtual
259 * addresses other than the linear mapping.
260 */
261#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
262
263#endif /* __real_pte */
264
13f829a5
AK		 265/*
266 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
267 * We currently remove entries from the hashtable regardless of whether
268 * the entry was young or dirty.
269 *
270 * We should be more intelligent about this but for the moment we override
271 * these functions and force a tlb flush unconditionally
272 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
273 * function for both hash and radix.
274 */
275static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
276 unsigned long addr, pte_t *ptep)
277{
278 unsigned long old;
279
280 if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
281 return 0;
282 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
283 return (old & _PAGE_ACCESSED) != 0;
284}
285
286#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
287#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
288({ \
289 int __r; \
290 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
291 __r; \
292})
293
294#define __HAVE_ARCH_PTEP_SET_WRPROTECT
295static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
296 pte_t *ptep)
297{
298
299 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
300 return;
301
302 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
303}
304
305static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
306 unsigned long addr, pte_t *ptep)
307{
308 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
309 return;
310
311 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
312}
313
314#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
315static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
316 unsigned long addr, pte_t *ptep)
317{
318 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
319 return __pte(old);
320}
321
322static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
323 pte_t * ptep)
324{
325 pte_update(mm, addr, ptep, ~0UL, 0, 0);
326}
327static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);}
328static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
329static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
330static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
331static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
332
333#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
334static inline bool pte_soft_dirty(pte_t pte)
335{
336 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
337}
338static inline pte_t pte_mksoft_dirty(pte_t pte)
339{
340 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
341}
342
343static inline pte_t pte_clear_soft_dirty(pte_t pte)
344{
345 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
346}
347#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
348
349#ifdef CONFIG_NUMA_BALANCING
350/*
351 * These work without NUMA balancing but the kernel does not care. See the
352 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
353 * work for user pages and always return true for kernel pages.
354 */
355static inline int pte_protnone(pte_t pte)
356{
357 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
358 (_PAGE_PRESENT | _PAGE_PRIVILEGED);
359}
360#endif /* CONFIG_NUMA_BALANCING */
361
362static inline int pte_present(pte_t pte)
363{
364 return !!(pte_val(pte) & _PAGE_PRESENT);
365}
366/*
367 * Conversion functions: convert a page and protection to a page entry,
368 * and a page entry and page directory to the page they refer to.
369 *
370 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
371 * long for now.
372 */
373static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
374{
375 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
376 pgprot_val(pgprot));
377}
378
379static inline unsigned long pte_pfn(pte_t pte)
380{
381 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
382}
383
384/* Generic modifiers for PTE bits */
385static inline pte_t pte_wrprotect(pte_t pte)
386{
387 return __pte(pte_val(pte) & ~_PAGE_WRITE);
388}
389
390static inline pte_t pte_mkclean(pte_t pte)
391{
392 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
393}
394
395static inline pte_t pte_mkold(pte_t pte)
396{
397 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
398}
399
400static inline pte_t pte_mkwrite(pte_t pte)
401{
402 /*
403 * write implies read, hence set both
404 */
405 return __pte(pte_val(pte) | _PAGE_RW);
406}
407
408static inline pte_t pte_mkdirty(pte_t pte)
409{
410 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
411}
412
413static inline pte_t pte_mkyoung(pte_t pte)
414{
415 return __pte(pte_val(pte) | _PAGE_ACCESSED);
416}
417
418static inline pte_t pte_mkspecial(pte_t pte)
419{
420 return __pte(pte_val(pte) | _PAGE_SPECIAL);
421}
422
423static inline pte_t pte_mkhuge(pte_t pte)
424{
425 return pte;
426}
427
428static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
429{
430 /* FIXME!! check whether this need to be a conditional */
431 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
432}
433
34fbadd8
AK		 434static inline bool pte_user(pte_t pte)
435{
436 return !(pte_val(pte) & _PAGE_PRIVILEGED);
437}
438
439/* Encode and de-code a swap entry */
440#define MAX_SWAPFILES_CHECK() do { \
441 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
442 /* \
443 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
444 * We filter HPTEFLAGS on set_pte. \
445 */ \
446 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
447 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
448 } while (0)
449/*
450 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
451 */
452#define SWP_TYPE_BITS 5
453#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
454 & ((1UL << SWP_TYPE_BITS) - 1))
455#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
456#define __swp_entry(type, offset) ((swp_entry_t) { \
457 ((type) << _PAGE_BIT_SWAP_TYPE) \
458 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
459/*
460 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
461 * swap type and offset we get from swap and convert that to pte to find a
462 * matching pte in linux page table.
463 * Clear bits not found in swap entries here.
464 */
465#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
466#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
467
468#ifdef CONFIG_MEM_SOFT_DIRTY
469#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
470#else
471#define _PAGE_SWP_SOFT_DIRTY 0UL
472#endif /* CONFIG_MEM_SOFT_DIRTY */
473
474#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
475static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
476{
477 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
478}
479static inline bool pte_swp_soft_dirty(pte_t pte)
480{
481 return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
482}
483static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
484{
485 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
486}
487#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
488
489static inline bool check_pte_access(unsigned long access, unsigned long ptev)
490{
491 /*
492 * This check for _PAGE_RWX and _PAGE_PRESENT bits
493 */
494 if (access & ~ptev)
495 return false;
496 /*
497 * This check for access to privilege space
498 */
499 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
500 return false;
501
502 return true;
503}
504
13f829a5
AK		 505#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
506
507#define pgprot_noncached pgprot_noncached
508static inline pgprot_t pgprot_noncached(pgprot_t prot)
509{
510 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
511 _PAGE_NON_IDEMPOTENT);
512}
513
514#define pgprot_noncached_wc pgprot_noncached_wc
515static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
516{
517 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
518 _PAGE_TOLERANT);
519}
520
521#define pgprot_cached pgprot_cached
522static inline pgprot_t pgprot_cached(pgprot_t prot)
523{
524 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
525}
526
527#define pgprot_writecombine pgprot_writecombine
528static inline pgprot_t pgprot_writecombine(pgprot_t prot)
529{
530 return pgprot_noncached_wc(prot);
531}
532/*
533 * check a pte mapping have cache inhibited property
534 */
535static inline bool pte_ci(pte_t pte)
536{
537 unsigned long pte_v = pte_val(pte);
538
539 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
540 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
541 return true;
542 return false;
543}
544
f281b5d5
AK		 545static inline void pmd_set(pmd_t *pmdp, unsigned long val)
546{
547 *pmdp = __pmd(val);
548}
549
550static inline void pmd_clear(pmd_t *pmdp)
551{
552 *pmdp = __pmd(0);
553}
554
3dfcb315 555#define pmd_none(pmd) (!pmd_val(pmd))
3dfcb315 556#define pmd_present(pmd) (!pmd_none(pmd))
3dfcb315 557
f281b5d5
AK		 558static inline void pud_set(pud_t *pudp, unsigned long val)
559{
560 *pudp = __pud(val);
561}
562
563static inline void pud_clear(pud_t *pudp)
564{
565 *pudp = __pud(0);
566}
567
3dfcb315 568#define pud_none(pud) (!pud_val(pud))
3dfcb315 569#define pud_present(pud) (pud_val(pud) != 0)
3dfcb315
AK		 570
571extern struct page *pud_page(pud_t pud);
371352ca 572extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 573static inline pte_t pud_pte(pud_t pud)
574{
575 return __pte(pud_val(pud));
576}
577
578static inline pud_t pte_pud(pte_t pte)
579{
580 return __pud(pte_val(pte));
581}
582#define pud_write(pud) pte_write(pud_pte(pud))
3dfcb315 583#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 584static inline void pgd_set(pgd_t *pgdp, unsigned long val)
585{
586 *pgdp = __pgd(val);
587}
3dfcb315 588
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AK		 589static inline void pgd_clear(pgd_t *pgdp)
590{
591 *pgdp = __pgd(0);
592}
593
594#define pgd_none(pgd) (!pgd_val(pgd))
595#define pgd_present(pgd) (!pgd_none(pgd))
596
597static inline pte_t pgd_pte(pgd_t pgd)
598{
599 return __pte(pgd_val(pgd));
600}
601
602static inline pgd_t pte_pgd(pte_t pte)
603{
604 return __pgd(pte_val(pte));
605}
606
607extern struct page *pgd_page(pgd_t pgd);
608
aba480e1
AK		 609/* Pointers in the page table tree are physical addresses */
610#define __pgtable_ptr_val(ptr) __pa(ptr)
611
612#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
613#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
614#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
615
616#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
617#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
618#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
619#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
620
3dfcb315
AK		 621/*
622 * Find an entry in a page-table-directory. We combine the address region
623 * (the high order N bits) and the pgd portion of the address.
624 */
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AK		 625
626#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
627
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AK		 628#define pud_offset(pgdp, addr) \
629 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 630#define pmd_offset(pudp,addr) \
371352ca 631 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 632#define pte_offset_kernel(dir,addr) \
371352ca 633 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 634
635#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
636#define pte_unmap(pte) do { } while(0)
637
638/* to find an entry in a kernel page-table-directory */
639/* This now only contains the vmalloc pages */
640#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 641
642#define pte_ERROR(e) \
643 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
644#define pmd_ERROR(e) \
645 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 646#define pud_ERROR(e) \
647 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 648#define pgd_ERROR(e) \
649 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
650
3dfcb315
AK		 651void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
652void pgtable_cache_init(void);
3dfcb315 653
3dfcb315
AK		 654struct page *realmode_pfn_to_page(unsigned long pfn);
655
3dfcb315 656#ifdef CONFIG_TRANSPARENT_HUGEPAGE
3dfcb315
AK		 657extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
658extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
659extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
660extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
661 pmd_t *pmdp, pmd_t pmd);
662extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
663 pmd_t *pmd);
3dfcb315 664extern int has_transparent_hugepage(void);
3dfcb315
AK		 665#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
666
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AK		 667
668static inline pte_t pmd_pte(pmd_t pmd)
669{
670 return __pte(pmd_val(pmd));
671}
672
673static inline pmd_t pte_pmd(pte_t pte)
674{
675 return __pmd(pte_val(pte));
676}
677
678static inline pte_t *pmdp_ptep(pmd_t *pmd)
679{
680 return (pte_t *)pmd;
681}
682
683#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
684#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
685#define pmd_young(pmd) pte_young(pmd_pte(pmd))
686#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
687#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
688#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 689#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 690#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
691#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
7207f436
LD		 692
693#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
694#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
695#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
696#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
697#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
698
1ca72129
AK		 699#ifdef CONFIG_NUMA_BALANCING
700static inline int pmd_protnone(pmd_t pmd)
701{
702 return pte_protnone(pmd_pte(pmd));
703}
704#endif /* CONFIG_NUMA_BALANCING */
3dfcb315
AK		 705
706#define __HAVE_ARCH_PMD_WRITE
707#define pmd_write(pmd) pte_write(pmd_pte(pmd))
708
709static inline pmd_t pmd_mkhuge(pmd_t pmd)
710{
945537df 711 return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE));
3dfcb315
AK		 712}
713
3dfcb315
AK		 714#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
715extern int pmdp_set_access_flags(struct vm_area_struct *vma,
716 unsigned long address, pmd_t *pmdp,
717 pmd_t entry, int dirty);
718
3dfcb315
AK		 719#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
720extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
721 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 722
723#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
724extern pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
725 unsigned long addr, pmd_t *pmdp);
726
3dfcb315
AK		 727extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
728 unsigned long address, pmd_t *pmdp);
729#define pmdp_collapse_flush pmdp_collapse_flush
730
731#define __HAVE_ARCH_PGTABLE_DEPOSIT
732extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
733 pgtable_t pgtable);
734#define __HAVE_ARCH_PGTABLE_WITHDRAW
735extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
736
737#define __HAVE_ARCH_PMDP_INVALIDATE
738extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
739 pmd_t *pmdp);
740
c777e2a8
AK		 741#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
742extern void pmdp_huge_split_prepare(struct vm_area_struct *vma,
743 unsigned long address, pmd_t *pmdp);
744
3dfcb315
AK		 745#define pmd_move_must_withdraw pmd_move_must_withdraw
746struct spinlock;
747static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
748 struct spinlock *old_pmd_ptl)
749{
750 /*
751 * Archs like ppc64 use pgtable to store per pmd
752 * specific information. So when we switch the pmd,
753 * we should also withdraw and deposit the pgtable
754 */
755 return true;
756}
757#endif /* __ASSEMBLY__ */
758#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)