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powerpc/mm: Update pte filter for radix
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
CommitLineData
3dfcb315
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519
AK		 3
4/*
5 * Common bits between hash and Radix page table
6 */
7#define _PAGE_BIT_SWAP_TYPE 0
8
9#define _PAGE_EXEC 0x00001 /* execute permission */
10#define _PAGE_WRITE 0x00002 /* write access allowed */
11#define _PAGE_READ 0x00004 /* read access allowed */
12#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
13#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
14#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
15#define _PAGE_SAO 0x00010 /* Strong access order */
16#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
17#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
18#define _PAGE_DIRTY 0x00080 /* C: page changed */
19#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
20/*
21 * Software bits
22 */
23#ifdef CONFIG_MEM_SOFT_DIRTY
24#define _PAGE_SOFT_DIRTY 0x00200 /* software: software dirty tracking */
25#else
26#define _PAGE_SOFT_DIRTY 0x00000
27#endif
28#define _PAGE_SPECIAL 0x00400 /* software: special page */
29
30
31#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
32#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
33/*
34 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
35 * Instead of fixing all of them, add an alternate define which
36 * maps CI pte mapping.
37 */
38#define _PAGE_NO_CACHE _PAGE_TOLERANT
39/*
40 * We support 57 bit real address in pte. Clear everything above 57, and
41 * every thing below PAGE_SHIFT;
42 */
43#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
44/*
45 * set of bits not changed in pmd_modify. Even though we have hash specific bits
46 * in here, on radix we expect them to be zero.
47 */
48#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
49 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
50 _PAGE_SOFT_DIRTY)
51/*
52 * user access blocked by key
53 */
54#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
55#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
56#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
57 _PAGE_RW | _PAGE_EXEC)
58/*
59 * No page size encoding in the linux PTE
60 */
61#define _PAGE_PSIZE 0
62/*
63 * _PAGE_CHG_MASK masks of bits that are to be preserved across
64 * pgprot changes
65 */
66#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
67 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
68 _PAGE_SOFT_DIRTY)
69/*
70 * Mask of bits returned by pte_pgprot()
71 */
72#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
73 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
74 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
75 _PAGE_SOFT_DIRTY)
3dfcb315 76/*
2e873519
AK		 77 * We define 2 sets of base prot bits, one for basic pages (ie,
78 * cacheable kernel and user pages) and one for non cacheable
79 * pages. We always set _PAGE_COHERENT when SMP is enabled or
80 * the processor might need it for DMA coherency.
3dfcb315 81 */
2e873519
AK		 82#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
83#define _PAGE_BASE (_PAGE_BASE_NC)
84
85/* Permission masks used to generate the __P and __S table,
86 *
87 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
88 *
89 * Write permissions imply read permissions for now (we could make write-only
90 * pages on BookE but we don't bother for now). Execute permission control is
91 * possible on platforms that define _PAGE_EXEC
92 *
93 * Note due to the way vm flags are laid out, the bits are XWR
94 */
95#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
96#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
97#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
98#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
99#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
100#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
101#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
102
103#define __P000 PAGE_NONE
104#define __P001 PAGE_READONLY
105#define __P010 PAGE_COPY
106#define __P011 PAGE_COPY
107#define __P100 PAGE_READONLY_X
108#define __P101 PAGE_READONLY_X
109#define __P110 PAGE_COPY_X
110#define __P111 PAGE_COPY_X
111
112#define __S000 PAGE_NONE
113#define __S001 PAGE_READONLY
114#define __S010 PAGE_SHARED
115#define __S011 PAGE_SHARED
116#define __S100 PAGE_READONLY_X
117#define __S101 PAGE_READONLY_X
118#define __S110 PAGE_SHARED_X
119#define __S111 PAGE_SHARED_X
120
121/* Permission masks used for kernel mappings */
122#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
123#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
124 _PAGE_TOLERANT)
125#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
126 _PAGE_NON_IDEMPOTENT)
127#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
128#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
129#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
130
131/*
132 * Protection used for kernel text. We want the debuggers to be able to
133 * set breakpoints anywhere, so don't write protect the kernel text
134 * on platforms where such control is possible.
135 */
136#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
137 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
138#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
139#else
140#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
141#endif
142
143/* Make modules code happy. We don't set RO yet */
144#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
145#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 146
dd1842a2
AK		 147#ifndef __ASSEMBLY__
148/*
149 * page table defines
150 */
151extern unsigned long __pte_index_size;
152extern unsigned long __pmd_index_size;
153extern unsigned long __pud_index_size;
154extern unsigned long __pgd_index_size;
155extern unsigned long __pmd_cache_index;
156#define PTE_INDEX_SIZE __pte_index_size
157#define PMD_INDEX_SIZE __pmd_index_size
158#define PUD_INDEX_SIZE __pud_index_size
159#define PGD_INDEX_SIZE __pgd_index_size
160#define PMD_CACHE_INDEX __pmd_cache_index
161/*
162 * Because of use of pte fragments and THP, size of page table
163 * are not always derived out of index size above.
164 */
165extern unsigned long __pte_table_size;
166extern unsigned long __pmd_table_size;
167extern unsigned long __pud_table_size;
168extern unsigned long __pgd_table_size;
169#define PTE_TABLE_SIZE __pte_table_size
170#define PMD_TABLE_SIZE __pmd_table_size
171#define PUD_TABLE_SIZE __pud_table_size
172#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 173
174extern unsigned long __pmd_val_bits;
175extern unsigned long __pud_val_bits;
176extern unsigned long __pgd_val_bits;
177#define PMD_VAL_BITS __pmd_val_bits
178#define PUD_VAL_BITS __pud_val_bits
179#define PGD_VAL_BITS __pgd_val_bits
dd1842a2
AK		 180/*
181 * Pgtable size used by swapper, init in asm code
dd1842a2 182 */
a2f41eb9 183#define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
dd1842a2
AK		 184
185#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
186#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
187#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
188#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
189
190/* PMD_SHIFT determines what a second-level page table entry can map */
191#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
192#define PMD_SIZE (1UL << PMD_SHIFT)
193#define PMD_MASK (~(PMD_SIZE-1))
194
195/* PUD_SHIFT determines what a third-level page table entry can map */
196#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
197#define PUD_SIZE (1UL << PUD_SHIFT)
198#define PUD_MASK (~(PUD_SIZE-1))
199
200/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
201#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
202#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
203#define PGDIR_MASK (~(PGDIR_SIZE-1))
204
205/* Bits to mask out from a PMD to get to the PTE page */
206#define PMD_MASKED_BITS 0xc0000000000000ffUL
207/* Bits to mask out from a PUD to get to the PMD page */
208#define PUD_MASKED_BITS 0xc0000000000000ffUL
209/* Bits to mask out from a PGD to get to the PUD page */
210#define PGD_MASKED_BITS 0xc0000000000000ffUL
211#endif /* __ASSEMBLY__ */
212
ab537dca 213#include <asm/book3s/64/hash.h>
b0b5e9b1 214#include <asm/book3s/64/radix.h>
a9252aae
AK		 215
216#ifdef CONFIG_PPC_64K_PAGES
217#include <asm/book3s/64/pgtable-64k.h>
218#else
219#include <asm/book3s/64/pgtable-4k.h>
220#endif
221
3dfcb315
AK		 222#include <asm/barrier.h>
223
3dfcb315
AK		 224/*
225 * The second half of the kernel virtual space is used for IO mappings,
226 * it's itself carved into the PIO region (ISA and PHB IO space) and
227 * the ioremap space
228 *
229 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
230 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
231 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
232 */
233#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
234#define FULL_IO_SIZE 0x80000000ul
235#define ISA_IO_BASE (KERN_IO_START)
236#define ISA_IO_END (KERN_IO_START + 0x10000ul)
237#define PHB_IO_BASE (ISA_IO_END)
238#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
239#define IOREMAP_BASE (PHB_IO_END)
240#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
241
3dfcb315
AK		 242#define vmemmap ((struct page *)VMEMMAP_BASE)
243
b0412ea9 244/* Advertise special mapping type for AGP */
b0412ea9
AK		 245#define HAVE_PAGE_AGP
246
247/* Advertise support for _PAGE_SPECIAL */
248#define __HAVE_ARCH_PTE_SPECIAL
249
3dfcb315
AK		 250#ifndef __ASSEMBLY__
251
252/*
253 * This is the default implementation of various PTE accessors, it's
254 * used in all cases except Book3S with 64K pages where we have a
255 * concept of sub-pages
256 */
257#ifndef __real_pte
258
3dfcb315
AK		 259#define __real_pte(e,p) ((real_pte_t){(e)})
260#define __rpte_to_pte(r) ((r).pte)
945537df 261#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 262
263#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
264 do { \
265 index = 0; \
266 shift = mmu_psize_defs[psize].shift; \
267
268#define pte_iterate_hashed_end() } while(0)
269
270/*
271 * We expect this to be called only for user addresses or kernel virtual
272 * addresses other than the linear mapping.
273 */
274#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
275
276#endif /* __real_pte */
277
ac94ac79
AK		 278static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
279 pte_t *ptep, unsigned long clr,
280 unsigned long set, int huge)
281{
282 if (radix_enabled())
283 return radix__pte_update(mm, addr, ptep, clr, set, huge);
284 return hash__pte_update(mm, addr, ptep, clr, set, huge);
285}
13f829a5
AK		 286/*
287 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
288 * We currently remove entries from the hashtable regardless of whether
289 * the entry was young or dirty.
290 *
291 * We should be more intelligent about this but for the moment we override
292 * these functions and force a tlb flush unconditionally
293 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
294 * function for both hash and radix.
295 */
296static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
297 unsigned long addr, pte_t *ptep)
298{
299 unsigned long old;
300
301 if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
302 return 0;
303 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
304 return (old & _PAGE_ACCESSED) != 0;
305}
306
307#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
308#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
309({ \
310 int __r; \
311 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
312 __r; \
313})
314
315#define __HAVE_ARCH_PTEP_SET_WRPROTECT
316static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
317 pte_t *ptep)
318{
319
320 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
321 return;
322
323 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
324}
325
326static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
327 unsigned long addr, pte_t *ptep)
328{
329 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
330 return;
331
332 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
333}
334
335#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
336static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
337 unsigned long addr, pte_t *ptep)
338{
339 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
340 return __pte(old);
341}
342
343static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
344 pte_t * ptep)
345{
346 pte_update(mm, addr, ptep, ~0UL, 0, 0);
347}
348static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);}
349static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
350static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
351static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
352static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
353
354#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
355static inline bool pte_soft_dirty(pte_t pte)
356{
357 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
358}
359static inline pte_t pte_mksoft_dirty(pte_t pte)
360{
361 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
362}
363
364static inline pte_t pte_clear_soft_dirty(pte_t pte)
365{
366 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
367}
368#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
369
370#ifdef CONFIG_NUMA_BALANCING
371/*
372 * These work without NUMA balancing but the kernel does not care. See the
373 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
374 * work for user pages and always return true for kernel pages.
375 */
376static inline int pte_protnone(pte_t pte)
377{
378 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
379 (_PAGE_PRESENT | _PAGE_PRIVILEGED);
380}
381#endif /* CONFIG_NUMA_BALANCING */
382
383static inline int pte_present(pte_t pte)
384{
385 return !!(pte_val(pte) & _PAGE_PRESENT);
386}
387/*
388 * Conversion functions: convert a page and protection to a page entry,
389 * and a page entry and page directory to the page they refer to.
390 *
391 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
392 * long for now.
393 */
394static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
395{
396 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
397 pgprot_val(pgprot));
398}
399
400static inline unsigned long pte_pfn(pte_t pte)
401{
402 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
403}
404
405/* Generic modifiers for PTE bits */
406static inline pte_t pte_wrprotect(pte_t pte)
407{
408 return __pte(pte_val(pte) & ~_PAGE_WRITE);
409}
410
411static inline pte_t pte_mkclean(pte_t pte)
412{
413 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
414}
415
416static inline pte_t pte_mkold(pte_t pte)
417{
418 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
419}
420
421static inline pte_t pte_mkwrite(pte_t pte)
422{
423 /*
424 * write implies read, hence set both
425 */
426 return __pte(pte_val(pte) | _PAGE_RW);
427}
428
429static inline pte_t pte_mkdirty(pte_t pte)
430{
431 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
432}
433
434static inline pte_t pte_mkyoung(pte_t pte)
435{
436 return __pte(pte_val(pte) | _PAGE_ACCESSED);
437}
438
439static inline pte_t pte_mkspecial(pte_t pte)
440{
441 return __pte(pte_val(pte) | _PAGE_SPECIAL);
442}
443
444static inline pte_t pte_mkhuge(pte_t pte)
445{
446 return pte;
447}
448
449static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
450{
451 /* FIXME!! check whether this need to be a conditional */
452 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
453}
454
34fbadd8
AK		 455static inline bool pte_user(pte_t pte)
456{
457 return !(pte_val(pte) & _PAGE_PRIVILEGED);
458}
459
460/* Encode and de-code a swap entry */
461#define MAX_SWAPFILES_CHECK() do { \
462 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
463 /* \
464 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
465 * We filter HPTEFLAGS on set_pte. \
466 */ \
467 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
468 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
469 } while (0)
470/*
471 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
472 */
473#define SWP_TYPE_BITS 5
474#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
475 & ((1UL << SWP_TYPE_BITS) - 1))
476#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
477#define __swp_entry(type, offset) ((swp_entry_t) { \
478 ((type) << _PAGE_BIT_SWAP_TYPE) \
479 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
480/*
481 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
482 * swap type and offset we get from swap and convert that to pte to find a
483 * matching pte in linux page table.
484 * Clear bits not found in swap entries here.
485 */
486#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
487#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
488
489#ifdef CONFIG_MEM_SOFT_DIRTY
490#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
491#else
492#define _PAGE_SWP_SOFT_DIRTY 0UL
493#endif /* CONFIG_MEM_SOFT_DIRTY */
494
495#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
496static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
497{
498 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
499}
500static inline bool pte_swp_soft_dirty(pte_t pte)
501{
502 return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
503}
504static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
505{
506 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
507}
508#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
509
510static inline bool check_pte_access(unsigned long access, unsigned long ptev)
511{
512 /*
513 * This check for _PAGE_RWX and _PAGE_PRESENT bits
514 */
515 if (access & ~ptev)
516 return false;
517 /*
518 * This check for access to privilege space
519 */
520 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
521 return false;
522
523 return true;
524}
ac94ac79
AK		 525/*
526 * Generic functions with hash/radix callbacks
527 */
528
529static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
530{
531 if (radix_enabled())
532 return radix__ptep_set_access_flags(ptep, entry);
533 return hash__ptep_set_access_flags(ptep, entry);
534}
535
536#define __HAVE_ARCH_PTE_SAME
537static inline int pte_same(pte_t pte_a, pte_t pte_b)
538{
539 if (radix_enabled())
540 return radix__pte_same(pte_a, pte_b);
541 return hash__pte_same(pte_a, pte_b);
542}
543
544static inline int pte_none(pte_t pte)
545{
546 if (radix_enabled())
547 return radix__pte_none(pte);
548 return hash__pte_none(pte);
549}
550
551static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
552 pte_t *ptep, pte_t pte, int percpu)
553{
554 if (radix_enabled())
555 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
556 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
557}
34fbadd8 558
13f829a5
AK		 559#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
560
561#define pgprot_noncached pgprot_noncached
562static inline pgprot_t pgprot_noncached(pgprot_t prot)
563{
564 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
565 _PAGE_NON_IDEMPOTENT);
566}
567
568#define pgprot_noncached_wc pgprot_noncached_wc
569static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
570{
571 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
572 _PAGE_TOLERANT);
573}
574
575#define pgprot_cached pgprot_cached
576static inline pgprot_t pgprot_cached(pgprot_t prot)
577{
578 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
579}
580
581#define pgprot_writecombine pgprot_writecombine
582static inline pgprot_t pgprot_writecombine(pgprot_t prot)
583{
584 return pgprot_noncached_wc(prot);
585}
586/*
587 * check a pte mapping have cache inhibited property
588 */
589static inline bool pte_ci(pte_t pte)
590{
591 unsigned long pte_v = pte_val(pte);
592
593 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
594 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
595 return true;
596 return false;
597}
598
f281b5d5
AK		 599static inline void pmd_set(pmd_t *pmdp, unsigned long val)
600{
601 *pmdp = __pmd(val);
602}
603
604static inline void pmd_clear(pmd_t *pmdp)
605{
606 *pmdp = __pmd(0);
607}
608
3dfcb315 609#define pmd_none(pmd) (!pmd_val(pmd))
3dfcb315 610#define pmd_present(pmd) (!pmd_none(pmd))
3dfcb315 611
ac94ac79
AK		 612static inline int pmd_bad(pmd_t pmd)
613{
614 if (radix_enabled())
615 return radix__pmd_bad(pmd);
616 return hash__pmd_bad(pmd);
617}
618
f281b5d5
AK		 619static inline void pud_set(pud_t *pudp, unsigned long val)
620{
621 *pudp = __pud(val);
622}
623
624static inline void pud_clear(pud_t *pudp)
625{
626 *pudp = __pud(0);
627}
628
3dfcb315 629#define pud_none(pud) (!pud_val(pud))
3dfcb315 630#define pud_present(pud) (pud_val(pud) != 0)
3dfcb315
AK		 631
632extern struct page *pud_page(pud_t pud);
371352ca 633extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 634static inline pte_t pud_pte(pud_t pud)
635{
636 return __pte(pud_val(pud));
637}
638
639static inline pud_t pte_pud(pte_t pte)
640{
641 return __pud(pte_val(pte));
642}
643#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 644
645static inline int pud_bad(pud_t pud)
646{
647 if (radix_enabled())
648 return radix__pud_bad(pud);
649 return hash__pud_bad(pud);
650}
651
652
3dfcb315 653#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 654static inline void pgd_set(pgd_t *pgdp, unsigned long val)
655{
656 *pgdp = __pgd(val);
657}
3dfcb315 658
368ced78
AK		 659static inline void pgd_clear(pgd_t *pgdp)
660{
661 *pgdp = __pgd(0);
662}
663
664#define pgd_none(pgd) (!pgd_val(pgd))
665#define pgd_present(pgd) (!pgd_none(pgd))
666
667static inline pte_t pgd_pte(pgd_t pgd)
668{
669 return __pte(pgd_val(pgd));
670}
671
672static inline pgd_t pte_pgd(pte_t pte)
673{
674 return __pgd(pte_val(pte));
675}
676
ac94ac79
AK		 677static inline int pgd_bad(pgd_t pgd)
678{
679 if (radix_enabled())
680 return radix__pgd_bad(pgd);
681 return hash__pgd_bad(pgd);
682}
683
368ced78
AK		 684extern struct page *pgd_page(pgd_t pgd);
685
aba480e1
AK		 686/* Pointers in the page table tree are physical addresses */
687#define __pgtable_ptr_val(ptr) __pa(ptr)
688
689#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
690#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
691#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
692
693#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
694#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
695#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
696#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
697
3dfcb315
AK		 698/*
699 * Find an entry in a page-table-directory. We combine the address region
700 * (the high order N bits) and the pgd portion of the address.
701 */
3dfcb315
AK		 702
703#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
704
368ced78
AK		 705#define pud_offset(pgdp, addr) \
706 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 707#define pmd_offset(pudp,addr) \
371352ca 708 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 709#define pte_offset_kernel(dir,addr) \
371352ca 710 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 711
712#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
713#define pte_unmap(pte) do { } while(0)
714
715/* to find an entry in a kernel page-table-directory */
716/* This now only contains the vmalloc pages */
717#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 718
719#define pte_ERROR(e) \
720 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
721#define pmd_ERROR(e) \
722 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 723#define pud_ERROR(e) \
724 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 725#define pgd_ERROR(e) \
726 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
727
3dfcb315
AK		 728void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
729void pgtable_cache_init(void);
3dfcb315 730
31a14fae
AK		 731static inline int map_kernel_page(unsigned long ea, unsigned long pa,
732 unsigned long flags)
733{
d9225ad9
AK		 734 if (radix_enabled()) {
735#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
736 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
737 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
738#endif
739 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
740 }
31a14fae
AK		 741 return hash__map_kernel_page(ea, pa, flags);
742}
743
744static inline int __meminit vmemmap_create_mapping(unsigned long start,
745 unsigned long page_size,
746 unsigned long phys)
747{
d9225ad9
AK		 748 if (radix_enabled())
749 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae
AK		 750 return hash__vmemmap_create_mapping(start, page_size, phys);
751}
752
753#ifdef CONFIG_MEMORY_HOTPLUG
754static inline void vmemmap_remove_mapping(unsigned long start,
755 unsigned long page_size)
756{
d9225ad9
AK		 757
758 if (radix_enabled())
759 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae
AK		 760 return hash__vmemmap_remove_mapping(start, page_size);
761}
762#endif
3dfcb315
AK		 763struct page *realmode_pfn_to_page(unsigned long pfn);
764
3dfcb315 765#ifdef CONFIG_TRANSPARENT_HUGEPAGE
3dfcb315
AK		 766extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
767extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
768extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
769extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
770 pmd_t *pmdp, pmd_t pmd);
771extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
772 pmd_t *pmd);
3dfcb315 773extern int has_transparent_hugepage(void);
3dfcb315
AK		 774#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
775
3dfcb315
AK		 776
777static inline pte_t pmd_pte(pmd_t pmd)
778{
779 return __pte(pmd_val(pmd));
780}
781
782static inline pmd_t pte_pmd(pte_t pte)
783{
784 return __pmd(pte_val(pte));
785}
786
787static inline pte_t *pmdp_ptep(pmd_t *pmd)
788{
789 return (pte_t *)pmd;
790}
791
792#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
793#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
794#define pmd_young(pmd) pte_young(pmd_pte(pmd))
795#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
796#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
797#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 798#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 799#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
800#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
7207f436
LD		 801
802#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
803#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
804#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
805#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
806#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
807
1ca72129
AK		 808#ifdef CONFIG_NUMA_BALANCING
809static inline int pmd_protnone(pmd_t pmd)
810{
811 return pte_protnone(pmd_pte(pmd));
812}
813#endif /* CONFIG_NUMA_BALANCING */
3dfcb315
AK		 814
815#define __HAVE_ARCH_PMD_WRITE
816#define pmd_write(pmd) pte_write(pmd_pte(pmd))
817
818static inline pmd_t pmd_mkhuge(pmd_t pmd)
819{
945537df 820 return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE));
3dfcb315
AK		 821}
822
3dfcb315
AK		 823#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
824extern int pmdp_set_access_flags(struct vm_area_struct *vma,
825 unsigned long address, pmd_t *pmdp,
826 pmd_t entry, int dirty);
827
3dfcb315
AK		 828#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
829extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
830 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 831
832#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
833extern pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
834 unsigned long addr, pmd_t *pmdp);
835
3dfcb315
AK		 836extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
837 unsigned long address, pmd_t *pmdp);
838#define pmdp_collapse_flush pmdp_collapse_flush
839
840#define __HAVE_ARCH_PGTABLE_DEPOSIT
841extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
842 pgtable_t pgtable);
843#define __HAVE_ARCH_PGTABLE_WITHDRAW
844extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
845
846#define __HAVE_ARCH_PMDP_INVALIDATE
847extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
848 pmd_t *pmdp);
849
c777e2a8
AK		 850#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
851extern void pmdp_huge_split_prepare(struct vm_area_struct *vma,
852 unsigned long address, pmd_t *pmdp);
853
3dfcb315
AK		 854#define pmd_move_must_withdraw pmd_move_must_withdraw
855struct spinlock;
856static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
857 struct spinlock *old_pmd_ptl)
858{
859 /*
860 * Archs like ppc64 use pgtable to store per pmd
861 * specific information. So when we switch the pmd,
862 * we should also withdraw and deposit the pgtable
863 */
864 return true;
865}
866#endif /* __ASSEMBLY__ */
867#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)