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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3dfcb315 AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 | 4 | |
2fb47060 | 5 | #include <asm-generic/pgtable-nop4d.h> |
9849a569 | 6 | |
c137a275 AK |
7 | #ifndef __ASSEMBLY__ |
8 | #include <linux/mmdebug.h> | |
ebd31197 | 9 | #include <linux/bug.h> |
9ccba66d | 10 | #include <linux/sizes.h> |
c137a275 | 11 | #endif |
9849a569 | 12 | |
2e873519 AK |
13 | /* |
14 | * Common bits between hash and Radix page table | |
15 | */ | |
2e873519 AK |
16 | |
17 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
18 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
19 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
2e873519 | 20 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ |
12564485 | 21 | #define _PAGE_SAO 0x00010 /* Strong access order */ |
2e873519 AK |
22 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ |
23 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
24 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
25 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 26 | /* |
2e873519 | 27 | * Software bits |
3dfcb315 | 28 | */ |
69dfbaeb AK |
29 | #define _RPAGE_SW0 0x2000000000000000UL |
30 | #define _RPAGE_SW1 0x00800 | |
31 | #define _RPAGE_SW2 0x00400 | |
32 | #define _RPAGE_SW3 0x00200 | |
ee8b3933 AK |
33 | #define _RPAGE_RSV1 0x00040UL |
34 | ||
35 | #define _RPAGE_PKEY_BIT4 0x1000000000000000UL | |
36 | #define _RPAGE_PKEY_BIT3 0x0800000000000000UL | |
37 | #define _RPAGE_PKEY_BIT2 0x0400000000000000UL | |
38 | #define _RPAGE_PKEY_BIT1 0x0200000000000000UL | |
39 | #define _RPAGE_PKEY_BIT0 0x0100000000000000UL | |
6aa59f51 AK |
40 | |
41 | #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ | |
42 | #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ | |
bd0dbb73 AK |
43 | /* |
44 | * We need to mark a pmd pte invalid while splitting. We can do that by clearing | |
45 | * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to | |
46 | * differentiate between two use a SW field when invalidating. | |
47 | * | |
48 | * We do that temporary invalidate for regular pte entry in ptep_set_access_flags | |
49 | * | |
50 | * This is used only when _PAGE_PRESENT is cleared. | |
51 | */ | |
52 | #define _PAGE_INVALID _RPAGE_SW0 | |
6aa59f51 AK |
53 | |
54 | /* | |
55 | * Top and bottom bits of RPN which can be used by hash | |
56 | * translation mode, because we expect them to be zero | |
57 | * otherwise. | |
58 | */ | |
32789d38 AK |
59 | #define _RPAGE_RPN0 0x01000 |
60 | #define _RPAGE_RPN1 0x02000 | |
6aa59f51 AK |
61 | #define _RPAGE_RPN43 0x0080000000000000UL |
62 | #define _RPAGE_RPN42 0x0040000000000000UL | |
63 | #define _RPAGE_RPN41 0x0020000000000000UL | |
049d567a | 64 | |
2f18d533 | 65 | /* Max physical address bit as per radix table */ |
ee8b3933 | 66 | #define _RPAGE_PA_MAX 56 |
2f18d533 AK |
67 | |
68 | /* | |
69 | * Max physical address bit we will use for now. | |
70 | * | |
71 | * This is mostly a hardware limitation and for now Power9 has | |
72 | * a 51 bit limit. | |
73 | * | |
74 | * This is different from the number of physical bit required to address | |
75 | * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. | |
76 | * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum | |
77 | * number of sections we can support (SECTIONS_SHIFT). | |
78 | * | |
79 | * This is different from Radix page table limitation above and | |
80 | * should always be less than that. The limit is done such that | |
81 | * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX | |
82 | * for hash linux page table specific bits. | |
83 | * | |
84 | * In order to be compatible with future hardware generations we keep | |
85 | * some offsets and limit this for now to 53 | |
86 | */ | |
87 | #define _PAGE_PA_MAX 53 | |
88 | ||
69dfbaeb | 89 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
69dfbaeb | 90 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
ebd31197 | 91 | #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ |
ebd31197 | 92 | |
2e873519 AK |
93 | /* |
94 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
95 | * Instead of fixing all of them, add an alternate define which | |
96 | * maps CI pte mapping. | |
97 | */ | |
98 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
99 | /* | |
2f18d533 AK |
100 | * We support _RPAGE_PA_MAX bit real address in pte. On the linux side |
101 | * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX | |
102 | * and every thing below PAGE_SHIFT; | |
2e873519 | 103 | */ |
2f18d533 | 104 | #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) |
9fee28ba | 105 | #define PTE_RPN_SHIFT PAGE_SHIFT |
2e873519 AK |
106 | /* |
107 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
108 | * in here, on radix we expect them to be zero. | |
109 | */ | |
110 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
111 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
4628a645 | 112 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
113 | /* |
114 | * user access blocked by key | |
115 | */ | |
116 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
117 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
56bec2f9 | 118 | #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) |
6cc07821 | 119 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) |
2e873519 AK |
120 | /* |
121 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
122 | * pgprot changes | |
123 | */ | |
124 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
125 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
4628a645 | 126 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
eb95d016 | 127 | |
3dfcb315 | 128 | /* |
2e873519 AK |
129 | * We define 2 sets of base prot bits, one for basic pages (ie, |
130 | * cacheable kernel and user pages) and one for non cacheable | |
131 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
132 | * the processor might need it for DMA coherency. | |
3dfcb315 | 133 | */ |
093d7ca2 | 134 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
2e873519 AK |
135 | #define _PAGE_BASE (_PAGE_BASE_NC) |
136 | ||
58f53462 CL |
137 | #include <asm/pgtable-masks.h> |
138 | ||
2e873519 AK |
139 | /* Permission masks used for kernel mappings */ |
140 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
6cc07821 CL |
141 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) |
142 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) | |
2e873519 AK |
143 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) |
144 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
145 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
146 | ||
dd1842a2 AK |
147 | #ifndef __ASSEMBLY__ |
148 | /* | |
149 | * page table defines | |
150 | */ | |
151 | extern unsigned long __pte_index_size; | |
152 | extern unsigned long __pmd_index_size; | |
153 | extern unsigned long __pud_index_size; | |
154 | extern unsigned long __pgd_index_size; | |
fae22116 | 155 | extern unsigned long __pud_cache_index; |
dd1842a2 AK |
156 | #define PTE_INDEX_SIZE __pte_index_size |
157 | #define PMD_INDEX_SIZE __pmd_index_size | |
158 | #define PUD_INDEX_SIZE __pud_index_size | |
159 | #define PGD_INDEX_SIZE __pgd_index_size | |
738f9645 AK |
160 | /* pmd table use page table fragments */ |
161 | #define PMD_CACHE_INDEX 0 | |
fae22116 | 162 | #define PUD_CACHE_INDEX __pud_cache_index |
dd1842a2 AK |
163 | /* |
164 | * Because of use of pte fragments and THP, size of page table | |
165 | * are not always derived out of index size above. | |
166 | */ | |
167 | extern unsigned long __pte_table_size; | |
168 | extern unsigned long __pmd_table_size; | |
169 | extern unsigned long __pud_table_size; | |
170 | extern unsigned long __pgd_table_size; | |
171 | #define PTE_TABLE_SIZE __pte_table_size | |
172 | #define PMD_TABLE_SIZE __pmd_table_size | |
173 | #define PUD_TABLE_SIZE __pud_table_size | |
174 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
175 | |
176 | extern unsigned long __pmd_val_bits; | |
177 | extern unsigned long __pud_val_bits; | |
178 | extern unsigned long __pgd_val_bits; | |
179 | #define PMD_VAL_BITS __pmd_val_bits | |
180 | #define PUD_VAL_BITS __pud_val_bits | |
181 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
182 | |
183 | extern unsigned long __pte_frag_nr; | |
184 | #define PTE_FRAG_NR __pte_frag_nr | |
185 | extern unsigned long __pte_frag_size_shift; | |
186 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
187 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 | 188 | |
8a6c697b AK |
189 | extern unsigned long __pmd_frag_nr; |
190 | #define PMD_FRAG_NR __pmd_frag_nr | |
191 | extern unsigned long __pmd_frag_size_shift; | |
192 | #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift | |
193 | #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) | |
194 | ||
dd1842a2 AK |
195 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) |
196 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
197 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
198 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
199 | ||
41b7a347 DA |
200 | #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) |
201 | #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) | |
202 | #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) | |
e72421a0 CL |
203 | #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ |
204 | H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) | |
205 | ||
dd1842a2 AK |
206 | /* PMD_SHIFT determines what a second-level page table entry can map */ |
207 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
208 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
209 | #define PMD_MASK (~(PMD_SIZE-1)) | |
210 | ||
211 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
212 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
213 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
214 | #define PUD_MASK (~(PUD_SIZE-1)) | |
215 | ||
216 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
217 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
218 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
219 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
220 | ||
221 | /* Bits to mask out from a PMD to get to the PTE page */ | |
222 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
223 | /* Bits to mask out from a PUD to get to the PMD page */ | |
224 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
225 | /* Bits to mask out from a PGD to get to the PUD page */ | |
2fb47060 | 226 | #define P4D_MASKED_BITS 0xc0000000000000ffUL |
d6a9996e | 227 | |
0c4d2680 AK |
228 | /* |
229 | * Used as an indicator for rcu callback functions | |
230 | */ | |
231 | enum pgtable_index { | |
232 | PTE_INDEX = 0, | |
233 | PMD_INDEX, | |
234 | PUD_INDEX, | |
235 | PGD_INDEX, | |
fadd03c6 AK |
236 | /* |
237 | * Below are used with 4k page size and hugetlb | |
238 | */ | |
239 | HTLB_16M_INDEX, | |
240 | HTLB_16G_INDEX, | |
0c4d2680 AK |
241 | }; |
242 | ||
d6a9996e AK |
243 | extern unsigned long __vmalloc_start; |
244 | extern unsigned long __vmalloc_end; | |
245 | #define VMALLOC_START __vmalloc_start | |
246 | #define VMALLOC_END __vmalloc_end | |
247 | ||
d909f910 NP |
248 | static inline unsigned int ioremap_max_order(void) |
249 | { | |
250 | if (radix_enabled()) | |
251 | return PUD_SHIFT; | |
252 | return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ | |
253 | } | |
254 | #define IOREMAP_MAX_ORDER ioremap_max_order() | |
255 | ||
d6a9996e | 256 | extern unsigned long __kernel_virt_start; |
63ee9b2f | 257 | extern unsigned long __kernel_io_start; |
a35a3c6f | 258 | extern unsigned long __kernel_io_end; |
d6a9996e | 259 | #define KERN_VIRT_START __kernel_virt_start |
63ee9b2f | 260 | #define KERN_IO_START __kernel_io_start |
a35a3c6f AK |
261 | #define KERN_IO_END __kernel_io_end |
262 | ||
d6a9996e | 263 | extern struct page *vmemmap; |
bfa37087 | 264 | extern unsigned long pci_io_base; |
460b9adc PX |
265 | |
266 | #define pmd_leaf pmd_leaf | |
267 | static inline bool pmd_leaf(pmd_t pmd) | |
268 | { | |
269 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); | |
270 | } | |
271 | ||
272 | #define pud_leaf pud_leaf | |
273 | static inline bool pud_leaf(pud_t pud) | |
274 | { | |
275 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); | |
276 | } | |
dd1842a2 | 277 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 278 | |
ab537dca | 279 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 280 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 281 | |
b32d5d7e AK |
282 | #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS |
283 | #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS | |
284 | #else | |
285 | #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS | |
286 | #endif | |
287 | ||
288 | ||
a9252aae AK |
289 | #ifdef CONFIG_PPC_64K_PAGES |
290 | #include <asm/book3s/64/pgtable-64k.h> | |
291 | #else | |
292 | #include <asm/book3s/64/pgtable-4k.h> | |
293 | #endif | |
294 | ||
3dfcb315 | 295 | #include <asm/barrier.h> |
3dfcb315 | 296 | /* |
a35a3c6f | 297 | * IO space itself carved into the PIO region (ISA and PHB IO space) and |
3dfcb315 AK |
298 | * the ioremap space |
299 | * | |
300 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
301 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
302 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
303 | */ | |
3dfcb315 AK |
304 | #define FULL_IO_SIZE 0x80000000ul |
305 | #define ISA_IO_BASE (KERN_IO_START) | |
306 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
307 | #define PHB_IO_BASE (ISA_IO_END) | |
308 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
309 | #define IOREMAP_BASE (PHB_IO_END) | |
4a45b746 | 310 | #define IOREMAP_START (ioremap_bot) |
9ccba66d CL |
311 | #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) |
312 | #define FIXADDR_SIZE SZ_32M | |
d3e01796 | 313 | #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE) |
3dfcb315 | 314 | |
3dfcb315 AK |
315 | #ifndef __ASSEMBLY__ |
316 | ||
317 | /* | |
318 | * This is the default implementation of various PTE accessors, it's | |
319 | * used in all cases except Book3S with 64K pages where we have a | |
320 | * concept of sub-pages | |
321 | */ | |
322 | #ifndef __real_pte | |
323 | ||
ff31e105 | 324 | #define __real_pte(e, p, o) ((real_pte_t){(e)}) |
3dfcb315 | 325 | #define __rpte_to_pte(r) ((r).pte) |
945537df | 326 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
327 | |
328 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
329 | do { \ | |
330 | index = 0; \ | |
331 | shift = mmu_psize_defs[psize].shift; \ | |
332 | ||
333 | #define pte_iterate_hashed_end() } while(0) | |
334 | ||
335 | /* | |
336 | * We expect this to be called only for user addresses or kernel virtual | |
337 | * addresses other than the linear mapping. | |
338 | */ | |
339 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
340 | ||
341 | #endif /* __real_pte */ | |
342 | ||
ac94ac79 AK |
343 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
344 | pte_t *ptep, unsigned long clr, | |
345 | unsigned long set, int huge) | |
346 | { | |
347 | if (radix_enabled()) | |
348 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
349 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
350 | } | |
13f829a5 AK |
351 | /* |
352 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
353 | * We currently remove entries from the hashtable regardless of whether | |
354 | * the entry was young or dirty. | |
355 | * | |
356 | * We should be more intelligent about this but for the moment we override | |
357 | * these functions and force a tlb flush unconditionally | |
358 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
359 | * function for both hash and radix. | |
360 | */ | |
361 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
362 | unsigned long addr, pte_t *ptep) | |
363 | { | |
364 | unsigned long old; | |
365 | ||
66c570f5 | 366 | if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
13f829a5 AK |
367 | return 0; |
368 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
369 | return (old & _PAGE_ACCESSED) != 0; | |
370 | } | |
371 | ||
372 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
373 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
374 | ({ \ | |
3cb1aa7a | 375 | __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ |
13f829a5 AK |
376 | }) |
377 | ||
3cb1aa7a NP |
378 | /* |
379 | * On Book3S CPUs, clearing the accessed bit without a TLB flush | |
380 | * doesn't cause data corruption. [ It could cause incorrect | |
381 | * page aging and the (mistaken) reclaim of hot pages, but the | |
382 | * chance of that should be relatively low. ] | |
383 | * | |
384 | * So as a performance optimization don't flush the TLB when | |
385 | * clearing the accessed bit, it will eventually be flushed by | |
386 | * a context switch or a VM operation anyway. [ In the rare | |
387 | * event of it not getting flushed for a long time the delay | |
388 | * shouldn't really matter because there's no real memory | |
389 | * pressure for swapout to react to. ] | |
b11931e9 NP |
390 | * |
391 | * Note: this optimisation also exists in pte_needs_flush() and | |
392 | * huge_pmd_needs_flush(). | |
3cb1aa7a NP |
393 | */ |
394 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
395 | #define ptep_clear_flush_young ptep_test_and_clear_young | |
396 | ||
397 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
398 | #define pmdp_clear_flush_young pmdp_test_and_clear_young | |
399 | ||
d19469e8 AK |
400 | static inline int pte_write(pte_t pte) |
401 | { | |
d6379159 | 402 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); |
d19469e8 AK |
403 | } |
404 | ||
ca8afd40 CL |
405 | static inline int pte_read(pte_t pte) |
406 | { | |
407 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); | |
408 | } | |
409 | ||
13f829a5 AK |
410 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
411 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
412 | pte_t *ptep) | |
413 | { | |
d6379159 | 414 | if (pte_write(*ptep)) |
52c50ca7 | 415 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); |
13f829a5 AK |
416 | } |
417 | ||
8e581d43 | 418 | #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT |
13f829a5 AK |
419 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, |
420 | unsigned long addr, pte_t *ptep) | |
421 | { | |
d6379159 | 422 | if (pte_write(*ptep)) |
52c50ca7 | 423 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); |
13f829a5 AK |
424 | } |
425 | ||
426 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
427 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
428 | unsigned long addr, pte_t *ptep) | |
429 | { | |
430 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
431 | return __pte(old); | |
432 | } | |
433 | ||
f4894b80 AK |
434 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
435 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
436 | unsigned long addr, | |
437 | pte_t *ptep, int full) | |
438 | { | |
439 | if (full && radix_enabled()) { | |
440 | /* | |
2bf1071a NP |
441 | * We know that this is a full mm pte clear and |
442 | * hence can be sure there is no parallel set_pte. | |
f4894b80 AK |
443 | */ |
444 | return radix__ptep_get_and_clear_full(mm, addr, ptep, full); | |
445 | } | |
446 | return ptep_get_and_clear(mm, addr, ptep); | |
447 | } | |
448 | ||
449 | ||
13f829a5 AK |
450 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
451 | pte_t * ptep) | |
452 | { | |
453 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
454 | } | |
66c570f5 | 455 | |
66c570f5 AK |
456 | static inline int pte_dirty(pte_t pte) |
457 | { | |
458 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); | |
459 | } | |
460 | ||
461 | static inline int pte_young(pte_t pte) | |
462 | { | |
463 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); | |
464 | } | |
465 | ||
466 | static inline int pte_special(pte_t pte) | |
467 | { | |
468 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); | |
469 | } | |
470 | ||
daba7902 CL |
471 | static inline bool pte_exec(pte_t pte) |
472 | { | |
473 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); | |
474 | } | |
475 | ||
13f829a5 AK |
476 | |
477 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
478 | static inline bool pte_soft_dirty(pte_t pte) | |
479 | { | |
66c570f5 | 480 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 | 481 | } |
66c570f5 | 482 | |
13f829a5 AK |
483 | static inline pte_t pte_mksoft_dirty(pte_t pte) |
484 | { | |
1b2443a5 | 485 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
486 | } |
487 | ||
488 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
489 | { | |
1b2443a5 | 490 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
491 | } |
492 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
493 | ||
494 | #ifdef CONFIG_NUMA_BALANCING | |
13f829a5 AK |
495 | static inline int pte_protnone(pte_t pte) |
496 | { | |
c137a275 AK |
497 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == |
498 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
499 | } | |
13f829a5 AK |
500 | #endif /* CONFIG_NUMA_BALANCING */ |
501 | ||
ec4abf1e AK |
502 | static inline bool pte_hw_valid(pte_t pte) |
503 | { | |
504 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == | |
505 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
506 | } | |
507 | ||
13f829a5 AK |
508 | static inline int pte_present(pte_t pte) |
509 | { | |
bd0dbb73 AK |
510 | /* |
511 | * A pte is considerent present if _PAGE_PRESENT is set. | |
512 | * We also need to consider the pte present which is marked | |
513 | * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID | |
514 | * if we find _PAGE_PRESENT cleared. | |
515 | */ | |
f72a85e3 | 516 | |
ec4abf1e AK |
517 | if (pte_hw_valid(pte)) |
518 | return true; | |
519 | return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == | |
520 | cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); | |
daba7902 CL |
521 | } |
522 | ||
bca7aacf | 523 | #ifdef CONFIG_PPC_MEM_KEYS |
f2407ef3 | 524 | extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); |
bca7aacf RP |
525 | #else |
526 | static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) | |
527 | { | |
528 | return true; | |
529 | } | |
530 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
f2407ef3 | 531 | |
1b2443a5 CL |
532 | static inline bool pte_user(pte_t pte) |
533 | { | |
534 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); | |
535 | } | |
536 | ||
f72a85e3 AK |
537 | #define pte_access_permitted pte_access_permitted |
538 | static inline bool pte_access_permitted(pte_t pte, bool write) | |
539 | { | |
f72a85e3 | 540 | /* |
773b93f1 AKI |
541 | * _PAGE_READ is needed for any access and will be cleared for |
542 | * PROT_NONE. Execute-only mapping via PROT_EXEC also returns false. | |
f72a85e3 | 543 | */ |
1b2443a5 | 544 | if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) |
f72a85e3 AK |
545 | return false; |
546 | ||
1b2443a5 | 547 | if (write && !pte_write(pte)) |
f72a85e3 | 548 | return false; |
bca7aacf RP |
549 | |
550 | return arch_pte_access_permitted(pte_val(pte), write, 0); | |
f72a85e3 AK |
551 | } |
552 | ||
13f829a5 AK |
553 | /* |
554 | * Conversion functions: convert a page and protection to a page entry, | |
555 | * and a page entry and page directory to the page they refer to. | |
556 | * | |
557 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
558 | * long for now. | |
559 | */ | |
560 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
561 | { | |
6bb25170 NP |
562 | VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); |
563 | VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); | |
564 | ||
379c926d | 565 | return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); |
13f829a5 AK |
566 | } |
567 | ||
13f829a5 AK |
568 | /* Generic modifiers for PTE bits */ |
569 | static inline pte_t pte_wrprotect(pte_t pte) | |
570 | { | |
1b2443a5 | 571 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
13f829a5 AK |
572 | } |
573 | ||
daba7902 CL |
574 | static inline pte_t pte_exprotect(pte_t pte) |
575 | { | |
1b2443a5 | 576 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); |
13f829a5 AK |
577 | } |
578 | ||
579 | static inline pte_t pte_mkclean(pte_t pte) | |
580 | { | |
1b2443a5 | 581 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); |
13f829a5 AK |
582 | } |
583 | ||
584 | static inline pte_t pte_mkold(pte_t pte) | |
585 | { | |
1b2443a5 | 586 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); |
13f829a5 AK |
587 | } |
588 | ||
daba7902 CL |
589 | static inline pte_t pte_mkexec(pte_t pte) |
590 | { | |
1b2443a5 | 591 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); |
daba7902 CL |
592 | } |
593 | ||
2f0584f3 | 594 | static inline pte_t pte_mkwrite_novma(pte_t pte) |
13f829a5 AK |
595 | { |
596 | /* | |
597 | * write implies read, hence set both | |
598 | */ | |
1b2443a5 | 599 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); |
13f829a5 AK |
600 | } |
601 | ||
602 | static inline pte_t pte_mkdirty(pte_t pte) | |
603 | { | |
1b2443a5 | 604 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); |
13f829a5 AK |
605 | } |
606 | ||
607 | static inline pte_t pte_mkyoung(pte_t pte) | |
608 | { | |
1b2443a5 | 609 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); |
13f829a5 AK |
610 | } |
611 | ||
612 | static inline pte_t pte_mkspecial(pte_t pte) | |
613 | { | |
1b2443a5 | 614 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); |
13f829a5 AK |
615 | } |
616 | ||
617 | static inline pte_t pte_mkhuge(pte_t pte) | |
618 | { | |
619 | return pte; | |
620 | } | |
621 | ||
ebd31197 OH |
622 | static inline pte_t pte_mkdevmap(pte_t pte) |
623 | { | |
1b2443a5 | 624 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); |
ebd31197 OH |
625 | } |
626 | ||
c9c98bc5 OH |
627 | /* |
628 | * This is potentially called with a pmd as the argument, in which case it's not | |
629 | * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. | |
630 | * That's because the bit we use for _PAGE_DEVMAP is not reserved for software | |
631 | * use in page directory entries (ie. non-ptes). | |
632 | */ | |
ebd31197 OH |
633 | static inline int pte_devmap(pte_t pte) |
634 | { | |
2b4a6cc9 | 635 | __be64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); |
c9c98bc5 OH |
636 | |
637 | return (pte_raw(pte) & mask) == mask; | |
ebd31197 OH |
638 | } |
639 | ||
13f829a5 AK |
640 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
641 | { | |
642 | /* FIXME!! check whether this need to be a conditional */ | |
1b2443a5 CL |
643 | return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | |
644 | cpu_to_be64(pgprot_val(newprot))); | |
34fbadd8 AK |
645 | } |
646 | ||
647 | /* Encode and de-code a swap entry */ | |
648 | #define MAX_SWAPFILES_CHECK() do { \ | |
649 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
650 | /* \ | |
651 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
652 | * We filter HPTEFLAGS on set_pte. \ | |
653 | */ \ | |
03ac1b71 | 654 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ |
34fbadd8 | 655 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ |
bff9beaa | 656 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ |
34fbadd8 | 657 | } while (0) |
3159f943 | 658 | |
34fbadd8 | 659 | #define SWP_TYPE_BITS 5 |
03ac1b71 DH |
660 | #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) |
661 | #define __swp_type(x) ((x).val & SWP_TYPE_MASK) | |
34fbadd8 AK |
662 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) |
663 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
03ac1b71 | 664 | (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) |
34fbadd8 AK |
665 | /* |
666 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
667 | * swap type and offset we get from swap and convert that to pte to find a | |
668 | * matching pte in linux page table. | |
669 | * Clear bits not found in swap entries here. | |
670 | */ | |
671 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
672 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
a0820ff3 AK |
673 | #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) |
674 | #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) | |
34fbadd8 AK |
675 | |
676 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
bff9beaa | 677 | #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY |
34fbadd8 AK |
678 | #else |
679 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
680 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
681 | ||
bff9beaa DH |
682 | #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT |
683 | ||
34fbadd8 AK |
684 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
685 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
686 | { | |
1b2443a5 | 687 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 688 | } |
66c570f5 | 689 | |
34fbadd8 AK |
690 | static inline bool pte_swp_soft_dirty(pte_t pte) |
691 | { | |
66c570f5 | 692 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 693 | } |
66c570f5 | 694 | |
34fbadd8 AK |
695 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) |
696 | { | |
1b2443a5 | 697 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 AK |
698 | } |
699 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
700 | ||
bff9beaa DH |
701 | static inline pte_t pte_swp_mkexclusive(pte_t pte) |
702 | { | |
703 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
704 | } | |
705 | ||
706 | static inline int pte_swp_exclusive(pte_t pte) | |
707 | { | |
708 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
709 | } | |
710 | ||
711 | static inline pte_t pte_swp_clear_exclusive(pte_t pte) | |
712 | { | |
713 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); | |
714 | } | |
715 | ||
34fbadd8 AK |
716 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) |
717 | { | |
718 | /* | |
719 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
720 | */ | |
721 | if (access & ~ptev) | |
722 | return false; | |
723 | /* | |
724 | * This check for access to privilege space | |
725 | */ | |
726 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
727 | return false; | |
728 | ||
729 | return true; | |
730 | } | |
ac94ac79 AK |
731 | /* |
732 | * Generic functions with hash/radix callbacks | |
733 | */ | |
734 | ||
e4c1112c | 735 | static inline void __ptep_set_access_flags(struct vm_area_struct *vma, |
b3603e17 | 736 | pte_t *ptep, pte_t entry, |
e4c1112c AK |
737 | unsigned long address, |
738 | int psize) | |
ac94ac79 AK |
739 | { |
740 | if (radix_enabled()) | |
e4c1112c AK |
741 | return radix__ptep_set_access_flags(vma, ptep, entry, |
742 | address, psize); | |
ac94ac79 AK |
743 | return hash__ptep_set_access_flags(ptep, entry); |
744 | } | |
745 | ||
746 | #define __HAVE_ARCH_PTE_SAME | |
747 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
748 | { | |
749 | if (radix_enabled()) | |
750 | return radix__pte_same(pte_a, pte_b); | |
751 | return hash__pte_same(pte_a, pte_b); | |
752 | } | |
753 | ||
754 | static inline int pte_none(pte_t pte) | |
755 | { | |
756 | if (radix_enabled()) | |
757 | return radix__pte_none(pte); | |
758 | return hash__pte_none(pte); | |
759 | } | |
760 | ||
761 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
762 | pte_t *ptep, pte_t pte, int percpu) | |
763 | { | |
379c926d AK |
764 | |
765 | VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); | |
766 | /* | |
767 | * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE | |
768 | * in all the callers. | |
769 | */ | |
770 | pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); | |
771 | ||
ac94ac79 AK |
772 | if (radix_enabled()) |
773 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
774 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
775 | } | |
34fbadd8 | 776 | |
12564485 SA |
777 | #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
778 | ||
13f829a5 AK |
779 | #define pgprot_noncached pgprot_noncached |
780 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
781 | { | |
782 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
783 | _PAGE_NON_IDEMPOTENT); | |
784 | } | |
785 | ||
786 | #define pgprot_noncached_wc pgprot_noncached_wc | |
787 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
788 | { | |
789 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
790 | _PAGE_TOLERANT); | |
791 | } | |
792 | ||
793 | #define pgprot_cached pgprot_cached | |
794 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
795 | { | |
796 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
797 | } | |
798 | ||
799 | #define pgprot_writecombine pgprot_writecombine | |
800 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
801 | { | |
802 | return pgprot_noncached_wc(prot); | |
803 | } | |
804 | /* | |
805 | * check a pte mapping have cache inhibited property | |
806 | */ | |
807 | static inline bool pte_ci(pte_t pte) | |
808 | { | |
1b2443a5 | 809 | __be64 pte_v = pte_raw(pte); |
13f829a5 | 810 | |
1b2443a5 CL |
811 | if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || |
812 | ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) | |
13f829a5 AK |
813 | return true; |
814 | return false; | |
815 | } | |
816 | ||
f281b5d5 AK |
817 | static inline void pmd_clear(pmd_t *pmdp) |
818 | { | |
392b4669 AK |
819 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
820 | /* | |
821 | * Don't use this if we can possibly have a hash page table | |
822 | * entry mapping this. | |
823 | */ | |
824 | WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
825 | } | |
f281b5d5 AK |
826 | *pmdp = __pmd(0); |
827 | } | |
828 | ||
66c570f5 AK |
829 | static inline int pmd_none(pmd_t pmd) |
830 | { | |
831 | return !pmd_raw(pmd); | |
832 | } | |
833 | ||
834 | static inline int pmd_present(pmd_t pmd) | |
835 | { | |
da7ad366 AK |
836 | /* |
837 | * A pmd is considerent present if _PAGE_PRESENT is set. | |
838 | * We also need to consider the pmd present which is marked | |
839 | * invalid during a split. Hence we look for _PAGE_INVALID | |
840 | * if we find _PAGE_PRESENT cleared. | |
841 | */ | |
842 | if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) | |
843 | return true; | |
66c570f5 | 844 | |
da7ad366 | 845 | return false; |
66c570f5 | 846 | } |
3dfcb315 | 847 | |
33258a1d NP |
848 | static inline int pmd_is_serializing(pmd_t pmd) |
849 | { | |
850 | /* | |
851 | * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear | |
852 | * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). | |
853 | * | |
854 | * This condition may also occur when flushing a pmd while flushing | |
855 | * it (see ptep_modify_prot_start), so callers must ensure this | |
856 | * case is fine as well. | |
857 | */ | |
858 | if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == | |
859 | cpu_to_be64(_PAGE_INVALID)) | |
860 | return true; | |
861 | ||
862 | return false; | |
863 | } | |
864 | ||
ac94ac79 AK |
865 | static inline int pmd_bad(pmd_t pmd) |
866 | { | |
867 | if (radix_enabled()) | |
868 | return radix__pmd_bad(pmd); | |
869 | return hash__pmd_bad(pmd); | |
870 | } | |
871 | ||
f281b5d5 AK |
872 | static inline void pud_clear(pud_t *pudp) |
873 | { | |
392b4669 AK |
874 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
875 | /* | |
876 | * Don't use this if we can possibly have a hash page table | |
877 | * entry mapping this. | |
878 | */ | |
879 | WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
880 | } | |
f281b5d5 AK |
881 | *pudp = __pud(0); |
882 | } | |
883 | ||
66c570f5 AK |
884 | static inline int pud_none(pud_t pud) |
885 | { | |
886 | return !pud_raw(pud); | |
887 | } | |
888 | ||
889 | static inline int pud_present(pud_t pud) | |
890 | { | |
a5800762 | 891 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 892 | } |
3dfcb315 AK |
893 | |
894 | extern struct page *pud_page(pud_t pud); | |
371352ca | 895 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
896 | static inline pte_t pud_pte(pud_t pud) |
897 | { | |
66c570f5 | 898 | return __pte_raw(pud_raw(pud)); |
3dfcb315 AK |
899 | } |
900 | ||
901 | static inline pud_t pte_pud(pte_t pte) | |
902 | { | |
66c570f5 | 903 | return __pud_raw(pte_raw(pte)); |
3dfcb315 | 904 | } |
27af67f3 AK |
905 | |
906 | static inline pte_t *pudp_ptep(pud_t *pud) | |
907 | { | |
908 | return (pte_t *)pud; | |
909 | } | |
910 | ||
911 | #define pud_pfn(pud) pte_pfn(pud_pte(pud)) | |
912 | #define pud_dirty(pud) pte_dirty(pud_pte(pud)) | |
913 | #define pud_young(pud) pte_young(pud_pte(pud)) | |
914 | #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud))) | |
915 | #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud))) | |
916 | #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud))) | |
917 | #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud))) | |
918 | #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) | |
f441ff73 | 919 | #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) |
3dfcb315 | 920 | #define pud_write(pud) pte_write(pud_pte(pud)) |
ac94ac79 | 921 | |
27af67f3 AK |
922 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
923 | #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud)) | |
924 | #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud))) | |
925 | #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud))) | |
926 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
927 | ||
ac94ac79 AK |
928 | static inline int pud_bad(pud_t pud) |
929 | { | |
930 | if (radix_enabled()) | |
931 | return radix__pud_bad(pud); | |
932 | return hash__pud_bad(pud); | |
933 | } | |
934 | ||
f72a85e3 AK |
935 | #define pud_access_permitted pud_access_permitted |
936 | static inline bool pud_access_permitted(pud_t pud, bool write) | |
937 | { | |
938 | return pte_access_permitted(pud_pte(pud), write); | |
939 | } | |
ac94ac79 | 940 | |
2fb47060 MR |
941 | #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) |
942 | static inline __be64 p4d_raw(p4d_t x) | |
943 | { | |
944 | return pgd_raw(x.pgd); | |
945 | } | |
946 | ||
947 | #define p4d_write(p4d) pte_write(p4d_pte(p4d)) | |
3dfcb315 | 948 | |
2fb47060 | 949 | static inline void p4d_clear(p4d_t *p4dp) |
368ced78 | 950 | { |
2fb47060 | 951 | *p4dp = __p4d(0); |
368ced78 AK |
952 | } |
953 | ||
2fb47060 | 954 | static inline int p4d_none(p4d_t p4d) |
66c570f5 | 955 | { |
2fb47060 | 956 | return !p4d_raw(p4d); |
66c570f5 AK |
957 | } |
958 | ||
2fb47060 | 959 | static inline int p4d_present(p4d_t p4d) |
66c570f5 | 960 | { |
2fb47060 | 961 | return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 962 | } |
368ced78 | 963 | |
2fb47060 | 964 | static inline pte_t p4d_pte(p4d_t p4d) |
368ced78 | 965 | { |
2fb47060 | 966 | return __pte_raw(p4d_raw(p4d)); |
368ced78 AK |
967 | } |
968 | ||
2fb47060 | 969 | static inline p4d_t pte_p4d(pte_t pte) |
368ced78 | 970 | { |
2fb47060 | 971 | return __p4d_raw(pte_raw(pte)); |
368ced78 AK |
972 | } |
973 | ||
2fb47060 | 974 | static inline int p4d_bad(p4d_t p4d) |
ac94ac79 AK |
975 | { |
976 | if (radix_enabled()) | |
2fb47060 MR |
977 | return radix__p4d_bad(p4d); |
978 | return hash__p4d_bad(p4d); | |
ac94ac79 AK |
979 | } |
980 | ||
2fb47060 MR |
981 | #define p4d_access_permitted p4d_access_permitted |
982 | static inline bool p4d_access_permitted(p4d_t p4d, bool write) | |
f72a85e3 | 983 | { |
2fb47060 | 984 | return pte_access_permitted(p4d_pte(p4d), write); |
f72a85e3 AK |
985 | } |
986 | ||
2fb47060 | 987 | extern struct page *p4d_page(p4d_t p4d); |
368ced78 | 988 | |
aba480e1 AK |
989 | /* Pointers in the page table tree are physical addresses */ |
990 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
991 | ||
dc4875f0 AK |
992 | static inline pud_t *p4d_pgtable(p4d_t p4d) |
993 | { | |
994 | return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); | |
995 | } | |
aba480e1 | 996 | |
9cf6fa24 AK |
997 | static inline pmd_t *pud_pgtable(pud_t pud) |
998 | { | |
999 | return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); | |
1000 | } | |
1001 | ||
3dfcb315 AK |
1002 | #define pmd_ERROR(e) \ |
1003 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
1004 | #define pud_ERROR(e) \ |
1005 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
1006 | #define pgd_ERROR(e) \ |
1007 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
1008 | ||
c766ee72 | 1009 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) |
7207f436 | 1010 | { |
d9225ad9 AK |
1011 | if (radix_enabled()) { |
1012 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
1013 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
1014 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
1015 | #endif | |
c766ee72 | 1016 | return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); |
d9225ad9 | 1017 | } |
c766ee72 | 1018 | return hash__map_kernel_page(ea, pa, prot); |
7207f436 | 1019 | } |
31a14fae | 1020 | |
aec98260 CL |
1021 | void unmap_kernel_page(unsigned long va); |
1022 | ||
31a14fae AK |
1023 | static inline int __meminit vmemmap_create_mapping(unsigned long start, |
1024 | unsigned long page_size, | |
1025 | unsigned long phys) | |
7207f436 | 1026 | { |
d9225ad9 AK |
1027 | if (radix_enabled()) |
1028 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 1029 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 1030 | } |
31a14fae AK |
1031 | |
1032 | #ifdef CONFIG_MEMORY_HOTPLUG | |
1033 | static inline void vmemmap_remove_mapping(unsigned long start, | |
1034 | unsigned long page_size) | |
7207f436 | 1035 | { |
d9225ad9 AK |
1036 | if (radix_enabled()) |
1037 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 1038 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 1039 | } |
31a14fae | 1040 | #endif |
3dfcb315 | 1041 | |
3dfcb315 AK |
1042 | static inline pte_t pmd_pte(pmd_t pmd) |
1043 | { | |
66c570f5 | 1044 | return __pte_raw(pmd_raw(pmd)); |
3dfcb315 AK |
1045 | } |
1046 | ||
1047 | static inline pmd_t pte_pmd(pte_t pte) | |
1048 | { | |
66c570f5 | 1049 | return __pmd_raw(pte_raw(pte)); |
3dfcb315 AK |
1050 | } |
1051 | ||
1052 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
1053 | { | |
1054 | return (pte_t *)pmd; | |
1055 | } | |
3dfcb315 AK |
1056 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
1057 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
1058 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
1059 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
1060 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
1061 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 1062 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 | 1063 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
2f0584f3 | 1064 | #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) |
7207f436 LD |
1065 | |
1066 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
1067 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
1068 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
1069 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
a0820ff3 AK |
1070 | |
1071 | #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION | |
1072 | #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) | |
1073 | #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) | |
1074 | #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) | |
1075 | #endif | |
7207f436 LD |
1076 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ |
1077 | ||
1ca72129 AK |
1078 | #ifdef CONFIG_NUMA_BALANCING |
1079 | static inline int pmd_protnone(pmd_t pmd) | |
1080 | { | |
1081 | return pte_protnone(pmd_pte(pmd)); | |
1082 | } | |
1083 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 | 1084 | |
3dfcb315 AK |
1085 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
1086 | ||
f72a85e3 AK |
1087 | #define pmd_access_permitted pmd_access_permitted |
1088 | static inline bool pmd_access_permitted(pmd_t pmd, bool write) | |
1089 | { | |
33258a1d NP |
1090 | /* |
1091 | * pmdp_invalidate sets this combination (which is not caught by | |
1092 | * !pte_present() check in pte_access_permitted), to prevent | |
1093 | * lock-free lookups, as part of the serialize_against_pte_lookup() | |
1094 | * synchronisation. | |
1095 | * | |
1096 | * This also catches the case where the PTE's hardware PRESENT bit is | |
1097 | * cleared while TLB is flushed, which is suboptimal but should not | |
1098 | * be frequent. | |
1099 | */ | |
1100 | if (pmd_is_serializing(pmd)) | |
1101 | return false; | |
1102 | ||
f72a85e3 AK |
1103 | return pte_access_permitted(pmd_pte(pmd), write); |
1104 | } | |
1105 | ||
6a1ea362 AK |
1106 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1107 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
27af67f3 | 1108 | extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot); |
6a1ea362 AK |
1109 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); |
1110 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
1111 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1112 | pmd_t *pmdp, pmd_t pmd); | |
27af67f3 AK |
1113 | extern void set_pud_at(struct mm_struct *mm, unsigned long addr, |
1114 | pud_t *pudp, pud_t pud); | |
1115 | ||
18594f9b NP |
1116 | static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, |
1117 | unsigned long addr, pmd_t *pmd) | |
1118 | { | |
1119 | } | |
1120 | ||
27af67f3 AK |
1121 | static inline void update_mmu_cache_pud(struct vm_area_struct *vma, |
1122 | unsigned long addr, pud_t *pud) | |
1123 | { | |
1124 | } | |
1125 | ||
3df33f12 AK |
1126 | extern int hash__has_transparent_hugepage(void); |
1127 | static inline int has_transparent_hugepage(void) | |
1128 | { | |
bde3eb62 AK |
1129 | if (radix_enabled()) |
1130 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
1131 | return hash__has_transparent_hugepage(); |
1132 | } | |
c04a5880 | 1133 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 1134 | |
27af67f3 AK |
1135 | static inline int has_transparent_pud_hugepage(void) |
1136 | { | |
1137 | if (radix_enabled()) | |
1138 | return radix__has_transparent_pud_hugepage(); | |
1139 | return 0; | |
1140 | } | |
1141 | #define has_transparent_pud_hugepage has_transparent_pud_hugepage | |
1142 | ||
3df33f12 AK |
1143 | static inline unsigned long |
1144 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
1145 | unsigned long clr, unsigned long set) | |
3dfcb315 | 1146 | { |
bde3eb62 AK |
1147 | if (radix_enabled()) |
1148 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
1149 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
1150 | } | |
1151 | ||
27af67f3 AK |
1152 | static inline unsigned long |
1153 | pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp, | |
1154 | unsigned long clr, unsigned long set) | |
1155 | { | |
1156 | if (radix_enabled()) | |
1157 | return radix__pud_hugepage_update(mm, addr, pudp, clr, set); | |
1158 | BUG(); | |
1159 | return pud_val(*pudp); | |
1160 | } | |
1161 | ||
3df33f12 AK |
1162 | /* |
1163 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
1164 | * the below will work for radix too | |
1165 | */ | |
1166 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
1167 | unsigned long addr, pmd_t *pmdp) | |
1168 | { | |
1169 | unsigned long old; | |
1170 | ||
66c570f5 | 1171 | if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
3df33f12 AK |
1172 | return 0; |
1173 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
1174 | return ((old & _PAGE_ACCESSED) != 0); | |
1175 | } | |
1176 | ||
27af67f3 AK |
1177 | static inline int __pudp_test_and_clear_young(struct mm_struct *mm, |
1178 | unsigned long addr, pud_t *pudp) | |
1179 | { | |
1180 | unsigned long old; | |
1181 | ||
1182 | if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
1183 | return 0; | |
1184 | old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0); | |
1185 | return ((old & _PAGE_ACCESSED) != 0); | |
1186 | } | |
1187 | ||
3df33f12 AK |
1188 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1189 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1190 | pmd_t *pmdp) | |
1191 | { | |
d6379159 | 1192 | if (pmd_write(*pmdp)) |
52c50ca7 | 1193 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); |
3dfcb315 AK |
1194 | } |
1195 | ||
27af67f3 AK |
1196 | #define __HAVE_ARCH_PUDP_SET_WRPROTECT |
1197 | static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1198 | pud_t *pudp) | |
1199 | { | |
1200 | if (pud_write(*pudp)) | |
1201 | pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0); | |
1202 | } | |
1203 | ||
8890e033 AK |
1204 | /* |
1205 | * Only returns true for a THP. False for pmd migration entry. | |
1206 | * We also need to return true when we come across a pte that | |
1207 | * in between a thp split. While splitting THP, we mark the pmd | |
1208 | * invalid (pmdp_invalidate()) before we set it with pte page | |
1209 | * address. A pmd_trans_huge() check against a pmd entry during that time | |
1210 | * should return true. | |
1211 | * We should not call this on a hugetlb entry. We should check for HugeTLB | |
1212 | * entry using vma->vm_flags | |
ee65728e | 1213 | * The page table walk rule is explained in Documentation/mm/transhuge.rst |
8890e033 | 1214 | */ |
ab624762 AK |
1215 | static inline int pmd_trans_huge(pmd_t pmd) |
1216 | { | |
8890e033 AK |
1217 | if (!pmd_present(pmd)) |
1218 | return false; | |
1219 | ||
ab624762 AK |
1220 | if (radix_enabled()) |
1221 | return radix__pmd_trans_huge(pmd); | |
1222 | return hash__pmd_trans_huge(pmd); | |
1223 | } | |
1224 | ||
27af67f3 AK |
1225 | static inline int pud_trans_huge(pud_t pud) |
1226 | { | |
1227 | if (!pud_present(pud)) | |
1228 | return false; | |
1229 | ||
1230 | if (radix_enabled()) | |
1231 | return radix__pud_trans_huge(pud); | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | ||
ab624762 AK |
1236 | #define __HAVE_ARCH_PMD_SAME |
1237 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
1238 | { | |
1239 | if (radix_enabled()) | |
1240 | return radix__pmd_same(pmd_a, pmd_b); | |
1241 | return hash__pmd_same(pmd_a, pmd_b); | |
1242 | } | |
1243 | ||
27af67f3 AK |
1244 | #define pud_same pud_same |
1245 | static inline int pud_same(pud_t pud_a, pud_t pud_b) | |
1246 | { | |
1247 | if (radix_enabled()) | |
1248 | return radix__pud_same(pud_a, pud_b); | |
1249 | return hash__pud_same(pud_a, pud_b); | |
1250 | } | |
1251 | ||
1252 | ||
53f45ecc | 1253 | static inline pmd_t __pmd_mkhuge(pmd_t pmd) |
3dfcb315 | 1254 | { |
ab624762 AK |
1255 | if (radix_enabled()) |
1256 | return radix__pmd_mkhuge(pmd); | |
1257 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
1258 | } |
1259 | ||
27af67f3 AK |
1260 | static inline pud_t __pud_mkhuge(pud_t pud) |
1261 | { | |
1262 | if (radix_enabled()) | |
1263 | return radix__pud_mkhuge(pud); | |
1264 | BUG(); | |
1265 | return pud; | |
1266 | } | |
1267 | ||
53f45ecc AK |
1268 | /* |
1269 | * pfn_pmd return a pmd_t that can be used as pmd pte entry. | |
1270 | */ | |
1271 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1272 | { | |
1273 | #ifdef CONFIG_DEBUG_VM | |
1274 | if (radix_enabled()) | |
1275 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1276 | else | |
1277 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != | |
1278 | cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); | |
1279 | #endif | |
1280 | return pmd; | |
1281 | } | |
1282 | ||
27af67f3 AK |
1283 | static inline pud_t pud_mkhuge(pud_t pud) |
1284 | { | |
1285 | #ifdef CONFIG_DEBUG_VM | |
1286 | if (radix_enabled()) | |
1287 | WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1288 | else | |
1289 | WARN_ON(1); | |
1290 | #endif | |
1291 | return pud; | |
1292 | } | |
1293 | ||
1294 | ||
3dfcb315 AK |
1295 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1296 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1297 | unsigned long address, pmd_t *pmdp, | |
1298 | pmd_t entry, int dirty); | |
27af67f3 AK |
1299 | #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS |
1300 | extern int pudp_set_access_flags(struct vm_area_struct *vma, | |
1301 | unsigned long address, pud_t *pudp, | |
1302 | pud_t entry, int dirty); | |
3dfcb315 | 1303 | |
3dfcb315 AK |
1304 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1305 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1306 | unsigned long address, pmd_t *pmdp); | |
27af67f3 AK |
1307 | #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG |
1308 | extern int pudp_test_and_clear_young(struct vm_area_struct *vma, | |
1309 | unsigned long address, pud_t *pudp); | |
1310 | ||
3dfcb315 AK |
1311 | |
1312 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
1313 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
1314 | unsigned long addr, pmd_t *pmdp) | |
1315 | { | |
bde3eb62 AK |
1316 | if (radix_enabled()) |
1317 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
1318 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
1319 | } | |
3dfcb315 | 1320 | |
27af67f3 AK |
1321 | #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR |
1322 | static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, | |
1323 | unsigned long addr, pud_t *pudp) | |
1324 | { | |
1325 | if (radix_enabled()) | |
1326 | return radix__pudp_huge_get_and_clear(mm, addr, pudp); | |
1327 | BUG(); | |
1328 | return *pudp; | |
1329 | } | |
1330 | ||
3df33f12 AK |
1331 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1332 | unsigned long address, pmd_t *pmdp) | |
1333 | { | |
bde3eb62 AK |
1334 | if (radix_enabled()) |
1335 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
1336 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
1337 | } | |
3dfcb315 AK |
1338 | #define pmdp_collapse_flush pmdp_collapse_flush |
1339 | ||
75358ea3 AK |
1340 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1341 | pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1342 | unsigned long addr, | |
1343 | pmd_t *pmdp, int full); | |
1344 | ||
27af67f3 AK |
1345 | #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL |
1346 | pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1347 | unsigned long addr, | |
1348 | pud_t *pudp, int full); | |
1349 | ||
3dfcb315 | 1350 | #define __HAVE_ARCH_PGTABLE_DEPOSIT |
3df33f12 AK |
1351 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
1352 | pmd_t *pmdp, pgtable_t pgtable) | |
1353 | { | |
bde3eb62 AK |
1354 | if (radix_enabled()) |
1355 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
1356 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
1357 | } | |
1358 | ||
3dfcb315 | 1359 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
1360 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
1361 | pmd_t *pmdp) | |
1362 | { | |
bde3eb62 AK |
1363 | if (radix_enabled()) |
1364 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
1365 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
1366 | } | |
3dfcb315 AK |
1367 | |
1368 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
8cc931e0 AK |
1369 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, |
1370 | pmd_t *pmdp); | |
3dfcb315 AK |
1371 | |
1372 | #define pmd_move_must_withdraw pmd_move_must_withdraw | |
1373 | struct spinlock; | |
579b9239 AK |
1374 | extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, |
1375 | struct spinlock *old_pmd_ptl, | |
1376 | struct vm_area_struct *vma); | |
1377 | /* | |
1378 | * Hash translation mode use the deposited table to store hash pte | |
1379 | * slot information. | |
1380 | */ | |
953c66c2 AK |
1381 | #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit |
1382 | static inline bool arch_needs_pgtable_deposit(void) | |
1383 | { | |
1384 | if (radix_enabled()) | |
1385 | return false; | |
1386 | return true; | |
1387 | } | |
fa4531f7 | 1388 | extern void serialize_against_pte_lookup(struct mm_struct *mm); |
953c66c2 | 1389 | |
ebd31197 OH |
1390 | |
1391 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) | |
1392 | { | |
36b78402 AK |
1393 | if (radix_enabled()) |
1394 | return radix__pmd_mkdevmap(pmd); | |
1395 | return hash__pmd_mkdevmap(pmd); | |
ebd31197 OH |
1396 | } |
1397 | ||
27af67f3 AK |
1398 | static inline pud_t pud_mkdevmap(pud_t pud) |
1399 | { | |
1400 | if (radix_enabled()) | |
1401 | return radix__pud_mkdevmap(pud); | |
1402 | BUG(); | |
1403 | return pud; | |
1404 | } | |
1405 | ||
ebd31197 OH |
1406 | static inline int pmd_devmap(pmd_t pmd) |
1407 | { | |
1408 | return pte_devmap(pmd_pte(pmd)); | |
1409 | } | |
1410 | ||
1411 | static inline int pud_devmap(pud_t pud) | |
1412 | { | |
27af67f3 | 1413 | return pte_devmap(pud_pte(pud)); |
ebd31197 OH |
1414 | } |
1415 | ||
1416 | static inline int pgd_devmap(pgd_t pgd) | |
1417 | { | |
1418 | return 0; | |
1419 | } | |
6a1ea362 | 1420 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
ebd31197 | 1421 | |
5b323367 AK |
1422 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1423 | pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); | |
1424 | void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, | |
1425 | pte_t *, pte_t, pte_t); | |
1426 | ||
1427 | /* | |
1428 | * Returns true for a R -> RW upgrade of pte | |
1429 | */ | |
1430 | static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) | |
1431 | { | |
1432 | if (!(old_val & _PAGE_READ)) | |
1433 | return false; | |
1434 | ||
1435 | if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) | |
1436 | return true; | |
1437 | ||
1438 | return false; | |
1439 | } | |
029d9252 | 1440 | |
3dfcb315 AK |
1441 | #endif /* __ASSEMBLY__ */ |
1442 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |