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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
3dfcb315 AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 | 4 | |
2fb47060 | 5 | #include <asm-generic/pgtable-nop4d.h> |
9849a569 | 6 | |
c137a275 AK |
7 | #ifndef __ASSEMBLY__ |
8 | #include <linux/mmdebug.h> | |
ebd31197 | 9 | #include <linux/bug.h> |
9ccba66d | 10 | #include <linux/sizes.h> |
c137a275 | 11 | #endif |
9849a569 | 12 | |
2e873519 AK |
13 | /* |
14 | * Common bits between hash and Radix page table | |
15 | */ | |
2e873519 AK |
16 | |
17 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
18 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
19 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
58f53462 | 20 | #define _PAGE_NA _PAGE_PRIVILEGED |
b1fba034 | 21 | #define _PAGE_NAX _PAGE_EXEC |
58f53462 CL |
22 | #define _PAGE_RO _PAGE_READ |
23 | #define _PAGE_ROX (_PAGE_READ | _PAGE_EXEC) | |
2e873519 AK |
24 | #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) |
25 | #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) | |
26 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ | |
12564485 | 27 | #define _PAGE_SAO 0x00010 /* Strong access order */ |
2e873519 AK |
28 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ |
29 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
30 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
31 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 32 | /* |
2e873519 | 33 | * Software bits |
3dfcb315 | 34 | */ |
69dfbaeb AK |
35 | #define _RPAGE_SW0 0x2000000000000000UL |
36 | #define _RPAGE_SW1 0x00800 | |
37 | #define _RPAGE_SW2 0x00400 | |
38 | #define _RPAGE_SW3 0x00200 | |
ee8b3933 AK |
39 | #define _RPAGE_RSV1 0x00040UL |
40 | ||
41 | #define _RPAGE_PKEY_BIT4 0x1000000000000000UL | |
42 | #define _RPAGE_PKEY_BIT3 0x0800000000000000UL | |
43 | #define _RPAGE_PKEY_BIT2 0x0400000000000000UL | |
44 | #define _RPAGE_PKEY_BIT1 0x0200000000000000UL | |
45 | #define _RPAGE_PKEY_BIT0 0x0100000000000000UL | |
6aa59f51 AK |
46 | |
47 | #define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ | |
48 | #define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ | |
bd0dbb73 AK |
49 | /* |
50 | * We need to mark a pmd pte invalid while splitting. We can do that by clearing | |
51 | * the _PAGE_PRESENT bit. But then that will be taken as a swap pte. In order to | |
52 | * differentiate between two use a SW field when invalidating. | |
53 | * | |
54 | * We do that temporary invalidate for regular pte entry in ptep_set_access_flags | |
55 | * | |
56 | * This is used only when _PAGE_PRESENT is cleared. | |
57 | */ | |
58 | #define _PAGE_INVALID _RPAGE_SW0 | |
6aa59f51 AK |
59 | |
60 | /* | |
61 | * Top and bottom bits of RPN which can be used by hash | |
62 | * translation mode, because we expect them to be zero | |
63 | * otherwise. | |
64 | */ | |
32789d38 AK |
65 | #define _RPAGE_RPN0 0x01000 |
66 | #define _RPAGE_RPN1 0x02000 | |
6aa59f51 AK |
67 | #define _RPAGE_RPN43 0x0080000000000000UL |
68 | #define _RPAGE_RPN42 0x0040000000000000UL | |
69 | #define _RPAGE_RPN41 0x0020000000000000UL | |
049d567a | 70 | |
2f18d533 | 71 | /* Max physical address bit as per radix table */ |
ee8b3933 | 72 | #define _RPAGE_PA_MAX 56 |
2f18d533 AK |
73 | |
74 | /* | |
75 | * Max physical address bit we will use for now. | |
76 | * | |
77 | * This is mostly a hardware limitation and for now Power9 has | |
78 | * a 51 bit limit. | |
79 | * | |
80 | * This is different from the number of physical bit required to address | |
81 | * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. | |
82 | * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum | |
83 | * number of sections we can support (SECTIONS_SHIFT). | |
84 | * | |
85 | * This is different from Radix page table limitation above and | |
86 | * should always be less than that. The limit is done such that | |
87 | * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX | |
88 | * for hash linux page table specific bits. | |
89 | * | |
90 | * In order to be compatible with future hardware generations we keep | |
91 | * some offsets and limit this for now to 53 | |
92 | */ | |
93 | #define _PAGE_PA_MAX 53 | |
94 | ||
69dfbaeb | 95 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
69dfbaeb | 96 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
ebd31197 | 97 | #define _PAGE_DEVMAP _RPAGE_SW1 /* software: ZONE_DEVICE page */ |
ebd31197 | 98 | |
2e873519 AK |
99 | /* |
100 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
101 | * Instead of fixing all of them, add an alternate define which | |
102 | * maps CI pte mapping. | |
103 | */ | |
104 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
105 | /* | |
2f18d533 AK |
106 | * We support _RPAGE_PA_MAX bit real address in pte. On the linux side |
107 | * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX | |
108 | * and every thing below PAGE_SHIFT; | |
2e873519 | 109 | */ |
2f18d533 | 110 | #define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) |
9fee28ba | 111 | #define PTE_RPN_SHIFT PAGE_SHIFT |
2e873519 AK |
112 | /* |
113 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
114 | * in here, on radix we expect them to be zero. | |
115 | */ | |
116 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
117 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
4628a645 | 118 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
2e873519 AK |
119 | /* |
120 | * user access blocked by key | |
121 | */ | |
122 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
123 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
56bec2f9 | 124 | #define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_READ | _PAGE_EXEC) |
6cc07821 | 125 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) |
2e873519 AK |
126 | /* |
127 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
128 | * pgprot changes | |
129 | */ | |
130 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
131 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
4628a645 | 132 | _PAGE_SOFT_DIRTY | _PAGE_DEVMAP) |
eb95d016 | 133 | |
3dfcb315 | 134 | /* |
2e873519 AK |
135 | * We define 2 sets of base prot bits, one for basic pages (ie, |
136 | * cacheable kernel and user pages) and one for non cacheable | |
137 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
138 | * the processor might need it for DMA coherency. | |
3dfcb315 | 139 | */ |
093d7ca2 | 140 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
2e873519 AK |
141 | #define _PAGE_BASE (_PAGE_BASE_NC) |
142 | ||
58f53462 CL |
143 | #include <asm/pgtable-masks.h> |
144 | ||
2e873519 AK |
145 | /* Permission masks used for kernel mappings */ |
146 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
6cc07821 CL |
147 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_TOLERANT) |
148 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NON_IDEMPOTENT) | |
2e873519 AK |
149 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) |
150 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
151 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
152 | ||
dd1842a2 AK |
153 | #ifndef __ASSEMBLY__ |
154 | /* | |
155 | * page table defines | |
156 | */ | |
157 | extern unsigned long __pte_index_size; | |
158 | extern unsigned long __pmd_index_size; | |
159 | extern unsigned long __pud_index_size; | |
160 | extern unsigned long __pgd_index_size; | |
fae22116 | 161 | extern unsigned long __pud_cache_index; |
dd1842a2 AK |
162 | #define PTE_INDEX_SIZE __pte_index_size |
163 | #define PMD_INDEX_SIZE __pmd_index_size | |
164 | #define PUD_INDEX_SIZE __pud_index_size | |
165 | #define PGD_INDEX_SIZE __pgd_index_size | |
738f9645 AK |
166 | /* pmd table use page table fragments */ |
167 | #define PMD_CACHE_INDEX 0 | |
fae22116 | 168 | #define PUD_CACHE_INDEX __pud_cache_index |
dd1842a2 AK |
169 | /* |
170 | * Because of use of pte fragments and THP, size of page table | |
171 | * are not always derived out of index size above. | |
172 | */ | |
173 | extern unsigned long __pte_table_size; | |
174 | extern unsigned long __pmd_table_size; | |
175 | extern unsigned long __pud_table_size; | |
176 | extern unsigned long __pgd_table_size; | |
177 | #define PTE_TABLE_SIZE __pte_table_size | |
178 | #define PMD_TABLE_SIZE __pmd_table_size | |
179 | #define PUD_TABLE_SIZE __pud_table_size | |
180 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
181 | |
182 | extern unsigned long __pmd_val_bits; | |
183 | extern unsigned long __pud_val_bits; | |
184 | extern unsigned long __pgd_val_bits; | |
185 | #define PMD_VAL_BITS __pmd_val_bits | |
186 | #define PUD_VAL_BITS __pud_val_bits | |
187 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
188 | |
189 | extern unsigned long __pte_frag_nr; | |
190 | #define PTE_FRAG_NR __pte_frag_nr | |
191 | extern unsigned long __pte_frag_size_shift; | |
192 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
193 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 | 194 | |
8a6c697b AK |
195 | extern unsigned long __pmd_frag_nr; |
196 | #define PMD_FRAG_NR __pmd_frag_nr | |
197 | extern unsigned long __pmd_frag_size_shift; | |
198 | #define PMD_FRAG_SIZE_SHIFT __pmd_frag_size_shift | |
199 | #define PMD_FRAG_SIZE (1UL << PMD_FRAG_SIZE_SHIFT) | |
200 | ||
dd1842a2 AK |
201 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) |
202 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
203 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
204 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
205 | ||
41b7a347 DA |
206 | #define MAX_PTRS_PER_PTE ((H_PTRS_PER_PTE > R_PTRS_PER_PTE) ? H_PTRS_PER_PTE : R_PTRS_PER_PTE) |
207 | #define MAX_PTRS_PER_PMD ((H_PTRS_PER_PMD > R_PTRS_PER_PMD) ? H_PTRS_PER_PMD : R_PTRS_PER_PMD) | |
208 | #define MAX_PTRS_PER_PUD ((H_PTRS_PER_PUD > R_PTRS_PER_PUD) ? H_PTRS_PER_PUD : R_PTRS_PER_PUD) | |
e72421a0 CL |
209 | #define MAX_PTRS_PER_PGD (1 << (H_PGD_INDEX_SIZE > RADIX_PGD_INDEX_SIZE ? \ |
210 | H_PGD_INDEX_SIZE : RADIX_PGD_INDEX_SIZE)) | |
211 | ||
dd1842a2 AK |
212 | /* PMD_SHIFT determines what a second-level page table entry can map */ |
213 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
214 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
215 | #define PMD_MASK (~(PMD_SIZE-1)) | |
216 | ||
217 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
218 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
219 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
220 | #define PUD_MASK (~(PUD_SIZE-1)) | |
221 | ||
222 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
223 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
224 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
225 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
226 | ||
227 | /* Bits to mask out from a PMD to get to the PTE page */ | |
228 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
229 | /* Bits to mask out from a PUD to get to the PMD page */ | |
230 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
231 | /* Bits to mask out from a PGD to get to the PUD page */ | |
2fb47060 | 232 | #define P4D_MASKED_BITS 0xc0000000000000ffUL |
d6a9996e | 233 | |
0c4d2680 AK |
234 | /* |
235 | * Used as an indicator for rcu callback functions | |
236 | */ | |
237 | enum pgtable_index { | |
238 | PTE_INDEX = 0, | |
239 | PMD_INDEX, | |
240 | PUD_INDEX, | |
241 | PGD_INDEX, | |
fadd03c6 AK |
242 | /* |
243 | * Below are used with 4k page size and hugetlb | |
244 | */ | |
245 | HTLB_16M_INDEX, | |
246 | HTLB_16G_INDEX, | |
0c4d2680 AK |
247 | }; |
248 | ||
d6a9996e AK |
249 | extern unsigned long __vmalloc_start; |
250 | extern unsigned long __vmalloc_end; | |
251 | #define VMALLOC_START __vmalloc_start | |
252 | #define VMALLOC_END __vmalloc_end | |
253 | ||
d909f910 NP |
254 | static inline unsigned int ioremap_max_order(void) |
255 | { | |
256 | if (radix_enabled()) | |
257 | return PUD_SHIFT; | |
258 | return 7 + PAGE_SHIFT; /* default from linux/vmalloc.h */ | |
259 | } | |
260 | #define IOREMAP_MAX_ORDER ioremap_max_order() | |
261 | ||
d6a9996e | 262 | extern unsigned long __kernel_virt_start; |
63ee9b2f | 263 | extern unsigned long __kernel_io_start; |
a35a3c6f | 264 | extern unsigned long __kernel_io_end; |
d6a9996e | 265 | #define KERN_VIRT_START __kernel_virt_start |
63ee9b2f | 266 | #define KERN_IO_START __kernel_io_start |
a35a3c6f AK |
267 | #define KERN_IO_END __kernel_io_end |
268 | ||
d6a9996e | 269 | extern struct page *vmemmap; |
bfa37087 | 270 | extern unsigned long pci_io_base; |
dd1842a2 | 271 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 272 | |
ab537dca | 273 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 274 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 275 | |
b32d5d7e AK |
276 | #if H_MAX_PHYSMEM_BITS > R_MAX_PHYSMEM_BITS |
277 | #define MAX_PHYSMEM_BITS H_MAX_PHYSMEM_BITS | |
278 | #else | |
279 | #define MAX_PHYSMEM_BITS R_MAX_PHYSMEM_BITS | |
280 | #endif | |
281 | ||
282 | ||
a9252aae AK |
283 | #ifdef CONFIG_PPC_64K_PAGES |
284 | #include <asm/book3s/64/pgtable-64k.h> | |
285 | #else | |
286 | #include <asm/book3s/64/pgtable-4k.h> | |
287 | #endif | |
288 | ||
3dfcb315 | 289 | #include <asm/barrier.h> |
3dfcb315 | 290 | /* |
a35a3c6f | 291 | * IO space itself carved into the PIO region (ISA and PHB IO space) and |
3dfcb315 AK |
292 | * the ioremap space |
293 | * | |
294 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
295 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
296 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
297 | */ | |
3dfcb315 AK |
298 | #define FULL_IO_SIZE 0x80000000ul |
299 | #define ISA_IO_BASE (KERN_IO_START) | |
300 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
301 | #define PHB_IO_BASE (ISA_IO_END) | |
302 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
303 | #define IOREMAP_BASE (PHB_IO_END) | |
4a45b746 | 304 | #define IOREMAP_START (ioremap_bot) |
9ccba66d CL |
305 | #define IOREMAP_END (KERN_IO_END - FIXADDR_SIZE) |
306 | #define FIXADDR_SIZE SZ_32M | |
d3e01796 | 307 | #define FIXADDR_TOP (IOREMAP_END + FIXADDR_SIZE) |
3dfcb315 | 308 | |
3dfcb315 AK |
309 | #ifndef __ASSEMBLY__ |
310 | ||
311 | /* | |
312 | * This is the default implementation of various PTE accessors, it's | |
313 | * used in all cases except Book3S with 64K pages where we have a | |
314 | * concept of sub-pages | |
315 | */ | |
316 | #ifndef __real_pte | |
317 | ||
ff31e105 | 318 | #define __real_pte(e, p, o) ((real_pte_t){(e)}) |
3dfcb315 | 319 | #define __rpte_to_pte(r) ((r).pte) |
945537df | 320 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
321 | |
322 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
323 | do { \ | |
324 | index = 0; \ | |
325 | shift = mmu_psize_defs[psize].shift; \ | |
326 | ||
327 | #define pte_iterate_hashed_end() } while(0) | |
328 | ||
329 | /* | |
330 | * We expect this to be called only for user addresses or kernel virtual | |
331 | * addresses other than the linear mapping. | |
332 | */ | |
333 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
334 | ||
335 | #endif /* __real_pte */ | |
336 | ||
ac94ac79 AK |
337 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
338 | pte_t *ptep, unsigned long clr, | |
339 | unsigned long set, int huge) | |
340 | { | |
341 | if (radix_enabled()) | |
342 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
343 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
344 | } | |
13f829a5 AK |
345 | /* |
346 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
347 | * We currently remove entries from the hashtable regardless of whether | |
348 | * the entry was young or dirty. | |
349 | * | |
350 | * We should be more intelligent about this but for the moment we override | |
351 | * these functions and force a tlb flush unconditionally | |
352 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
353 | * function for both hash and radix. | |
354 | */ | |
355 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
356 | unsigned long addr, pte_t *ptep) | |
357 | { | |
358 | unsigned long old; | |
359 | ||
66c570f5 | 360 | if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
13f829a5 AK |
361 | return 0; |
362 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
363 | return (old & _PAGE_ACCESSED) != 0; | |
364 | } | |
365 | ||
366 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
367 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
368 | ({ \ | |
3cb1aa7a | 369 | __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ |
13f829a5 AK |
370 | }) |
371 | ||
3cb1aa7a NP |
372 | /* |
373 | * On Book3S CPUs, clearing the accessed bit without a TLB flush | |
374 | * doesn't cause data corruption. [ It could cause incorrect | |
375 | * page aging and the (mistaken) reclaim of hot pages, but the | |
376 | * chance of that should be relatively low. ] | |
377 | * | |
378 | * So as a performance optimization don't flush the TLB when | |
379 | * clearing the accessed bit, it will eventually be flushed by | |
380 | * a context switch or a VM operation anyway. [ In the rare | |
381 | * event of it not getting flushed for a long time the delay | |
382 | * shouldn't really matter because there's no real memory | |
383 | * pressure for swapout to react to. ] | |
b11931e9 NP |
384 | * |
385 | * Note: this optimisation also exists in pte_needs_flush() and | |
386 | * huge_pmd_needs_flush(). | |
3cb1aa7a NP |
387 | */ |
388 | #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH | |
389 | #define ptep_clear_flush_young ptep_test_and_clear_young | |
390 | ||
391 | #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH | |
392 | #define pmdp_clear_flush_young pmdp_test_and_clear_young | |
393 | ||
d19469e8 AK |
394 | static inline int pte_write(pte_t pte) |
395 | { | |
d6379159 | 396 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE)); |
d19469e8 AK |
397 | } |
398 | ||
ca8afd40 CL |
399 | static inline int pte_read(pte_t pte) |
400 | { | |
401 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_READ)); | |
402 | } | |
403 | ||
13f829a5 AK |
404 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT |
405 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
406 | pte_t *ptep) | |
407 | { | |
d6379159 | 408 | if (pte_write(*ptep)) |
52c50ca7 | 409 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); |
13f829a5 AK |
410 | } |
411 | ||
8e581d43 | 412 | #define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT |
13f829a5 AK |
413 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, |
414 | unsigned long addr, pte_t *ptep) | |
415 | { | |
d6379159 | 416 | if (pte_write(*ptep)) |
52c50ca7 | 417 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); |
13f829a5 AK |
418 | } |
419 | ||
420 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
421 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
422 | unsigned long addr, pte_t *ptep) | |
423 | { | |
424 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
425 | return __pte(old); | |
426 | } | |
427 | ||
f4894b80 AK |
428 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL |
429 | static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, | |
430 | unsigned long addr, | |
431 | pte_t *ptep, int full) | |
432 | { | |
433 | if (full && radix_enabled()) { | |
434 | /* | |
2bf1071a NP |
435 | * We know that this is a full mm pte clear and |
436 | * hence can be sure there is no parallel set_pte. | |
f4894b80 AK |
437 | */ |
438 | return radix__ptep_get_and_clear_full(mm, addr, ptep, full); | |
439 | } | |
440 | return ptep_get_and_clear(mm, addr, ptep); | |
441 | } | |
442 | ||
443 | ||
13f829a5 AK |
444 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, |
445 | pte_t * ptep) | |
446 | { | |
447 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
448 | } | |
66c570f5 | 449 | |
66c570f5 AK |
450 | static inline int pte_dirty(pte_t pte) |
451 | { | |
452 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY)); | |
453 | } | |
454 | ||
455 | static inline int pte_young(pte_t pte) | |
456 | { | |
457 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED)); | |
458 | } | |
459 | ||
460 | static inline int pte_special(pte_t pte) | |
461 | { | |
462 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL)); | |
463 | } | |
464 | ||
daba7902 CL |
465 | static inline bool pte_exec(pte_t pte) |
466 | { | |
467 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_EXEC)); | |
468 | } | |
469 | ||
13f829a5 AK |
470 | |
471 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
472 | static inline bool pte_soft_dirty(pte_t pte) | |
473 | { | |
66c570f5 | 474 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 | 475 | } |
66c570f5 | 476 | |
13f829a5 AK |
477 | static inline pte_t pte_mksoft_dirty(pte_t pte) |
478 | { | |
1b2443a5 | 479 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
480 | } |
481 | ||
482 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
483 | { | |
1b2443a5 | 484 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY)); |
13f829a5 AK |
485 | } |
486 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
487 | ||
488 | #ifdef CONFIG_NUMA_BALANCING | |
13f829a5 AK |
489 | static inline int pte_protnone(pte_t pte) |
490 | { | |
c137a275 AK |
491 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE | _PAGE_RWX)) == |
492 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
493 | } | |
13f829a5 AK |
494 | #endif /* CONFIG_NUMA_BALANCING */ |
495 | ||
ec4abf1e AK |
496 | static inline bool pte_hw_valid(pte_t pte) |
497 | { | |
498 | return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE)) == | |
499 | cpu_to_be64(_PAGE_PRESENT | _PAGE_PTE); | |
500 | } | |
501 | ||
13f829a5 AK |
502 | static inline int pte_present(pte_t pte) |
503 | { | |
bd0dbb73 AK |
504 | /* |
505 | * A pte is considerent present if _PAGE_PRESENT is set. | |
506 | * We also need to consider the pte present which is marked | |
507 | * invalid during ptep_set_access_flags. Hence we look for _PAGE_INVALID | |
508 | * if we find _PAGE_PRESENT cleared. | |
509 | */ | |
f72a85e3 | 510 | |
ec4abf1e AK |
511 | if (pte_hw_valid(pte)) |
512 | return true; | |
513 | return (pte_raw(pte) & cpu_to_be64(_PAGE_INVALID | _PAGE_PTE)) == | |
514 | cpu_to_be64(_PAGE_INVALID | _PAGE_PTE); | |
daba7902 CL |
515 | } |
516 | ||
bca7aacf | 517 | #ifdef CONFIG_PPC_MEM_KEYS |
f2407ef3 | 518 | extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute); |
bca7aacf RP |
519 | #else |
520 | static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute) | |
521 | { | |
522 | return true; | |
523 | } | |
524 | #endif /* CONFIG_PPC_MEM_KEYS */ | |
f2407ef3 | 525 | |
1b2443a5 CL |
526 | static inline bool pte_user(pte_t pte) |
527 | { | |
528 | return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED)); | |
529 | } | |
530 | ||
f72a85e3 AK |
531 | #define pte_access_permitted pte_access_permitted |
532 | static inline bool pte_access_permitted(pte_t pte, bool write) | |
533 | { | |
f72a85e3 AK |
534 | /* |
535 | * _PAGE_READ is needed for any access and will be | |
536 | * cleared for PROT_NONE | |
537 | */ | |
1b2443a5 | 538 | if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) |
f72a85e3 AK |
539 | return false; |
540 | ||
1b2443a5 | 541 | if (write && !pte_write(pte)) |
f72a85e3 | 542 | return false; |
bca7aacf RP |
543 | |
544 | return arch_pte_access_permitted(pte_val(pte), write, 0); | |
f72a85e3 AK |
545 | } |
546 | ||
13f829a5 AK |
547 | /* |
548 | * Conversion functions: convert a page and protection to a page entry, | |
549 | * and a page entry and page directory to the page they refer to. | |
550 | * | |
551 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
552 | * long for now. | |
553 | */ | |
554 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
555 | { | |
6bb25170 NP |
556 | VM_BUG_ON(pfn >> (64 - PAGE_SHIFT)); |
557 | VM_BUG_ON((pfn << PAGE_SHIFT) & ~PTE_RPN_MASK); | |
558 | ||
379c926d | 559 | return __pte(((pte_basic_t)pfn << PAGE_SHIFT) | pgprot_val(pgprot) | _PAGE_PTE); |
13f829a5 AK |
560 | } |
561 | ||
13f829a5 AK |
562 | /* Generic modifiers for PTE bits */ |
563 | static inline pte_t pte_wrprotect(pte_t pte) | |
564 | { | |
1b2443a5 | 565 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE)); |
13f829a5 AK |
566 | } |
567 | ||
daba7902 CL |
568 | static inline pte_t pte_exprotect(pte_t pte) |
569 | { | |
1b2443a5 | 570 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC)); |
13f829a5 AK |
571 | } |
572 | ||
573 | static inline pte_t pte_mkclean(pte_t pte) | |
574 | { | |
1b2443a5 | 575 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY)); |
13f829a5 AK |
576 | } |
577 | ||
578 | static inline pte_t pte_mkold(pte_t pte) | |
579 | { | |
1b2443a5 | 580 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED)); |
13f829a5 AK |
581 | } |
582 | ||
daba7902 CL |
583 | static inline pte_t pte_mkexec(pte_t pte) |
584 | { | |
1b2443a5 | 585 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC)); |
daba7902 CL |
586 | } |
587 | ||
2f0584f3 | 588 | static inline pte_t pte_mkwrite_novma(pte_t pte) |
13f829a5 AK |
589 | { |
590 | /* | |
591 | * write implies read, hence set both | |
592 | */ | |
1b2443a5 | 593 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW)); |
13f829a5 AK |
594 | } |
595 | ||
596 | static inline pte_t pte_mkdirty(pte_t pte) | |
597 | { | |
1b2443a5 | 598 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY)); |
13f829a5 AK |
599 | } |
600 | ||
601 | static inline pte_t pte_mkyoung(pte_t pte) | |
602 | { | |
1b2443a5 | 603 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED)); |
13f829a5 AK |
604 | } |
605 | ||
606 | static inline pte_t pte_mkspecial(pte_t pte) | |
607 | { | |
1b2443a5 | 608 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL)); |
13f829a5 AK |
609 | } |
610 | ||
611 | static inline pte_t pte_mkhuge(pte_t pte) | |
612 | { | |
613 | return pte; | |
614 | } | |
615 | ||
ebd31197 OH |
616 | static inline pte_t pte_mkdevmap(pte_t pte) |
617 | { | |
1b2443a5 | 618 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP)); |
ebd31197 OH |
619 | } |
620 | ||
c9c98bc5 OH |
621 | /* |
622 | * This is potentially called with a pmd as the argument, in which case it's not | |
623 | * safe to check _PAGE_DEVMAP unless we also confirm that _PAGE_PTE is set. | |
624 | * That's because the bit we use for _PAGE_DEVMAP is not reserved for software | |
625 | * use in page directory entries (ie. non-ptes). | |
626 | */ | |
ebd31197 OH |
627 | static inline int pte_devmap(pte_t pte) |
628 | { | |
2b4a6cc9 | 629 | __be64 mask = cpu_to_be64(_PAGE_DEVMAP | _PAGE_PTE); |
c9c98bc5 OH |
630 | |
631 | return (pte_raw(pte) & mask) == mask; | |
ebd31197 OH |
632 | } |
633 | ||
13f829a5 AK |
634 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
635 | { | |
636 | /* FIXME!! check whether this need to be a conditional */ | |
1b2443a5 CL |
637 | return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) | |
638 | cpu_to_be64(pgprot_val(newprot))); | |
34fbadd8 AK |
639 | } |
640 | ||
641 | /* Encode and de-code a swap entry */ | |
642 | #define MAX_SWAPFILES_CHECK() do { \ | |
643 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
644 | /* \ | |
645 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
646 | * We filter HPTEFLAGS on set_pte. \ | |
647 | */ \ | |
03ac1b71 | 648 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & SWP_TYPE_MASK); \ |
34fbadd8 | 649 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ |
bff9beaa | 650 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_EXCLUSIVE); \ |
34fbadd8 | 651 | } while (0) |
3159f943 | 652 | |
34fbadd8 | 653 | #define SWP_TYPE_BITS 5 |
03ac1b71 DH |
654 | #define SWP_TYPE_MASK ((1UL << SWP_TYPE_BITS) - 1) |
655 | #define __swp_type(x) ((x).val & SWP_TYPE_MASK) | |
34fbadd8 AK |
656 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) |
657 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
03ac1b71 | 658 | (type) | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) |
34fbadd8 AK |
659 | /* |
660 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
661 | * swap type and offset we get from swap and convert that to pte to find a | |
662 | * matching pte in linux page table. | |
663 | * Clear bits not found in swap entries here. | |
664 | */ | |
665 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
666 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
a0820ff3 AK |
667 | #define __pmd_to_swp_entry(pmd) (__pte_to_swp_entry(pmd_pte(pmd))) |
668 | #define __swp_entry_to_pmd(x) (pte_pmd(__swp_entry_to_pte(x))) | |
34fbadd8 AK |
669 | |
670 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
bff9beaa | 671 | #define _PAGE_SWP_SOFT_DIRTY _PAGE_SOFT_DIRTY |
34fbadd8 AK |
672 | #else |
673 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
674 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
675 | ||
bff9beaa DH |
676 | #define _PAGE_SWP_EXCLUSIVE _PAGE_NON_IDEMPOTENT |
677 | ||
34fbadd8 AK |
678 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
679 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
680 | { | |
1b2443a5 | 681 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 682 | } |
66c570f5 | 683 | |
34fbadd8 AK |
684 | static inline bool pte_swp_soft_dirty(pte_t pte) |
685 | { | |
66c570f5 | 686 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 | 687 | } |
66c570f5 | 688 | |
34fbadd8 AK |
689 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) |
690 | { | |
1b2443a5 | 691 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY)); |
34fbadd8 AK |
692 | } |
693 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
694 | ||
bff9beaa DH |
695 | static inline pte_t pte_swp_mkexclusive(pte_t pte) |
696 | { | |
697 | return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
698 | } | |
699 | ||
700 | static inline int pte_swp_exclusive(pte_t pte) | |
701 | { | |
702 | return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_EXCLUSIVE)); | |
703 | } | |
704 | ||
705 | static inline pte_t pte_swp_clear_exclusive(pte_t pte) | |
706 | { | |
707 | return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_EXCLUSIVE)); | |
708 | } | |
709 | ||
34fbadd8 AK |
710 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) |
711 | { | |
712 | /* | |
713 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
714 | */ | |
715 | if (access & ~ptev) | |
716 | return false; | |
717 | /* | |
718 | * This check for access to privilege space | |
719 | */ | |
720 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
721 | return false; | |
722 | ||
723 | return true; | |
724 | } | |
ac94ac79 AK |
725 | /* |
726 | * Generic functions with hash/radix callbacks | |
727 | */ | |
728 | ||
e4c1112c | 729 | static inline void __ptep_set_access_flags(struct vm_area_struct *vma, |
b3603e17 | 730 | pte_t *ptep, pte_t entry, |
e4c1112c AK |
731 | unsigned long address, |
732 | int psize) | |
ac94ac79 AK |
733 | { |
734 | if (radix_enabled()) | |
e4c1112c AK |
735 | return radix__ptep_set_access_flags(vma, ptep, entry, |
736 | address, psize); | |
ac94ac79 AK |
737 | return hash__ptep_set_access_flags(ptep, entry); |
738 | } | |
739 | ||
740 | #define __HAVE_ARCH_PTE_SAME | |
741 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
742 | { | |
743 | if (radix_enabled()) | |
744 | return radix__pte_same(pte_a, pte_b); | |
745 | return hash__pte_same(pte_a, pte_b); | |
746 | } | |
747 | ||
748 | static inline int pte_none(pte_t pte) | |
749 | { | |
750 | if (radix_enabled()) | |
751 | return radix__pte_none(pte); | |
752 | return hash__pte_none(pte); | |
753 | } | |
754 | ||
755 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
756 | pte_t *ptep, pte_t pte, int percpu) | |
757 | { | |
379c926d AK |
758 | |
759 | VM_WARN_ON(!(pte_raw(pte) & cpu_to_be64(_PAGE_PTE))); | |
760 | /* | |
761 | * Keep the _PAGE_PTE added till we are sure we handle _PAGE_PTE | |
762 | * in all the callers. | |
763 | */ | |
764 | pte = __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE)); | |
765 | ||
ac94ac79 AK |
766 | if (radix_enabled()) |
767 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
768 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
769 | } | |
34fbadd8 | 770 | |
12564485 SA |
771 | #define _PAGE_CACHE_CTL (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
772 | ||
13f829a5 AK |
773 | #define pgprot_noncached pgprot_noncached |
774 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
775 | { | |
776 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
777 | _PAGE_NON_IDEMPOTENT); | |
778 | } | |
779 | ||
780 | #define pgprot_noncached_wc pgprot_noncached_wc | |
781 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
782 | { | |
783 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
784 | _PAGE_TOLERANT); | |
785 | } | |
786 | ||
787 | #define pgprot_cached pgprot_cached | |
788 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
789 | { | |
790 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
791 | } | |
792 | ||
793 | #define pgprot_writecombine pgprot_writecombine | |
794 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
795 | { | |
796 | return pgprot_noncached_wc(prot); | |
797 | } | |
798 | /* | |
799 | * check a pte mapping have cache inhibited property | |
800 | */ | |
801 | static inline bool pte_ci(pte_t pte) | |
802 | { | |
1b2443a5 | 803 | __be64 pte_v = pte_raw(pte); |
13f829a5 | 804 | |
1b2443a5 CL |
805 | if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) || |
806 | ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT))) | |
13f829a5 AK |
807 | return true; |
808 | return false; | |
809 | } | |
810 | ||
f281b5d5 AK |
811 | static inline void pmd_clear(pmd_t *pmdp) |
812 | { | |
392b4669 AK |
813 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
814 | /* | |
815 | * Don't use this if we can possibly have a hash page table | |
816 | * entry mapping this. | |
817 | */ | |
818 | WARN_ON((pmd_val(*pmdp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
819 | } | |
f281b5d5 AK |
820 | *pmdp = __pmd(0); |
821 | } | |
822 | ||
66c570f5 AK |
823 | static inline int pmd_none(pmd_t pmd) |
824 | { | |
825 | return !pmd_raw(pmd); | |
826 | } | |
827 | ||
828 | static inline int pmd_present(pmd_t pmd) | |
829 | { | |
da7ad366 AK |
830 | /* |
831 | * A pmd is considerent present if _PAGE_PRESENT is set. | |
832 | * We also need to consider the pmd present which is marked | |
833 | * invalid during a split. Hence we look for _PAGE_INVALID | |
834 | * if we find _PAGE_PRESENT cleared. | |
835 | */ | |
836 | if (pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) | |
837 | return true; | |
66c570f5 | 838 | |
da7ad366 | 839 | return false; |
66c570f5 | 840 | } |
3dfcb315 | 841 | |
33258a1d NP |
842 | static inline int pmd_is_serializing(pmd_t pmd) |
843 | { | |
844 | /* | |
845 | * If the pmd is undergoing a split, the _PAGE_PRESENT bit is clear | |
846 | * and _PAGE_INVALID is set (see pmd_present, pmdp_invalidate). | |
847 | * | |
848 | * This condition may also occur when flushing a pmd while flushing | |
849 | * it (see ptep_modify_prot_start), so callers must ensure this | |
850 | * case is fine as well. | |
851 | */ | |
852 | if ((pmd_raw(pmd) & cpu_to_be64(_PAGE_PRESENT | _PAGE_INVALID)) == | |
853 | cpu_to_be64(_PAGE_INVALID)) | |
854 | return true; | |
855 | ||
856 | return false; | |
857 | } | |
858 | ||
ac94ac79 AK |
859 | static inline int pmd_bad(pmd_t pmd) |
860 | { | |
861 | if (radix_enabled()) | |
862 | return radix__pmd_bad(pmd); | |
863 | return hash__pmd_bad(pmd); | |
864 | } | |
865 | ||
f281b5d5 AK |
866 | static inline void pud_clear(pud_t *pudp) |
867 | { | |
392b4669 AK |
868 | if (IS_ENABLED(CONFIG_DEBUG_VM) && !radix_enabled()) { |
869 | /* | |
870 | * Don't use this if we can possibly have a hash page table | |
871 | * entry mapping this. | |
872 | */ | |
873 | WARN_ON((pud_val(*pudp) & (H_PAGE_HASHPTE | _PAGE_PTE)) == (H_PAGE_HASHPTE | _PAGE_PTE)); | |
874 | } | |
f281b5d5 AK |
875 | *pudp = __pud(0); |
876 | } | |
877 | ||
66c570f5 AK |
878 | static inline int pud_none(pud_t pud) |
879 | { | |
880 | return !pud_raw(pud); | |
881 | } | |
882 | ||
883 | static inline int pud_present(pud_t pud) | |
884 | { | |
a5800762 | 885 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 886 | } |
3dfcb315 AK |
887 | |
888 | extern struct page *pud_page(pud_t pud); | |
371352ca | 889 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
890 | static inline pte_t pud_pte(pud_t pud) |
891 | { | |
66c570f5 | 892 | return __pte_raw(pud_raw(pud)); |
3dfcb315 AK |
893 | } |
894 | ||
895 | static inline pud_t pte_pud(pte_t pte) | |
896 | { | |
66c570f5 | 897 | return __pud_raw(pte_raw(pte)); |
3dfcb315 | 898 | } |
27af67f3 AK |
899 | |
900 | static inline pte_t *pudp_ptep(pud_t *pud) | |
901 | { | |
902 | return (pte_t *)pud; | |
903 | } | |
904 | ||
905 | #define pud_pfn(pud) pte_pfn(pud_pte(pud)) | |
906 | #define pud_dirty(pud) pte_dirty(pud_pte(pud)) | |
907 | #define pud_young(pud) pte_young(pud_pte(pud)) | |
908 | #define pud_mkold(pud) pte_pud(pte_mkold(pud_pte(pud))) | |
909 | #define pud_wrprotect(pud) pte_pud(pte_wrprotect(pud_pte(pud))) | |
910 | #define pud_mkdirty(pud) pte_pud(pte_mkdirty(pud_pte(pud))) | |
911 | #define pud_mkclean(pud) pte_pud(pte_mkclean(pud_pte(pud))) | |
912 | #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud))) | |
f441ff73 | 913 | #define pud_mkwrite(pud) pte_pud(pte_mkwrite_novma(pud_pte(pud))) |
3dfcb315 | 914 | #define pud_write(pud) pte_write(pud_pte(pud)) |
ac94ac79 | 915 | |
27af67f3 AK |
916 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY |
917 | #define pud_soft_dirty(pmd) pte_soft_dirty(pud_pte(pud)) | |
918 | #define pud_mksoft_dirty(pmd) pte_pud(pte_mksoft_dirty(pud_pte(pud))) | |
919 | #define pud_clear_soft_dirty(pmd) pte_pud(pte_clear_soft_dirty(pud_pte(pud))) | |
920 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
921 | ||
ac94ac79 AK |
922 | static inline int pud_bad(pud_t pud) |
923 | { | |
924 | if (radix_enabled()) | |
925 | return radix__pud_bad(pud); | |
926 | return hash__pud_bad(pud); | |
927 | } | |
928 | ||
f72a85e3 AK |
929 | #define pud_access_permitted pud_access_permitted |
930 | static inline bool pud_access_permitted(pud_t pud, bool write) | |
931 | { | |
932 | return pte_access_permitted(pud_pte(pud), write); | |
933 | } | |
ac94ac79 | 934 | |
2fb47060 MR |
935 | #define __p4d_raw(x) ((p4d_t) { __pgd_raw(x) }) |
936 | static inline __be64 p4d_raw(p4d_t x) | |
937 | { | |
938 | return pgd_raw(x.pgd); | |
939 | } | |
940 | ||
941 | #define p4d_write(p4d) pte_write(p4d_pte(p4d)) | |
3dfcb315 | 942 | |
2fb47060 | 943 | static inline void p4d_clear(p4d_t *p4dp) |
368ced78 | 944 | { |
2fb47060 | 945 | *p4dp = __p4d(0); |
368ced78 AK |
946 | } |
947 | ||
2fb47060 | 948 | static inline int p4d_none(p4d_t p4d) |
66c570f5 | 949 | { |
2fb47060 | 950 | return !p4d_raw(p4d); |
66c570f5 AK |
951 | } |
952 | ||
2fb47060 | 953 | static inline int p4d_present(p4d_t p4d) |
66c570f5 | 954 | { |
2fb47060 | 955 | return !!(p4d_raw(p4d) & cpu_to_be64(_PAGE_PRESENT)); |
66c570f5 | 956 | } |
368ced78 | 957 | |
2fb47060 | 958 | static inline pte_t p4d_pte(p4d_t p4d) |
368ced78 | 959 | { |
2fb47060 | 960 | return __pte_raw(p4d_raw(p4d)); |
368ced78 AK |
961 | } |
962 | ||
2fb47060 | 963 | static inline p4d_t pte_p4d(pte_t pte) |
368ced78 | 964 | { |
2fb47060 | 965 | return __p4d_raw(pte_raw(pte)); |
368ced78 AK |
966 | } |
967 | ||
2fb47060 | 968 | static inline int p4d_bad(p4d_t p4d) |
ac94ac79 AK |
969 | { |
970 | if (radix_enabled()) | |
2fb47060 MR |
971 | return radix__p4d_bad(p4d); |
972 | return hash__p4d_bad(p4d); | |
ac94ac79 AK |
973 | } |
974 | ||
2fb47060 MR |
975 | #define p4d_access_permitted p4d_access_permitted |
976 | static inline bool p4d_access_permitted(p4d_t p4d, bool write) | |
f72a85e3 | 977 | { |
2fb47060 | 978 | return pte_access_permitted(p4d_pte(p4d), write); |
f72a85e3 AK |
979 | } |
980 | ||
2fb47060 | 981 | extern struct page *p4d_page(p4d_t p4d); |
368ced78 | 982 | |
aba480e1 AK |
983 | /* Pointers in the page table tree are physical addresses */ |
984 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
985 | ||
dc4875f0 AK |
986 | static inline pud_t *p4d_pgtable(p4d_t p4d) |
987 | { | |
988 | return (pud_t *)__va(p4d_val(p4d) & ~P4D_MASKED_BITS); | |
989 | } | |
aba480e1 | 990 | |
9cf6fa24 AK |
991 | static inline pmd_t *pud_pgtable(pud_t pud) |
992 | { | |
993 | return (pmd_t *)__va(pud_val(pud) & ~PUD_MASKED_BITS); | |
994 | } | |
995 | ||
3dfcb315 AK |
996 | #define pmd_ERROR(e) \ |
997 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
998 | #define pud_ERROR(e) \ |
999 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
1000 | #define pgd_ERROR(e) \ |
1001 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
1002 | ||
c766ee72 | 1003 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot) |
7207f436 | 1004 | { |
d9225ad9 AK |
1005 | if (radix_enabled()) { |
1006 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
1007 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
1008 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
1009 | #endif | |
c766ee72 | 1010 | return radix__map_kernel_page(ea, pa, prot, PAGE_SIZE); |
d9225ad9 | 1011 | } |
c766ee72 | 1012 | return hash__map_kernel_page(ea, pa, prot); |
7207f436 | 1013 | } |
31a14fae | 1014 | |
aec98260 CL |
1015 | void unmap_kernel_page(unsigned long va); |
1016 | ||
31a14fae AK |
1017 | static inline int __meminit vmemmap_create_mapping(unsigned long start, |
1018 | unsigned long page_size, | |
1019 | unsigned long phys) | |
7207f436 | 1020 | { |
d9225ad9 AK |
1021 | if (radix_enabled()) |
1022 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 1023 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 1024 | } |
31a14fae AK |
1025 | |
1026 | #ifdef CONFIG_MEMORY_HOTPLUG | |
1027 | static inline void vmemmap_remove_mapping(unsigned long start, | |
1028 | unsigned long page_size) | |
7207f436 | 1029 | { |
d9225ad9 AK |
1030 | if (radix_enabled()) |
1031 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 1032 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 1033 | } |
31a14fae | 1034 | #endif |
3dfcb315 | 1035 | |
a5edf981 | 1036 | #if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KFENCE) |
4f703e7f JS |
1037 | static inline void __kernel_map_pages(struct page *page, int numpages, int enable) |
1038 | { | |
1039 | if (radix_enabled()) | |
1040 | radix__kernel_map_pages(page, numpages, enable); | |
1041 | else | |
1042 | hash__kernel_map_pages(page, numpages, enable); | |
1043 | } | |
1044 | #endif | |
1045 | ||
3dfcb315 AK |
1046 | static inline pte_t pmd_pte(pmd_t pmd) |
1047 | { | |
66c570f5 | 1048 | return __pte_raw(pmd_raw(pmd)); |
3dfcb315 AK |
1049 | } |
1050 | ||
1051 | static inline pmd_t pte_pmd(pte_t pte) | |
1052 | { | |
66c570f5 | 1053 | return __pmd_raw(pte_raw(pte)); |
3dfcb315 AK |
1054 | } |
1055 | ||
1056 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
1057 | { | |
1058 | return (pte_t *)pmd; | |
1059 | } | |
3dfcb315 AK |
1060 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
1061 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
1062 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
1063 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
1064 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
1065 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 1066 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 | 1067 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
2f0584f3 | 1068 | #define pmd_mkwrite_novma(pmd) pte_pmd(pte_mkwrite_novma(pmd_pte(pmd))) |
7207f436 LD |
1069 | |
1070 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
1071 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
1072 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
1073 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
a0820ff3 AK |
1074 | |
1075 | #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION | |
1076 | #define pmd_swp_mksoft_dirty(pmd) pte_pmd(pte_swp_mksoft_dirty(pmd_pte(pmd))) | |
1077 | #define pmd_swp_soft_dirty(pmd) pte_swp_soft_dirty(pmd_pte(pmd)) | |
1078 | #define pmd_swp_clear_soft_dirty(pmd) pte_pmd(pte_swp_clear_soft_dirty(pmd_pte(pmd))) | |
1079 | #endif | |
7207f436 LD |
1080 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ |
1081 | ||
1ca72129 AK |
1082 | #ifdef CONFIG_NUMA_BALANCING |
1083 | static inline int pmd_protnone(pmd_t pmd) | |
1084 | { | |
1085 | return pte_protnone(pmd_pte(pmd)); | |
1086 | } | |
1087 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 | 1088 | |
3dfcb315 AK |
1089 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) |
1090 | ||
f72a85e3 AK |
1091 | #define pmd_access_permitted pmd_access_permitted |
1092 | static inline bool pmd_access_permitted(pmd_t pmd, bool write) | |
1093 | { | |
33258a1d NP |
1094 | /* |
1095 | * pmdp_invalidate sets this combination (which is not caught by | |
1096 | * !pte_present() check in pte_access_permitted), to prevent | |
1097 | * lock-free lookups, as part of the serialize_against_pte_lookup() | |
1098 | * synchronisation. | |
1099 | * | |
1100 | * This also catches the case where the PTE's hardware PRESENT bit is | |
1101 | * cleared while TLB is flushed, which is suboptimal but should not | |
1102 | * be frequent. | |
1103 | */ | |
1104 | if (pmd_is_serializing(pmd)) | |
1105 | return false; | |
1106 | ||
f72a85e3 AK |
1107 | return pte_access_permitted(pmd_pte(pmd), write); |
1108 | } | |
1109 | ||
6a1ea362 AK |
1110 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
1111 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
27af67f3 | 1112 | extern pud_t pfn_pud(unsigned long pfn, pgprot_t pgprot); |
6a1ea362 AK |
1113 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); |
1114 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
1115 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
1116 | pmd_t *pmdp, pmd_t pmd); | |
27af67f3 AK |
1117 | extern void set_pud_at(struct mm_struct *mm, unsigned long addr, |
1118 | pud_t *pudp, pud_t pud); | |
1119 | ||
18594f9b NP |
1120 | static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, |
1121 | unsigned long addr, pmd_t *pmd) | |
1122 | { | |
1123 | } | |
1124 | ||
27af67f3 AK |
1125 | static inline void update_mmu_cache_pud(struct vm_area_struct *vma, |
1126 | unsigned long addr, pud_t *pud) | |
1127 | { | |
1128 | } | |
1129 | ||
3df33f12 AK |
1130 | extern int hash__has_transparent_hugepage(void); |
1131 | static inline int has_transparent_hugepage(void) | |
1132 | { | |
bde3eb62 AK |
1133 | if (radix_enabled()) |
1134 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
1135 | return hash__has_transparent_hugepage(); |
1136 | } | |
c04a5880 | 1137 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 1138 | |
27af67f3 AK |
1139 | static inline int has_transparent_pud_hugepage(void) |
1140 | { | |
1141 | if (radix_enabled()) | |
1142 | return radix__has_transparent_pud_hugepage(); | |
1143 | return 0; | |
1144 | } | |
1145 | #define has_transparent_pud_hugepage has_transparent_pud_hugepage | |
1146 | ||
3df33f12 AK |
1147 | static inline unsigned long |
1148 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
1149 | unsigned long clr, unsigned long set) | |
3dfcb315 | 1150 | { |
bde3eb62 AK |
1151 | if (radix_enabled()) |
1152 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
1153 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
1154 | } | |
1155 | ||
27af67f3 AK |
1156 | static inline unsigned long |
1157 | pud_hugepage_update(struct mm_struct *mm, unsigned long addr, pud_t *pudp, | |
1158 | unsigned long clr, unsigned long set) | |
1159 | { | |
1160 | if (radix_enabled()) | |
1161 | return radix__pud_hugepage_update(mm, addr, pudp, clr, set); | |
1162 | BUG(); | |
1163 | return pud_val(*pudp); | |
1164 | } | |
1165 | ||
8890e033 AK |
1166 | /* |
1167 | * returns true for pmd migration entries, THP, devmap, hugetlb | |
1168 | * But compile time dependent on THP config | |
1169 | */ | |
3df33f12 AK |
1170 | static inline int pmd_large(pmd_t pmd) |
1171 | { | |
66c570f5 | 1172 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); |
3df33f12 AK |
1173 | } |
1174 | ||
27af67f3 AK |
1175 | static inline int pud_large(pud_t pud) |
1176 | { | |
1177 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); | |
1178 | } | |
1179 | ||
3df33f12 AK |
1180 | /* |
1181 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
1182 | * the below will work for radix too | |
1183 | */ | |
1184 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
1185 | unsigned long addr, pmd_t *pmdp) | |
1186 | { | |
1187 | unsigned long old; | |
1188 | ||
66c570f5 | 1189 | if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) |
3df33f12 AK |
1190 | return 0; |
1191 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
1192 | return ((old & _PAGE_ACCESSED) != 0); | |
1193 | } | |
1194 | ||
27af67f3 AK |
1195 | static inline int __pudp_test_and_clear_young(struct mm_struct *mm, |
1196 | unsigned long addr, pud_t *pudp) | |
1197 | { | |
1198 | unsigned long old; | |
1199 | ||
1200 | if ((pud_raw(*pudp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
1201 | return 0; | |
1202 | old = pud_hugepage_update(mm, addr, pudp, _PAGE_ACCESSED, 0); | |
1203 | return ((old & _PAGE_ACCESSED) != 0); | |
1204 | } | |
1205 | ||
3df33f12 AK |
1206 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT |
1207 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1208 | pmd_t *pmdp) | |
1209 | { | |
d6379159 | 1210 | if (pmd_write(*pmdp)) |
52c50ca7 | 1211 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); |
3dfcb315 AK |
1212 | } |
1213 | ||
27af67f3 AK |
1214 | #define __HAVE_ARCH_PUDP_SET_WRPROTECT |
1215 | static inline void pudp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
1216 | pud_t *pudp) | |
1217 | { | |
1218 | if (pud_write(*pudp)) | |
1219 | pud_hugepage_update(mm, addr, pudp, _PAGE_WRITE, 0); | |
1220 | } | |
1221 | ||
8890e033 AK |
1222 | /* |
1223 | * Only returns true for a THP. False for pmd migration entry. | |
1224 | * We also need to return true when we come across a pte that | |
1225 | * in between a thp split. While splitting THP, we mark the pmd | |
1226 | * invalid (pmdp_invalidate()) before we set it with pte page | |
1227 | * address. A pmd_trans_huge() check against a pmd entry during that time | |
1228 | * should return true. | |
1229 | * We should not call this on a hugetlb entry. We should check for HugeTLB | |
1230 | * entry using vma->vm_flags | |
ee65728e | 1231 | * The page table walk rule is explained in Documentation/mm/transhuge.rst |
8890e033 | 1232 | */ |
ab624762 AK |
1233 | static inline int pmd_trans_huge(pmd_t pmd) |
1234 | { | |
8890e033 AK |
1235 | if (!pmd_present(pmd)) |
1236 | return false; | |
1237 | ||
ab624762 AK |
1238 | if (radix_enabled()) |
1239 | return radix__pmd_trans_huge(pmd); | |
1240 | return hash__pmd_trans_huge(pmd); | |
1241 | } | |
1242 | ||
27af67f3 AK |
1243 | static inline int pud_trans_huge(pud_t pud) |
1244 | { | |
1245 | if (!pud_present(pud)) | |
1246 | return false; | |
1247 | ||
1248 | if (radix_enabled()) | |
1249 | return radix__pud_trans_huge(pud); | |
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | ||
ab624762 AK |
1254 | #define __HAVE_ARCH_PMD_SAME |
1255 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
1256 | { | |
1257 | if (radix_enabled()) | |
1258 | return radix__pmd_same(pmd_a, pmd_b); | |
1259 | return hash__pmd_same(pmd_a, pmd_b); | |
1260 | } | |
1261 | ||
27af67f3 AK |
1262 | #define pud_same pud_same |
1263 | static inline int pud_same(pud_t pud_a, pud_t pud_b) | |
1264 | { | |
1265 | if (radix_enabled()) | |
1266 | return radix__pud_same(pud_a, pud_b); | |
1267 | return hash__pud_same(pud_a, pud_b); | |
1268 | } | |
1269 | ||
1270 | ||
53f45ecc | 1271 | static inline pmd_t __pmd_mkhuge(pmd_t pmd) |
3dfcb315 | 1272 | { |
ab624762 AK |
1273 | if (radix_enabled()) |
1274 | return radix__pmd_mkhuge(pmd); | |
1275 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
1276 | } |
1277 | ||
27af67f3 AK |
1278 | static inline pud_t __pud_mkhuge(pud_t pud) |
1279 | { | |
1280 | if (radix_enabled()) | |
1281 | return radix__pud_mkhuge(pud); | |
1282 | BUG(); | |
1283 | return pud; | |
1284 | } | |
1285 | ||
53f45ecc AK |
1286 | /* |
1287 | * pfn_pmd return a pmd_t that can be used as pmd pte entry. | |
1288 | */ | |
1289 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
1290 | { | |
1291 | #ifdef CONFIG_DEBUG_VM | |
1292 | if (radix_enabled()) | |
1293 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1294 | else | |
1295 | WARN_ON((pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)) != | |
1296 | cpu_to_be64(_PAGE_PTE | H_PAGE_THP_HUGE)); | |
1297 | #endif | |
1298 | return pmd; | |
1299 | } | |
1300 | ||
27af67f3 AK |
1301 | static inline pud_t pud_mkhuge(pud_t pud) |
1302 | { | |
1303 | #ifdef CONFIG_DEBUG_VM | |
1304 | if (radix_enabled()) | |
1305 | WARN_ON((pud_raw(pud) & cpu_to_be64(_PAGE_PTE)) == 0); | |
1306 | else | |
1307 | WARN_ON(1); | |
1308 | #endif | |
1309 | return pud; | |
1310 | } | |
1311 | ||
1312 | ||
3dfcb315 AK |
1313 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
1314 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
1315 | unsigned long address, pmd_t *pmdp, | |
1316 | pmd_t entry, int dirty); | |
27af67f3 AK |
1317 | #define __HAVE_ARCH_PUDP_SET_ACCESS_FLAGS |
1318 | extern int pudp_set_access_flags(struct vm_area_struct *vma, | |
1319 | unsigned long address, pud_t *pudp, | |
1320 | pud_t entry, int dirty); | |
3dfcb315 | 1321 | |
3dfcb315 AK |
1322 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
1323 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
1324 | unsigned long address, pmd_t *pmdp); | |
27af67f3 AK |
1325 | #define __HAVE_ARCH_PUDP_TEST_AND_CLEAR_YOUNG |
1326 | extern int pudp_test_and_clear_young(struct vm_area_struct *vma, | |
1327 | unsigned long address, pud_t *pudp); | |
1328 | ||
3dfcb315 AK |
1329 | |
1330 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
1331 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
1332 | unsigned long addr, pmd_t *pmdp) | |
1333 | { | |
bde3eb62 AK |
1334 | if (radix_enabled()) |
1335 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
1336 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
1337 | } | |
3dfcb315 | 1338 | |
27af67f3 AK |
1339 | #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR |
1340 | static inline pud_t pudp_huge_get_and_clear(struct mm_struct *mm, | |
1341 | unsigned long addr, pud_t *pudp) | |
1342 | { | |
1343 | if (radix_enabled()) | |
1344 | return radix__pudp_huge_get_and_clear(mm, addr, pudp); | |
1345 | BUG(); | |
1346 | return *pudp; | |
1347 | } | |
1348 | ||
3df33f12 AK |
1349 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
1350 | unsigned long address, pmd_t *pmdp) | |
1351 | { | |
bde3eb62 AK |
1352 | if (radix_enabled()) |
1353 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
1354 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
1355 | } | |
3dfcb315 AK |
1356 | #define pmdp_collapse_flush pmdp_collapse_flush |
1357 | ||
75358ea3 AK |
1358 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL |
1359 | pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1360 | unsigned long addr, | |
1361 | pmd_t *pmdp, int full); | |
1362 | ||
27af67f3 AK |
1363 | #define __HAVE_ARCH_PUDP_HUGE_GET_AND_CLEAR_FULL |
1364 | pud_t pudp_huge_get_and_clear_full(struct vm_area_struct *vma, | |
1365 | unsigned long addr, | |
1366 | pud_t *pudp, int full); | |
1367 | ||
3dfcb315 | 1368 | #define __HAVE_ARCH_PGTABLE_DEPOSIT |
3df33f12 AK |
1369 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
1370 | pmd_t *pmdp, pgtable_t pgtable) | |
1371 | { | |
bde3eb62 AK |
1372 | if (radix_enabled()) |
1373 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
1374 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
1375 | } | |
1376 | ||
3dfcb315 | 1377 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
1378 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
1379 | pmd_t *pmdp) | |
1380 | { | |
bde3eb62 AK |
1381 | if (radix_enabled()) |
1382 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
1383 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
1384 | } | |
3dfcb315 AK |
1385 | |
1386 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
8cc931e0 AK |
1387 | extern pmd_t pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, |
1388 | pmd_t *pmdp); | |
3dfcb315 AK |
1389 | |
1390 | #define pmd_move_must_withdraw pmd_move_must_withdraw | |
1391 | struct spinlock; | |
579b9239 AK |
1392 | extern int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, |
1393 | struct spinlock *old_pmd_ptl, | |
1394 | struct vm_area_struct *vma); | |
1395 | /* | |
1396 | * Hash translation mode use the deposited table to store hash pte | |
1397 | * slot information. | |
1398 | */ | |
953c66c2 AK |
1399 | #define arch_needs_pgtable_deposit arch_needs_pgtable_deposit |
1400 | static inline bool arch_needs_pgtable_deposit(void) | |
1401 | { | |
1402 | if (radix_enabled()) | |
1403 | return false; | |
1404 | return true; | |
1405 | } | |
fa4531f7 | 1406 | extern void serialize_against_pte_lookup(struct mm_struct *mm); |
953c66c2 | 1407 | |
ebd31197 OH |
1408 | |
1409 | static inline pmd_t pmd_mkdevmap(pmd_t pmd) | |
1410 | { | |
36b78402 AK |
1411 | if (radix_enabled()) |
1412 | return radix__pmd_mkdevmap(pmd); | |
1413 | return hash__pmd_mkdevmap(pmd); | |
ebd31197 OH |
1414 | } |
1415 | ||
27af67f3 AK |
1416 | static inline pud_t pud_mkdevmap(pud_t pud) |
1417 | { | |
1418 | if (radix_enabled()) | |
1419 | return radix__pud_mkdevmap(pud); | |
1420 | BUG(); | |
1421 | return pud; | |
1422 | } | |
1423 | ||
ebd31197 OH |
1424 | static inline int pmd_devmap(pmd_t pmd) |
1425 | { | |
1426 | return pte_devmap(pmd_pte(pmd)); | |
1427 | } | |
1428 | ||
1429 | static inline int pud_devmap(pud_t pud) | |
1430 | { | |
27af67f3 | 1431 | return pte_devmap(pud_pte(pud)); |
ebd31197 OH |
1432 | } |
1433 | ||
1434 | static inline int pgd_devmap(pgd_t pgd) | |
1435 | { | |
1436 | return 0; | |
1437 | } | |
6a1ea362 | 1438 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
ebd31197 | 1439 | |
5b323367 AK |
1440 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1441 | pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *); | |
1442 | void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long, | |
1443 | pte_t *, pte_t, pte_t); | |
1444 | ||
1445 | /* | |
1446 | * Returns true for a R -> RW upgrade of pte | |
1447 | */ | |
1448 | static inline bool is_pte_rw_upgrade(unsigned long old_val, unsigned long new_val) | |
1449 | { | |
1450 | if (!(old_val & _PAGE_READ)) | |
1451 | return false; | |
1452 | ||
1453 | if ((!(old_val & _PAGE_WRITE)) && (new_val & _PAGE_WRITE)) | |
1454 | return true; | |
1455 | ||
1456 | return false; | |
1457 | } | |
029d9252 | 1458 | |
d6eacedd AK |
1459 | /* |
1460 | * Like pmd_huge() and pmd_large(), but works regardless of config options | |
1461 | */ | |
1462 | #define pmd_is_leaf pmd_is_leaf | |
070434b1 | 1463 | #define pmd_leaf pmd_is_leaf |
d6eacedd AK |
1464 | static inline bool pmd_is_leaf(pmd_t pmd) |
1465 | { | |
1466 | return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE)); | |
1467 | } | |
1468 | ||
1469 | #define pud_is_leaf pud_is_leaf | |
070434b1 | 1470 | #define pud_leaf pud_is_leaf |
d6eacedd AK |
1471 | static inline bool pud_is_leaf(pud_t pud) |
1472 | { | |
1473 | return !!(pud_raw(pud) & cpu_to_be64(_PAGE_PTE)); | |
1474 | } | |
1475 | ||
3dfcb315 AK |
1476 | #endif /* __ASSEMBLY__ */ |
1477 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |