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mm: move vma_is_anonymous check within pmd_move_must_withdraw
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
CommitLineData
3dfcb315
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519
AK		 3
4/*
5 * Common bits between hash and Radix page table
6 */
7#define _PAGE_BIT_SWAP_TYPE 0
8
6b8cb66a
CL		 9#define _PAGE_RO 0
10
2e873519
AK		 11#define _PAGE_EXEC 0x00001 /* execute permission */
12#define _PAGE_WRITE 0x00002 /* write access allowed */
13#define _PAGE_READ 0x00004 /* read access allowed */
14#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
15#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
16#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
17#define _PAGE_SAO 0x00010 /* Strong access order */
18#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
19#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
20#define _PAGE_DIRTY 0x00080 /* C: page changed */
21#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 22/*
2e873519 23 * Software bits
3dfcb315 24 */
69dfbaeb
AK		 25#define _RPAGE_SW0 0x2000000000000000UL
26#define _RPAGE_SW1 0x00800
27#define _RPAGE_SW2 0x00400
28#define _RPAGE_SW3 0x00200
2e873519 29#ifdef CONFIG_MEM_SOFT_DIRTY
69dfbaeb 30#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
2e873519
AK		 31#else
32#define _PAGE_SOFT_DIRTY 0x00000
33#endif
69dfbaeb 34#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
2e873519
AK		 35
36
37#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
38#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
39/*
40 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
41 * Instead of fixing all of them, add an alternate define which
42 * maps CI pte mapping.
43 */
44#define _PAGE_NO_CACHE _PAGE_TOLERANT
45/*
46 * We support 57 bit real address in pte. Clear everything above 57, and
47 * every thing below PAGE_SHIFT;
48 */
49#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
50/*
51 * set of bits not changed in pmd_modify. Even though we have hash specific bits
52 * in here, on radix we expect them to be zero.
53 */
54#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
55 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
56 _PAGE_SOFT_DIRTY)
57/*
58 * user access blocked by key
59 */
60#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
61#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
62#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
63 _PAGE_RW | _PAGE_EXEC)
64/*
65 * No page size encoding in the linux PTE
66 */
67#define _PAGE_PSIZE 0
68/*
69 * _PAGE_CHG_MASK masks of bits that are to be preserved across
70 * pgprot changes
71 */
72#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
73 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
74 _PAGE_SOFT_DIRTY)
75/*
76 * Mask of bits returned by pte_pgprot()
77 */
78#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
79 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
80 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
81 _PAGE_SOFT_DIRTY)
3dfcb315 82/*
2e873519
AK		 83 * We define 2 sets of base prot bits, one for basic pages (ie,
84 * cacheable kernel and user pages) and one for non cacheable
85 * pages. We always set _PAGE_COHERENT when SMP is enabled or
86 * the processor might need it for DMA coherency.
3dfcb315 87 */
2e873519
AK		 88#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
89#define _PAGE_BASE (_PAGE_BASE_NC)
90
91/* Permission masks used to generate the __P and __S table,
92 *
93 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
94 *
95 * Write permissions imply read permissions for now (we could make write-only
96 * pages on BookE but we don't bother for now). Execute permission control is
97 * possible on platforms that define _PAGE_EXEC
98 *
99 * Note due to the way vm flags are laid out, the bits are XWR
100 */
101#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
102#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
103#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
104#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
105#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
106#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
107#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
108
109#define __P000 PAGE_NONE
110#define __P001 PAGE_READONLY
111#define __P010 PAGE_COPY
112#define __P011 PAGE_COPY
113#define __P100 PAGE_READONLY_X
114#define __P101 PAGE_READONLY_X
115#define __P110 PAGE_COPY_X
116#define __P111 PAGE_COPY_X
117
118#define __S000 PAGE_NONE
119#define __S001 PAGE_READONLY
120#define __S010 PAGE_SHARED
121#define __S011 PAGE_SHARED
122#define __S100 PAGE_READONLY_X
123#define __S101 PAGE_READONLY_X
124#define __S110 PAGE_SHARED_X
125#define __S111 PAGE_SHARED_X
126
127/* Permission masks used for kernel mappings */
128#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
129#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
130 _PAGE_TOLERANT)
131#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
132 _PAGE_NON_IDEMPOTENT)
133#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
134#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
135#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
136
137/*
138 * Protection used for kernel text. We want the debuggers to be able to
139 * set breakpoints anywhere, so don't write protect the kernel text
140 * on platforms where such control is possible.
141 */
142#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
143 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
144#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
145#else
146#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
147#endif
148
149/* Make modules code happy. We don't set RO yet */
150#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
151#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 152
dd1842a2
AK		 153#ifndef __ASSEMBLY__
154/*
155 * page table defines
156 */
157extern unsigned long __pte_index_size;
158extern unsigned long __pmd_index_size;
159extern unsigned long __pud_index_size;
160extern unsigned long __pgd_index_size;
161extern unsigned long __pmd_cache_index;
162#define PTE_INDEX_SIZE __pte_index_size
163#define PMD_INDEX_SIZE __pmd_index_size
164#define PUD_INDEX_SIZE __pud_index_size
165#define PGD_INDEX_SIZE __pgd_index_size
166#define PMD_CACHE_INDEX __pmd_cache_index
167/*
168 * Because of use of pte fragments and THP, size of page table
169 * are not always derived out of index size above.
170 */
171extern unsigned long __pte_table_size;
172extern unsigned long __pmd_table_size;
173extern unsigned long __pud_table_size;
174extern unsigned long __pgd_table_size;
175#define PTE_TABLE_SIZE __pte_table_size
176#define PMD_TABLE_SIZE __pmd_table_size
177#define PUD_TABLE_SIZE __pud_table_size
178#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 179
180extern unsigned long __pmd_val_bits;
181extern unsigned long __pud_val_bits;
182extern unsigned long __pgd_val_bits;
183#define PMD_VAL_BITS __pmd_val_bits
184#define PUD_VAL_BITS __pud_val_bits
185#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 186
187extern unsigned long __pte_frag_nr;
188#define PTE_FRAG_NR __pte_frag_nr
189extern unsigned long __pte_frag_size_shift;
190#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
191#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2
AK		 192/*
193 * Pgtable size used by swapper, init in asm code
dd1842a2 194 */
a2f41eb9 195#define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
dd1842a2
AK		 196
197#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
198#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
199#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
200#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
201
202/* PMD_SHIFT determines what a second-level page table entry can map */
203#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
204#define PMD_SIZE (1UL << PMD_SHIFT)
205#define PMD_MASK (~(PMD_SIZE-1))
206
207/* PUD_SHIFT determines what a third-level page table entry can map */
208#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
209#define PUD_SIZE (1UL << PUD_SHIFT)
210#define PUD_MASK (~(PUD_SIZE-1))
211
212/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
213#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
214#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
215#define PGDIR_MASK (~(PGDIR_SIZE-1))
216
217/* Bits to mask out from a PMD to get to the PTE page */
218#define PMD_MASKED_BITS 0xc0000000000000ffUL
219/* Bits to mask out from a PUD to get to the PMD page */
220#define PUD_MASKED_BITS 0xc0000000000000ffUL
221/* Bits to mask out from a PGD to get to the PUD page */
222#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e
AK		 223
224extern unsigned long __vmalloc_start;
225extern unsigned long __vmalloc_end;
226#define VMALLOC_START __vmalloc_start
227#define VMALLOC_END __vmalloc_end
228
229extern unsigned long __kernel_virt_start;
230extern unsigned long __kernel_virt_size;
231#define KERN_VIRT_START __kernel_virt_start
232#define KERN_VIRT_SIZE __kernel_virt_size
233extern struct page *vmemmap;
234extern unsigned long ioremap_bot;
bfa37087 235extern unsigned long pci_io_base;
dd1842a2 236#endif /* __ASSEMBLY__ */
3dfcb315 237
ab537dca 238#include <asm/book3s/64/hash.h>
b0b5e9b1 239#include <asm/book3s/64/radix.h>
3dfcb315 240
a9252aae
AK		 241#ifdef CONFIG_PPC_64K_PAGES
242#include <asm/book3s/64/pgtable-64k.h>
243#else
244#include <asm/book3s/64/pgtable-4k.h>
245#endif
246
3dfcb315 247#include <asm/barrier.h>
3dfcb315
AK		 248/*
249 * The second half of the kernel virtual space is used for IO mappings,
250 * it's itself carved into the PIO region (ISA and PHB IO space) and
251 * the ioremap space
252 *
253 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
254 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
255 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
256 */
257#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
258#define FULL_IO_SIZE 0x80000000ul
259#define ISA_IO_BASE (KERN_IO_START)
260#define ISA_IO_END (KERN_IO_START + 0x10000ul)
261#define PHB_IO_BASE (ISA_IO_END)
262#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
263#define IOREMAP_BASE (PHB_IO_END)
264#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
265
b0412ea9 266/* Advertise special mapping type for AGP */
b0412ea9
AK		 267#define HAVE_PAGE_AGP
268
269/* Advertise support for _PAGE_SPECIAL */
270#define __HAVE_ARCH_PTE_SPECIAL
271
3dfcb315
AK		 272#ifndef __ASSEMBLY__
273
274/*
275 * This is the default implementation of various PTE accessors, it's
276 * used in all cases except Book3S with 64K pages where we have a
277 * concept of sub-pages
278 */
279#ifndef __real_pte
280
3dfcb315
AK		 281#define __real_pte(e,p) ((real_pte_t){(e)})
282#define __rpte_to_pte(r) ((r).pte)
945537df 283#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 284
285#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
286 do { \
287 index = 0; \
288 shift = mmu_psize_defs[psize].shift; \
289
290#define pte_iterate_hashed_end() } while(0)
291
292/*
293 * We expect this to be called only for user addresses or kernel virtual
294 * addresses other than the linear mapping.
295 */
296#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
297
298#endif /* __real_pte */
299
ac94ac79
AK		 300static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
301 pte_t *ptep, unsigned long clr,
302 unsigned long set, int huge)
303{
304 if (radix_enabled())
305 return radix__pte_update(mm, addr, ptep, clr, set, huge);
306 return hash__pte_update(mm, addr, ptep, clr, set, huge);
307}
13f829a5
AK		 308/*
309 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
310 * We currently remove entries from the hashtable regardless of whether
311 * the entry was young or dirty.
312 *
313 * We should be more intelligent about this but for the moment we override
314 * these functions and force a tlb flush unconditionally
315 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
316 * function for both hash and radix.
317 */
318static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
319 unsigned long addr, pte_t *ptep)
320{
321 unsigned long old;
322
66c570f5 323 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
13f829a5
AK		 324 return 0;
325 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
326 return (old & _PAGE_ACCESSED) != 0;
327}
328
329#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
330#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
331({ \
332 int __r; \
333 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
334 __r; \
335})
336
337#define __HAVE_ARCH_PTEP_SET_WRPROTECT
338static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
339 pte_t *ptep)
340{
66c570f5 341 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
13f829a5
AK		 342 return;
343
344 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
345}
346
347static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
348 unsigned long addr, pte_t *ptep)
349{
66c570f5 350 if ((pte_raw(*ptep) & cpu_to_be64(_PAGE_WRITE)) == 0)
13f829a5
AK		 351 return;
352
353 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
354}
355
356#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
357static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
358 unsigned long addr, pte_t *ptep)
359{
360 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
361 return __pte(old);
362}
363
364static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
365 pte_t * ptep)
366{
367 pte_update(mm, addr, ptep, ~0UL, 0, 0);
368}
66c570f5
AK		 369
370static inline int pte_write(pte_t pte)
371{
372 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_WRITE));
373}
374
375static inline int pte_dirty(pte_t pte)
376{
377 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_DIRTY));
378}
379
380static inline int pte_young(pte_t pte)
381{
382 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_ACCESSED));
383}
384
385static inline int pte_special(pte_t pte)
386{
387 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SPECIAL));
388}
389
13f829a5
AK		 390static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
391
392#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
393static inline bool pte_soft_dirty(pte_t pte)
394{
66c570f5 395 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SOFT_DIRTY));
13f829a5 396}
66c570f5 397
13f829a5
AK		 398static inline pte_t pte_mksoft_dirty(pte_t pte)
399{
400 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
401}
402
403static inline pte_t pte_clear_soft_dirty(pte_t pte)
404{
405 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
406}
407#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
408
409#ifdef CONFIG_NUMA_BALANCING
410/*
411 * These work without NUMA balancing but the kernel does not care. See the
412 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
413 * work for user pages and always return true for kernel pages.
414 */
415static inline int pte_protnone(pte_t pte)
416{
66c570f5
AK		 417 return (pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
418 cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED);
13f829a5
AK		 419}
420#endif /* CONFIG_NUMA_BALANCING */
421
422static inline int pte_present(pte_t pte)
423{
66c570f5 424 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT));
13f829a5
AK		 425}
426/*
427 * Conversion functions: convert a page and protection to a page entry,
428 * and a page entry and page directory to the page they refer to.
429 *
430 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
431 * long for now.
432 */
433static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
434{
435 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
436 pgprot_val(pgprot));
437}
438
439static inline unsigned long pte_pfn(pte_t pte)
440{
441 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
442}
443
444/* Generic modifiers for PTE bits */
445static inline pte_t pte_wrprotect(pte_t pte)
446{
447 return __pte(pte_val(pte) & ~_PAGE_WRITE);
448}
449
450static inline pte_t pte_mkclean(pte_t pte)
451{
452 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
453}
454
455static inline pte_t pte_mkold(pte_t pte)
456{
457 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
458}
459
460static inline pte_t pte_mkwrite(pte_t pte)
461{
462 /*
463 * write implies read, hence set both
464 */
465 return __pte(pte_val(pte) | _PAGE_RW);
466}
467
468static inline pte_t pte_mkdirty(pte_t pte)
469{
470 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
471}
472
473static inline pte_t pte_mkyoung(pte_t pte)
474{
475 return __pte(pte_val(pte) | _PAGE_ACCESSED);
476}
477
478static inline pte_t pte_mkspecial(pte_t pte)
479{
480 return __pte(pte_val(pte) | _PAGE_SPECIAL);
481}
482
483static inline pte_t pte_mkhuge(pte_t pte)
484{
485 return pte;
486}
487
488static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
489{
490 /* FIXME!! check whether this need to be a conditional */
491 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
492}
493
34fbadd8
AK		 494static inline bool pte_user(pte_t pte)
495{
66c570f5 496 return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
34fbadd8
AK		 497}
498
499/* Encode and de-code a swap entry */
500#define MAX_SWAPFILES_CHECK() do { \
501 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
502 /* \
503 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
504 * We filter HPTEFLAGS on set_pte. \
505 */ \
506 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
507 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
508 } while (0)
509/*
510 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
511 */
512#define SWP_TYPE_BITS 5
513#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
514 & ((1UL << SWP_TYPE_BITS) - 1))
515#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
516#define __swp_entry(type, offset) ((swp_entry_t) { \
517 ((type) << _PAGE_BIT_SWAP_TYPE) \
518 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
519/*
520 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
521 * swap type and offset we get from swap and convert that to pte to find a
522 * matching pte in linux page table.
523 * Clear bits not found in swap entries here.
524 */
525#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
526#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
527
528#ifdef CONFIG_MEM_SOFT_DIRTY
529#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
530#else
531#define _PAGE_SWP_SOFT_DIRTY 0UL
532#endif /* CONFIG_MEM_SOFT_DIRTY */
533
534#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
535static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
536{
537 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
538}
66c570f5 539
34fbadd8
AK		 540static inline bool pte_swp_soft_dirty(pte_t pte)
541{
66c570f5 542 return !!(pte_raw(pte) & cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
34fbadd8 543}
66c570f5 544
34fbadd8
AK		 545static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
546{
547 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
548}
549#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
550
551static inline bool check_pte_access(unsigned long access, unsigned long ptev)
552{
553 /*
554 * This check for _PAGE_RWX and _PAGE_PRESENT bits
555 */
556 if (access & ~ptev)
557 return false;
558 /*
559 * This check for access to privilege space
560 */
561 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
562 return false;
563
564 return true;
565}
ac94ac79
AK		 566/*
567 * Generic functions with hash/radix callbacks
568 */
569
c6d1a767
AK		 570static inline void __ptep_set_access_flags(struct mm_struct *mm,
571 pte_t *ptep, pte_t entry)
ac94ac79
AK		 572{
573 if (radix_enabled())
c6d1a767 574 return radix__ptep_set_access_flags(mm, ptep, entry);
ac94ac79
AK		 575 return hash__ptep_set_access_flags(ptep, entry);
576}
577
578#define __HAVE_ARCH_PTE_SAME
579static inline int pte_same(pte_t pte_a, pte_t pte_b)
580{
581 if (radix_enabled())
582 return radix__pte_same(pte_a, pte_b);
583 return hash__pte_same(pte_a, pte_b);
584}
585
586static inline int pte_none(pte_t pte)
587{
588 if (radix_enabled())
589 return radix__pte_none(pte);
590 return hash__pte_none(pte);
591}
592
593static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
594 pte_t *ptep, pte_t pte, int percpu)
595{
596 if (radix_enabled())
597 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
598 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
599}
34fbadd8 600
13f829a5
AK		 601#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
602
603#define pgprot_noncached pgprot_noncached
604static inline pgprot_t pgprot_noncached(pgprot_t prot)
605{
606 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
607 _PAGE_NON_IDEMPOTENT);
608}
609
610#define pgprot_noncached_wc pgprot_noncached_wc
611static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
612{
613 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
614 _PAGE_TOLERANT);
615}
616
617#define pgprot_cached pgprot_cached
618static inline pgprot_t pgprot_cached(pgprot_t prot)
619{
620 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
621}
622
623#define pgprot_writecombine pgprot_writecombine
624static inline pgprot_t pgprot_writecombine(pgprot_t prot)
625{
626 return pgprot_noncached_wc(prot);
627}
628/*
629 * check a pte mapping have cache inhibited property
630 */
631static inline bool pte_ci(pte_t pte)
632{
633 unsigned long pte_v = pte_val(pte);
634
635 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
636 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
637 return true;
638 return false;
639}
640
f281b5d5
AK		 641static inline void pmd_set(pmd_t *pmdp, unsigned long val)
642{
643 *pmdp = __pmd(val);
644}
645
646static inline void pmd_clear(pmd_t *pmdp)
647{
648 *pmdp = __pmd(0);
649}
650
66c570f5
AK		 651static inline int pmd_none(pmd_t pmd)
652{
653 return !pmd_raw(pmd);
654}
655
656static inline int pmd_present(pmd_t pmd)
657{
658
659 return !pmd_none(pmd);
660}
3dfcb315 661
ac94ac79
AK		 662static inline int pmd_bad(pmd_t pmd)
663{
664 if (radix_enabled())
665 return radix__pmd_bad(pmd);
666 return hash__pmd_bad(pmd);
667}
668
f281b5d5
AK		 669static inline void pud_set(pud_t *pudp, unsigned long val)
670{
671 *pudp = __pud(val);
672}
673
674static inline void pud_clear(pud_t *pudp)
675{
676 *pudp = __pud(0);
677}
678
66c570f5
AK		 679static inline int pud_none(pud_t pud)
680{
681 return !pud_raw(pud);
682}
683
684static inline int pud_present(pud_t pud)
685{
686 return !pud_none(pud);
687}
3dfcb315
AK		 688
689extern struct page *pud_page(pud_t pud);
371352ca 690extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 691static inline pte_t pud_pte(pud_t pud)
692{
66c570f5 693 return __pte_raw(pud_raw(pud));
3dfcb315
AK		 694}
695
696static inline pud_t pte_pud(pte_t pte)
697{
66c570f5 698 return __pud_raw(pte_raw(pte));
3dfcb315
AK		 699}
700#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 701
702static inline int pud_bad(pud_t pud)
703{
704 if (radix_enabled())
705 return radix__pud_bad(pud);
706 return hash__pud_bad(pud);
707}
708
709
3dfcb315 710#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 711static inline void pgd_set(pgd_t *pgdp, unsigned long val)
712{
713 *pgdp = __pgd(val);
714}
3dfcb315 715
368ced78
AK		 716static inline void pgd_clear(pgd_t *pgdp)
717{
718 *pgdp = __pgd(0);
719}
720
66c570f5
AK		 721static inline int pgd_none(pgd_t pgd)
722{
723 return !pgd_raw(pgd);
724}
725
726static inline int pgd_present(pgd_t pgd)
727{
728 return !pgd_none(pgd);
729}
368ced78
AK		 730
731static inline pte_t pgd_pte(pgd_t pgd)
732{
66c570f5 733 return __pte_raw(pgd_raw(pgd));
368ced78
AK		 734}
735
736static inline pgd_t pte_pgd(pte_t pte)
737{
66c570f5 738 return __pgd_raw(pte_raw(pte));
368ced78
AK		 739}
740
ac94ac79
AK		 741static inline int pgd_bad(pgd_t pgd)
742{
743 if (radix_enabled())
744 return radix__pgd_bad(pgd);
745 return hash__pgd_bad(pgd);
746}
747
368ced78
AK		 748extern struct page *pgd_page(pgd_t pgd);
749
aba480e1
AK		 750/* Pointers in the page table tree are physical addresses */
751#define __pgtable_ptr_val(ptr) __pa(ptr)
752
753#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
754#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
755#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
756
757#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
758#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
759#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
760#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
761
3dfcb315
AK		 762/*
763 * Find an entry in a page-table-directory. We combine the address region
764 * (the high order N bits) and the pgd portion of the address.
765 */
3dfcb315
AK		 766
767#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
768
368ced78
AK		 769#define pud_offset(pgdp, addr) \
770 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 771#define pmd_offset(pudp,addr) \
371352ca 772 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 773#define pte_offset_kernel(dir,addr) \
371352ca 774 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 775
776#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
777#define pte_unmap(pte) do { } while(0)
778
779/* to find an entry in a kernel page-table-directory */
780/* This now only contains the vmalloc pages */
781#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 782
783#define pte_ERROR(e) \
784 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
785#define pmd_ERROR(e) \
786 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 787#define pud_ERROR(e) \
788 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 789#define pgd_ERROR(e) \
790 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
791
3dfcb315
AK		 792void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
793void pgtable_cache_init(void);
2f10f1a7 794
31a14fae
AK		 795static inline int map_kernel_page(unsigned long ea, unsigned long pa,
796 unsigned long flags)
7207f436 797{
d9225ad9
AK		 798 if (radix_enabled()) {
799#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
800 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
801 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
802#endif
803 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
804 }
31a14fae 805 return hash__map_kernel_page(ea, pa, flags);
7207f436 806}
31a14fae
AK		 807
808static inline int __meminit vmemmap_create_mapping(unsigned long start,
809 unsigned long page_size,
810 unsigned long phys)
7207f436 811{
d9225ad9
AK		 812 if (radix_enabled())
813 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 814 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 815}
31a14fae
AK		 816
817#ifdef CONFIG_MEMORY_HOTPLUG
818static inline void vmemmap_remove_mapping(unsigned long start,
819 unsigned long page_size)
7207f436 820{
d9225ad9
AK		 821 if (radix_enabled())
822 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 823 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 824}
31a14fae 825#endif
3dfcb315
AK		 826struct page *realmode_pfn_to_page(unsigned long pfn);
827
3dfcb315
AK		 828static inline pte_t pmd_pte(pmd_t pmd)
829{
66c570f5 830 return __pte_raw(pmd_raw(pmd));
3dfcb315
AK		 831}
832
833static inline pmd_t pte_pmd(pte_t pte)
834{
66c570f5 835 return __pmd_raw(pte_raw(pte));
3dfcb315
AK		 836}
837
838static inline pte_t *pmdp_ptep(pmd_t *pmd)
839{
840 return (pte_t *)pmd;
841}
3dfcb315
AK		 842#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
843#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
844#define pmd_young(pmd) pte_young(pmd_pte(pmd))
845#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
846#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
847#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 848#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 849#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
850#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
7207f436
LD		 851
852#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
853#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
854#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
855#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
856#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
857
1ca72129
AK		 858#ifdef CONFIG_NUMA_BALANCING
859static inline int pmd_protnone(pmd_t pmd)
860{
861 return pte_protnone(pmd_pte(pmd));
862}
863#endif /* CONFIG_NUMA_BALANCING */
3dfcb315
AK		 864
865#define __HAVE_ARCH_PMD_WRITE
866#define pmd_write(pmd) pte_write(pmd_pte(pmd))
867
6a1ea362
AK		 868#ifdef CONFIG_TRANSPARENT_HUGEPAGE
869extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
870extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
871extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
872extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
873 pmd_t *pmdp, pmd_t pmd);
874extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
875 pmd_t *pmd);
3df33f12
AK		 876extern int hash__has_transparent_hugepage(void);
877static inline int has_transparent_hugepage(void)
878{
bde3eb62
AK		 879 if (radix_enabled())
880 return radix__has_transparent_hugepage();
3df33f12
AK		 881 return hash__has_transparent_hugepage();
882}
c04a5880 883#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 884
3df33f12
AK		 885static inline unsigned long
886pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
887 unsigned long clr, unsigned long set)
3dfcb315 888{
bde3eb62
AK		 889 if (radix_enabled())
890 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 891 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
892}
893
894static inline int pmd_large(pmd_t pmd)
895{
66c570f5 896 return !!(pmd_raw(pmd) & cpu_to_be64(_PAGE_PTE));
3df33f12
AK		 897}
898
899static inline pmd_t pmd_mknotpresent(pmd_t pmd)
900{
901 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
902}
903/*
904 * For radix we should always find H_PAGE_HASHPTE zero. Hence
905 * the below will work for radix too
906 */
907static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
908 unsigned long addr, pmd_t *pmdp)
909{
910 unsigned long old;
911
66c570f5 912 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
3df33f12
AK		 913 return 0;
914 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
915 return ((old & _PAGE_ACCESSED) != 0);
916}
917
918#define __HAVE_ARCH_PMDP_SET_WRPROTECT
919static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
920 pmd_t *pmdp)
921{
922
66c570f5 923 if ((pmd_raw(*pmdp) & cpu_to_be64(_PAGE_WRITE)) == 0)
3df33f12
AK		 924 return;
925
926 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
3dfcb315
AK		 927}
928
ab624762
AK		 929static inline int pmd_trans_huge(pmd_t pmd)
930{
931 if (radix_enabled())
932 return radix__pmd_trans_huge(pmd);
933 return hash__pmd_trans_huge(pmd);
934}
935
936#define __HAVE_ARCH_PMD_SAME
937static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
938{
939 if (radix_enabled())
940 return radix__pmd_same(pmd_a, pmd_b);
941 return hash__pmd_same(pmd_a, pmd_b);
942}
943
3dfcb315
AK		 944static inline pmd_t pmd_mkhuge(pmd_t pmd)
945{
ab624762
AK		 946 if (radix_enabled())
947 return radix__pmd_mkhuge(pmd);
948 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 949}
950
3dfcb315
AK		 951#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
952extern int pmdp_set_access_flags(struct vm_area_struct *vma,
953 unsigned long address, pmd_t *pmdp,
954 pmd_t entry, int dirty);
955
3dfcb315
AK		 956#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
957extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
958 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 959
960#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 961static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
962 unsigned long addr, pmd_t *pmdp)
963{
bde3eb62
AK		 964 if (radix_enabled())
965 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 966 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
967}
3dfcb315 968
3df33f12
AK		 969static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
970 unsigned long address, pmd_t *pmdp)
971{
bde3eb62
AK		 972 if (radix_enabled())
973 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 974 return hash__pmdp_collapse_flush(vma, address, pmdp);
975}
3dfcb315
AK		 976#define pmdp_collapse_flush pmdp_collapse_flush
977
978#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 979static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
980 pmd_t *pmdp, pgtable_t pgtable)
981{
bde3eb62
AK		 982 if (radix_enabled())
983 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 984 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
985}
986
3dfcb315 987#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 988static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
989 pmd_t *pmdp)
990{
bde3eb62
AK		 991 if (radix_enabled())
992 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 993 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
994}
3dfcb315
AK		 995
996#define __HAVE_ARCH_PMDP_INVALIDATE
997extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
998 pmd_t *pmdp);
999
c777e2a8 1000#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
3df33f12
AK		 1001static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
1002 unsigned long address, pmd_t *pmdp)
1003{
bde3eb62
AK		 1004 if (radix_enabled())
1005 return radix__pmdp_huge_split_prepare(vma, address, pmdp);
3df33f12
AK		 1006 return hash__pmdp_huge_split_prepare(vma, address, pmdp);
1007}
c777e2a8 1008
3dfcb315
AK		 1009#define pmd_move_must_withdraw pmd_move_must_withdraw
1010struct spinlock;
1011static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
1dd38b6c
AK		 1012 struct spinlock *old_pmd_ptl,
1013 struct vm_area_struct *vma)
3dfcb315 1014{
bde3eb62
AK		 1015 if (radix_enabled())
1016 return false;
3dfcb315
AK		 1017 /*
1018 * Archs like ppc64 use pgtable to store per pmd
1019 * specific information. So when we switch the pmd,
1020 * we should also withdraw and deposit the pgtable
1021 */
1022 return true;
1023}
6a1ea362 1024#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
3dfcb315
AK		 1025#endif /* __ASSEMBLY__ */
1026#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)