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powerpc/tm: Avoid SLB faults in treclaim/trecheckpoint when RI=0
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
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3dfcb315
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519
AK		 3
4/*
5 * Common bits between hash and Radix page table
6 */
7#define _PAGE_BIT_SWAP_TYPE 0
8
9#define _PAGE_EXEC 0x00001 /* execute permission */
10#define _PAGE_WRITE 0x00002 /* write access allowed */
11#define _PAGE_READ 0x00004 /* read access allowed */
12#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
13#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
14#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
15#define _PAGE_SAO 0x00010 /* Strong access order */
16#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
17#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
18#define _PAGE_DIRTY 0x00080 /* C: page changed */
19#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
3dfcb315 20/*
2e873519 21 * Software bits
3dfcb315 22 */
69dfbaeb
AK		 23#define _RPAGE_SW0 0x2000000000000000UL
24#define _RPAGE_SW1 0x00800
25#define _RPAGE_SW2 0x00400
26#define _RPAGE_SW3 0x00200
2e873519 27#ifdef CONFIG_MEM_SOFT_DIRTY
69dfbaeb 28#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
2e873519
AK		 29#else
30#define _PAGE_SOFT_DIRTY 0x00000
31#endif
69dfbaeb 32#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
2e873519
AK		 33
34
35#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
36#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
37/*
38 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
39 * Instead of fixing all of them, add an alternate define which
40 * maps CI pte mapping.
41 */
42#define _PAGE_NO_CACHE _PAGE_TOLERANT
43/*
44 * We support 57 bit real address in pte. Clear everything above 57, and
45 * every thing below PAGE_SHIFT;
46 */
47#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
48/*
49 * set of bits not changed in pmd_modify. Even though we have hash specific bits
50 * in here, on radix we expect them to be zero.
51 */
52#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
53 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
54 _PAGE_SOFT_DIRTY)
55/*
56 * user access blocked by key
57 */
58#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
59#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
60#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
61 _PAGE_RW | _PAGE_EXEC)
62/*
63 * No page size encoding in the linux PTE
64 */
65#define _PAGE_PSIZE 0
66/*
67 * _PAGE_CHG_MASK masks of bits that are to be preserved across
68 * pgprot changes
69 */
70#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
71 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
72 _PAGE_SOFT_DIRTY)
73/*
74 * Mask of bits returned by pte_pgprot()
75 */
76#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
77 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
78 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
79 _PAGE_SOFT_DIRTY)
3dfcb315 80/*
2e873519
AK		 81 * We define 2 sets of base prot bits, one for basic pages (ie,
82 * cacheable kernel and user pages) and one for non cacheable
83 * pages. We always set _PAGE_COHERENT when SMP is enabled or
84 * the processor might need it for DMA coherency.
3dfcb315 85 */
2e873519
AK		 86#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
87#define _PAGE_BASE (_PAGE_BASE_NC)
88
89/* Permission masks used to generate the __P and __S table,
90 *
91 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
92 *
93 * Write permissions imply read permissions for now (we could make write-only
94 * pages on BookE but we don't bother for now). Execute permission control is
95 * possible on platforms that define _PAGE_EXEC
96 *
97 * Note due to the way vm flags are laid out, the bits are XWR
98 */
99#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
100#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
101#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
102#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
103#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
104#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
105#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
106
107#define __P000 PAGE_NONE
108#define __P001 PAGE_READONLY
109#define __P010 PAGE_COPY
110#define __P011 PAGE_COPY
111#define __P100 PAGE_READONLY_X
112#define __P101 PAGE_READONLY_X
113#define __P110 PAGE_COPY_X
114#define __P111 PAGE_COPY_X
115
116#define __S000 PAGE_NONE
117#define __S001 PAGE_READONLY
118#define __S010 PAGE_SHARED
119#define __S011 PAGE_SHARED
120#define __S100 PAGE_READONLY_X
121#define __S101 PAGE_READONLY_X
122#define __S110 PAGE_SHARED_X
123#define __S111 PAGE_SHARED_X
124
125/* Permission masks used for kernel mappings */
126#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
127#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
128 _PAGE_TOLERANT)
129#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
130 _PAGE_NON_IDEMPOTENT)
131#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
132#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
133#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
134
135/*
136 * Protection used for kernel text. We want the debuggers to be able to
137 * set breakpoints anywhere, so don't write protect the kernel text
138 * on platforms where such control is possible.
139 */
140#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
141 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
142#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
143#else
144#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
145#endif
146
147/* Make modules code happy. We don't set RO yet */
148#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
149#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 150
dd1842a2
AK		 151#ifndef __ASSEMBLY__
152/*
153 * page table defines
154 */
155extern unsigned long __pte_index_size;
156extern unsigned long __pmd_index_size;
157extern unsigned long __pud_index_size;
158extern unsigned long __pgd_index_size;
159extern unsigned long __pmd_cache_index;
160#define PTE_INDEX_SIZE __pte_index_size
161#define PMD_INDEX_SIZE __pmd_index_size
162#define PUD_INDEX_SIZE __pud_index_size
163#define PGD_INDEX_SIZE __pgd_index_size
164#define PMD_CACHE_INDEX __pmd_cache_index
165/*
166 * Because of use of pte fragments and THP, size of page table
167 * are not always derived out of index size above.
168 */
169extern unsigned long __pte_table_size;
170extern unsigned long __pmd_table_size;
171extern unsigned long __pud_table_size;
172extern unsigned long __pgd_table_size;
173#define PTE_TABLE_SIZE __pte_table_size
174#define PMD_TABLE_SIZE __pmd_table_size
175#define PUD_TABLE_SIZE __pud_table_size
176#define PGD_TABLE_SIZE __pgd_table_size
a2f41eb9
AK		 177
178extern unsigned long __pmd_val_bits;
179extern unsigned long __pud_val_bits;
180extern unsigned long __pgd_val_bits;
181#define PMD_VAL_BITS __pmd_val_bits
182#define PUD_VAL_BITS __pud_val_bits
183#define PGD_VAL_BITS __pgd_val_bits
5ed7ecd0
AK		 184
185extern unsigned long __pte_frag_nr;
186#define PTE_FRAG_NR __pte_frag_nr
187extern unsigned long __pte_frag_size_shift;
188#define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift
189#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
dd1842a2
AK		 190/*
191 * Pgtable size used by swapper, init in asm code
dd1842a2 192 */
a2f41eb9 193#define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE)
dd1842a2
AK		 194
195#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
196#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
197#define PTRS_PER_PUD (1 << PUD_INDEX_SIZE)
198#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
199
200/* PMD_SHIFT determines what a second-level page table entry can map */
201#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
202#define PMD_SIZE (1UL << PMD_SHIFT)
203#define PMD_MASK (~(PMD_SIZE-1))
204
205/* PUD_SHIFT determines what a third-level page table entry can map */
206#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
207#define PUD_SIZE (1UL << PUD_SHIFT)
208#define PUD_MASK (~(PUD_SIZE-1))
209
210/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
211#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
212#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
213#define PGDIR_MASK (~(PGDIR_SIZE-1))
214
215/* Bits to mask out from a PMD to get to the PTE page */
216#define PMD_MASKED_BITS 0xc0000000000000ffUL
217/* Bits to mask out from a PUD to get to the PMD page */
218#define PUD_MASKED_BITS 0xc0000000000000ffUL
219/* Bits to mask out from a PGD to get to the PUD page */
220#define PGD_MASKED_BITS 0xc0000000000000ffUL
d6a9996e
AK		 221
222extern unsigned long __vmalloc_start;
223extern unsigned long __vmalloc_end;
224#define VMALLOC_START __vmalloc_start
225#define VMALLOC_END __vmalloc_end
226
227extern unsigned long __kernel_virt_start;
228extern unsigned long __kernel_virt_size;
229#define KERN_VIRT_START __kernel_virt_start
230#define KERN_VIRT_SIZE __kernel_virt_size
231extern struct page *vmemmap;
232extern unsigned long ioremap_bot;
dd1842a2 233#endif /* __ASSEMBLY__ */
3dfcb315 234
ab537dca 235#include <asm/book3s/64/hash.h>
b0b5e9b1 236#include <asm/book3s/64/radix.h>
3dfcb315 237
a9252aae
AK		 238#ifdef CONFIG_PPC_64K_PAGES
239#include <asm/book3s/64/pgtable-64k.h>
240#else
241#include <asm/book3s/64/pgtable-4k.h>
242#endif
243
3dfcb315 244#include <asm/barrier.h>
3dfcb315
AK		 245/*
246 * The second half of the kernel virtual space is used for IO mappings,
247 * it's itself carved into the PIO region (ISA and PHB IO space) and
248 * the ioremap space
249 *
250 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
251 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
252 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
253 */
254#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
255#define FULL_IO_SIZE 0x80000000ul
256#define ISA_IO_BASE (KERN_IO_START)
257#define ISA_IO_END (KERN_IO_START + 0x10000ul)
258#define PHB_IO_BASE (ISA_IO_END)
259#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
260#define IOREMAP_BASE (PHB_IO_END)
261#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
262
b0412ea9 263/* Advertise special mapping type for AGP */
b0412ea9
AK		 264#define HAVE_PAGE_AGP
265
266/* Advertise support for _PAGE_SPECIAL */
267#define __HAVE_ARCH_PTE_SPECIAL
268
3dfcb315
AK		 269#ifndef __ASSEMBLY__
270
271/*
272 * This is the default implementation of various PTE accessors, it's
273 * used in all cases except Book3S with 64K pages where we have a
274 * concept of sub-pages
275 */
276#ifndef __real_pte
277
3dfcb315
AK		 278#define __real_pte(e,p) ((real_pte_t){(e)})
279#define __rpte_to_pte(r) ((r).pte)
945537df 280#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 281
282#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
283 do { \
284 index = 0; \
285 shift = mmu_psize_defs[psize].shift; \
286
287#define pte_iterate_hashed_end() } while(0)
288
289/*
290 * We expect this to be called only for user addresses or kernel virtual
291 * addresses other than the linear mapping.
292 */
293#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
294
295#endif /* __real_pte */
296
ac94ac79
AK		 297static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr,
298 pte_t *ptep, unsigned long clr,
299 unsigned long set, int huge)
300{
301 if (radix_enabled())
302 return radix__pte_update(mm, addr, ptep, clr, set, huge);
303 return hash__pte_update(mm, addr, ptep, clr, set, huge);
304}
13f829a5
AK		 305/*
306 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
307 * We currently remove entries from the hashtable regardless of whether
308 * the entry was young or dirty.
309 *
310 * We should be more intelligent about this but for the moment we override
311 * these functions and force a tlb flush unconditionally
312 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
313 * function for both hash and radix.
314 */
315static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
316 unsigned long addr, pte_t *ptep)
317{
318 unsigned long old;
319
320 if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
321 return 0;
322 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
323 return (old & _PAGE_ACCESSED) != 0;
324}
325
326#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
327#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
328({ \
329 int __r; \
330 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
331 __r; \
332})
333
334#define __HAVE_ARCH_PTEP_SET_WRPROTECT
335static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
336 pte_t *ptep)
337{
338
339 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
340 return;
341
342 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
343}
344
345static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
346 unsigned long addr, pte_t *ptep)
347{
348 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
349 return;
350
351 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
352}
353
354#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
355static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
356 unsigned long addr, pte_t *ptep)
357{
358 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
359 return __pte(old);
360}
361
362static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
363 pte_t * ptep)
364{
365 pte_update(mm, addr, ptep, ~0UL, 0, 0);
366}
367static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);}
368static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
369static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
370static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
371static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
372
373#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
374static inline bool pte_soft_dirty(pte_t pte)
375{
376 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
377}
378static inline pte_t pte_mksoft_dirty(pte_t pte)
379{
380 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
381}
382
383static inline pte_t pte_clear_soft_dirty(pte_t pte)
384{
385 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
386}
387#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
388
389#ifdef CONFIG_NUMA_BALANCING
390/*
391 * These work without NUMA balancing but the kernel does not care. See the
392 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
393 * work for user pages and always return true for kernel pages.
394 */
395static inline int pte_protnone(pte_t pte)
396{
397 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
398 (_PAGE_PRESENT | _PAGE_PRIVILEGED);
399}
400#endif /* CONFIG_NUMA_BALANCING */
401
402static inline int pte_present(pte_t pte)
403{
404 return !!(pte_val(pte) & _PAGE_PRESENT);
405}
406/*
407 * Conversion functions: convert a page and protection to a page entry,
408 * and a page entry and page directory to the page they refer to.
409 *
410 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
411 * long for now.
412 */
413static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
414{
415 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
416 pgprot_val(pgprot));
417}
418
419static inline unsigned long pte_pfn(pte_t pte)
420{
421 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
422}
423
424/* Generic modifiers for PTE bits */
425static inline pte_t pte_wrprotect(pte_t pte)
426{
427 return __pte(pte_val(pte) & ~_PAGE_WRITE);
428}
429
430static inline pte_t pte_mkclean(pte_t pte)
431{
432 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
433}
434
435static inline pte_t pte_mkold(pte_t pte)
436{
437 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
438}
439
440static inline pte_t pte_mkwrite(pte_t pte)
441{
442 /*
443 * write implies read, hence set both
444 */
445 return __pte(pte_val(pte) | _PAGE_RW);
446}
447
448static inline pte_t pte_mkdirty(pte_t pte)
449{
450 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
451}
452
453static inline pte_t pte_mkyoung(pte_t pte)
454{
455 return __pte(pte_val(pte) | _PAGE_ACCESSED);
456}
457
458static inline pte_t pte_mkspecial(pte_t pte)
459{
460 return __pte(pte_val(pte) | _PAGE_SPECIAL);
461}
462
463static inline pte_t pte_mkhuge(pte_t pte)
464{
465 return pte;
466}
467
468static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
469{
470 /* FIXME!! check whether this need to be a conditional */
471 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
472}
473
34fbadd8
AK		 474static inline bool pte_user(pte_t pte)
475{
476 return !(pte_val(pte) & _PAGE_PRIVILEGED);
477}
478
479/* Encode and de-code a swap entry */
480#define MAX_SWAPFILES_CHECK() do { \
481 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
482 /* \
483 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
484 * We filter HPTEFLAGS on set_pte. \
485 */ \
486 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
487 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
488 } while (0)
489/*
490 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
491 */
492#define SWP_TYPE_BITS 5
493#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
494 & ((1UL << SWP_TYPE_BITS) - 1))
495#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
496#define __swp_entry(type, offset) ((swp_entry_t) { \
497 ((type) << _PAGE_BIT_SWAP_TYPE) \
498 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
499/*
500 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
501 * swap type and offset we get from swap and convert that to pte to find a
502 * matching pte in linux page table.
503 * Clear bits not found in swap entries here.
504 */
505#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
506#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
507
508#ifdef CONFIG_MEM_SOFT_DIRTY
509#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
510#else
511#define _PAGE_SWP_SOFT_DIRTY 0UL
512#endif /* CONFIG_MEM_SOFT_DIRTY */
513
514#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
515static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
516{
517 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
518}
519static inline bool pte_swp_soft_dirty(pte_t pte)
520{
521 return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
522}
523static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
524{
525 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
526}
527#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
528
529static inline bool check_pte_access(unsigned long access, unsigned long ptev)
530{
531 /*
532 * This check for _PAGE_RWX and _PAGE_PRESENT bits
533 */
534 if (access & ~ptev)
535 return false;
536 /*
537 * This check for access to privilege space
538 */
539 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
540 return false;
541
542 return true;
543}
ac94ac79
AK		 544/*
545 * Generic functions with hash/radix callbacks
546 */
547
548static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
549{
550 if (radix_enabled())
551 return radix__ptep_set_access_flags(ptep, entry);
552 return hash__ptep_set_access_flags(ptep, entry);
553}
554
555#define __HAVE_ARCH_PTE_SAME
556static inline int pte_same(pte_t pte_a, pte_t pte_b)
557{
558 if (radix_enabled())
559 return radix__pte_same(pte_a, pte_b);
560 return hash__pte_same(pte_a, pte_b);
561}
562
563static inline int pte_none(pte_t pte)
564{
565 if (radix_enabled())
566 return radix__pte_none(pte);
567 return hash__pte_none(pte);
568}
569
570static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
571 pte_t *ptep, pte_t pte, int percpu)
572{
573 if (radix_enabled())
574 return radix__set_pte_at(mm, addr, ptep, pte, percpu);
575 return hash__set_pte_at(mm, addr, ptep, pte, percpu);
576}
34fbadd8 577
13f829a5
AK		 578#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
579
580#define pgprot_noncached pgprot_noncached
581static inline pgprot_t pgprot_noncached(pgprot_t prot)
582{
583 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
584 _PAGE_NON_IDEMPOTENT);
585}
586
587#define pgprot_noncached_wc pgprot_noncached_wc
588static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
589{
590 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
591 _PAGE_TOLERANT);
592}
593
594#define pgprot_cached pgprot_cached
595static inline pgprot_t pgprot_cached(pgprot_t prot)
596{
597 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
598}
599
600#define pgprot_writecombine pgprot_writecombine
601static inline pgprot_t pgprot_writecombine(pgprot_t prot)
602{
603 return pgprot_noncached_wc(prot);
604}
605/*
606 * check a pte mapping have cache inhibited property
607 */
608static inline bool pte_ci(pte_t pte)
609{
610 unsigned long pte_v = pte_val(pte);
611
612 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
613 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
614 return true;
615 return false;
616}
617
f281b5d5
AK		 618static inline void pmd_set(pmd_t *pmdp, unsigned long val)
619{
620 *pmdp = __pmd(val);
621}
622
623static inline void pmd_clear(pmd_t *pmdp)
624{
625 *pmdp = __pmd(0);
626}
627
3dfcb315 628#define pmd_none(pmd) (!pmd_val(pmd))
3dfcb315 629#define pmd_present(pmd) (!pmd_none(pmd))
3dfcb315 630
ac94ac79
AK		 631static inline int pmd_bad(pmd_t pmd)
632{
633 if (radix_enabled())
634 return radix__pmd_bad(pmd);
635 return hash__pmd_bad(pmd);
636}
637
f281b5d5
AK		 638static inline void pud_set(pud_t *pudp, unsigned long val)
639{
640 *pudp = __pud(val);
641}
642
643static inline void pud_clear(pud_t *pudp)
644{
645 *pudp = __pud(0);
646}
647
3dfcb315 648#define pud_none(pud) (!pud_val(pud))
3dfcb315 649#define pud_present(pud) (pud_val(pud) != 0)
3dfcb315
AK		 650
651extern struct page *pud_page(pud_t pud);
371352ca 652extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 653static inline pte_t pud_pte(pud_t pud)
654{
655 return __pte(pud_val(pud));
656}
657
658static inline pud_t pte_pud(pte_t pte)
659{
660 return __pud(pte_val(pte));
661}
662#define pud_write(pud) pte_write(pud_pte(pud))
ac94ac79
AK		 663
664static inline int pud_bad(pud_t pud)
665{
666 if (radix_enabled())
667 return radix__pud_bad(pud);
668 return hash__pud_bad(pud);
669}
670
671
3dfcb315 672#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 673static inline void pgd_set(pgd_t *pgdp, unsigned long val)
674{
675 *pgdp = __pgd(val);
676}
3dfcb315 677
368ced78
AK		 678static inline void pgd_clear(pgd_t *pgdp)
679{
680 *pgdp = __pgd(0);
681}
682
683#define pgd_none(pgd) (!pgd_val(pgd))
684#define pgd_present(pgd) (!pgd_none(pgd))
685
686static inline pte_t pgd_pte(pgd_t pgd)
687{
688 return __pte(pgd_val(pgd));
689}
690
691static inline pgd_t pte_pgd(pte_t pte)
692{
693 return __pgd(pte_val(pte));
694}
695
ac94ac79
AK		 696static inline int pgd_bad(pgd_t pgd)
697{
698 if (radix_enabled())
699 return radix__pgd_bad(pgd);
700 return hash__pgd_bad(pgd);
701}
702
368ced78
AK		 703extern struct page *pgd_page(pgd_t pgd);
704
aba480e1
AK		 705/* Pointers in the page table tree are physical addresses */
706#define __pgtable_ptr_val(ptr) __pa(ptr)
707
708#define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS)
709#define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS)
710#define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS)
711
712#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
713#define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1))
714#define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
715#define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
716
3dfcb315
AK		 717/*
718 * Find an entry in a page-table-directory. We combine the address region
719 * (the high order N bits) and the pgd portion of the address.
720 */
3dfcb315
AK		 721
722#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
723
368ced78
AK		 724#define pud_offset(pgdp, addr) \
725 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 726#define pmd_offset(pudp,addr) \
371352ca 727 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 728#define pte_offset_kernel(dir,addr) \
371352ca 729 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 730
731#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
732#define pte_unmap(pte) do { } while(0)
733
734/* to find an entry in a kernel page-table-directory */
735/* This now only contains the vmalloc pages */
736#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 737
738#define pte_ERROR(e) \
739 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
740#define pmd_ERROR(e) \
741 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 742#define pud_ERROR(e) \
743 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 744#define pgd_ERROR(e) \
745 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
746
3dfcb315
AK		 747void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
748void pgtable_cache_init(void);
2f10f1a7 749
31a14fae
AK		 750static inline int map_kernel_page(unsigned long ea, unsigned long pa,
751 unsigned long flags)
7207f436 752{
d9225ad9
AK		 753 if (radix_enabled()) {
754#if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM)
755 unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift;
756 WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE");
757#endif
758 return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE);
759 }
31a14fae 760 return hash__map_kernel_page(ea, pa, flags);
7207f436 761}
31a14fae
AK		 762
763static inline int __meminit vmemmap_create_mapping(unsigned long start,
764 unsigned long page_size,
765 unsigned long phys)
7207f436 766{
d9225ad9
AK		 767 if (radix_enabled())
768 return radix__vmemmap_create_mapping(start, page_size, phys);
31a14fae 769 return hash__vmemmap_create_mapping(start, page_size, phys);
7207f436 770}
31a14fae
AK		 771
772#ifdef CONFIG_MEMORY_HOTPLUG
773static inline void vmemmap_remove_mapping(unsigned long start,
774 unsigned long page_size)
7207f436 775{
d9225ad9
AK		 776 if (radix_enabled())
777 return radix__vmemmap_remove_mapping(start, page_size);
31a14fae 778 return hash__vmemmap_remove_mapping(start, page_size);
7207f436 779}
31a14fae 780#endif
3dfcb315
AK		 781struct page *realmode_pfn_to_page(unsigned long pfn);
782
3dfcb315
AK		 783static inline pte_t pmd_pte(pmd_t pmd)
784{
785 return __pte(pmd_val(pmd));
786}
787
788static inline pmd_t pte_pmd(pte_t pte)
789{
790 return __pmd(pte_val(pte));
791}
792
793static inline pte_t *pmdp_ptep(pmd_t *pmd)
794{
795 return (pte_t *)pmd;
796}
3dfcb315
AK		 797#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
798#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
799#define pmd_young(pmd) pte_young(pmd_pte(pmd))
800#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
801#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
802#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 803#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
3dfcb315
AK		 804#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
805#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
7207f436
LD		 806
807#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
808#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
809#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
810#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
811#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
812
1ca72129
AK		 813#ifdef CONFIG_NUMA_BALANCING
814static inline int pmd_protnone(pmd_t pmd)
815{
816 return pte_protnone(pmd_pte(pmd));
817}
818#endif /* CONFIG_NUMA_BALANCING */
3dfcb315
AK		 819
820#define __HAVE_ARCH_PMD_WRITE
821#define pmd_write(pmd) pte_write(pmd_pte(pmd))
822
6a1ea362
AK		 823#ifdef CONFIG_TRANSPARENT_HUGEPAGE
824extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
825extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
826extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
827extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
828 pmd_t *pmdp, pmd_t pmd);
829extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
830 pmd_t *pmd);
3df33f12
AK		 831extern int hash__has_transparent_hugepage(void);
832static inline int has_transparent_hugepage(void)
833{
bde3eb62
AK		 834 if (radix_enabled())
835 return radix__has_transparent_hugepage();
3df33f12
AK		 836 return hash__has_transparent_hugepage();
837}
c04a5880 838#define has_transparent_hugepage has_transparent_hugepage
6a1ea362 839
3df33f12
AK		 840static inline unsigned long
841pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp,
842 unsigned long clr, unsigned long set)
3dfcb315 843{
bde3eb62
AK		 844 if (radix_enabled())
845 return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set);
3df33f12
AK		 846 return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set);
847}
848
849static inline int pmd_large(pmd_t pmd)
850{
851 return !!(pmd_val(pmd) & _PAGE_PTE);
852}
853
854static inline pmd_t pmd_mknotpresent(pmd_t pmd)
855{
856 return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT);
857}
858/*
859 * For radix we should always find H_PAGE_HASHPTE zero. Hence
860 * the below will work for radix too
861 */
862static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
863 unsigned long addr, pmd_t *pmdp)
864{
865 unsigned long old;
866
867 if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
868 return 0;
869 old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0);
870 return ((old & _PAGE_ACCESSED) != 0);
871}
872
873#define __HAVE_ARCH_PMDP_SET_WRPROTECT
874static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
875 pmd_t *pmdp)
876{
877
878 if ((pmd_val(*pmdp) & _PAGE_WRITE) == 0)
879 return;
880
881 pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0);
3dfcb315
AK		 882}
883
ab624762
AK		 884static inline int pmd_trans_huge(pmd_t pmd)
885{
886 if (radix_enabled())
887 return radix__pmd_trans_huge(pmd);
888 return hash__pmd_trans_huge(pmd);
889}
890
891#define __HAVE_ARCH_PMD_SAME
892static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
893{
894 if (radix_enabled())
895 return radix__pmd_same(pmd_a, pmd_b);
896 return hash__pmd_same(pmd_a, pmd_b);
897}
898
3dfcb315
AK		 899static inline pmd_t pmd_mkhuge(pmd_t pmd)
900{
ab624762
AK		 901 if (radix_enabled())
902 return radix__pmd_mkhuge(pmd);
903 return hash__pmd_mkhuge(pmd);
3dfcb315
AK		 904}
905
3dfcb315
AK		 906#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
907extern int pmdp_set_access_flags(struct vm_area_struct *vma,
908 unsigned long address, pmd_t *pmdp,
909 pmd_t entry, int dirty);
910
3dfcb315
AK		 911#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
912extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
913 unsigned long address, pmd_t *pmdp);
3dfcb315
AK		 914
915#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
3df33f12
AK		 916static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
917 unsigned long addr, pmd_t *pmdp)
918{
bde3eb62
AK		 919 if (radix_enabled())
920 return radix__pmdp_huge_get_and_clear(mm, addr, pmdp);
3df33f12
AK		 921 return hash__pmdp_huge_get_and_clear(mm, addr, pmdp);
922}
3dfcb315 923
3df33f12
AK		 924static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
925 unsigned long address, pmd_t *pmdp)
926{
bde3eb62
AK		 927 if (radix_enabled())
928 return radix__pmdp_collapse_flush(vma, address, pmdp);
3df33f12
AK		 929 return hash__pmdp_collapse_flush(vma, address, pmdp);
930}
3dfcb315
AK		 931#define pmdp_collapse_flush pmdp_collapse_flush
932
933#define __HAVE_ARCH_PGTABLE_DEPOSIT
3df33f12
AK		 934static inline void pgtable_trans_huge_deposit(struct mm_struct *mm,
935 pmd_t *pmdp, pgtable_t pgtable)
936{
bde3eb62
AK		 937 if (radix_enabled())
938 return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
3df33f12
AK		 939 return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable);
940}
941
3dfcb315 942#define __HAVE_ARCH_PGTABLE_WITHDRAW
3df33f12
AK		 943static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm,
944 pmd_t *pmdp)
945{
bde3eb62
AK		 946 if (radix_enabled())
947 return radix__pgtable_trans_huge_withdraw(mm, pmdp);
3df33f12
AK		 948 return hash__pgtable_trans_huge_withdraw(mm, pmdp);
949}
3dfcb315
AK		 950
951#define __HAVE_ARCH_PMDP_INVALIDATE
952extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
953 pmd_t *pmdp);
954
c777e2a8 955#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
3df33f12
AK		 956static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma,
957 unsigned long address, pmd_t *pmdp)
958{
bde3eb62
AK		 959 if (radix_enabled())
960 return radix__pmdp_huge_split_prepare(vma, address, pmdp);
3df33f12
AK		 961 return hash__pmdp_huge_split_prepare(vma, address, pmdp);
962}
c777e2a8 963
3dfcb315
AK		 964#define pmd_move_must_withdraw pmd_move_must_withdraw
965struct spinlock;
966static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
967 struct spinlock *old_pmd_ptl)
968{
bde3eb62
AK		 969 if (radix_enabled())
970 return false;
3dfcb315
AK		 971 /*
972 * Archs like ppc64 use pgtable to store per pmd
973 * specific information. So when we switch the pmd,
974 * we should also withdraw and deposit the pgtable
975 */
976 return true;
977}
6a1ea362 978#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
3dfcb315
AK		 979#endif /* __ASSEMBLY__ */
980#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)