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powerpc/mm: Move pte accessors that operate on common pte bits to pgtable.h
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / pgtable.h
CommitLineData
3dfcb315
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2#define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_
2e873519
AK		 3
4/*
5 * Common bits between hash and Radix page table
6 */
7#define _PAGE_BIT_SWAP_TYPE 0
8
9#define _PAGE_EXEC 0x00001 /* execute permission */
10#define _PAGE_WRITE 0x00002 /* write access allowed */
11#define _PAGE_READ 0x00004 /* read access allowed */
12#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
13#define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
14#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */
15#define _PAGE_SAO 0x00010 /* Strong access order */
16#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
17#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
18#define _PAGE_DIRTY 0x00080 /* C: page changed */
19#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
20/*
21 * Software bits
22 */
23#ifdef CONFIG_MEM_SOFT_DIRTY
24#define _PAGE_SOFT_DIRTY 0x00200 /* software: software dirty tracking */
25#else
26#define _PAGE_SOFT_DIRTY 0x00000
27#endif
28#define _PAGE_SPECIAL 0x00400 /* software: special page */
29
30
31#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
32#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
33/*
34 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
35 * Instead of fixing all of them, add an alternate define which
36 * maps CI pte mapping.
37 */
38#define _PAGE_NO_CACHE _PAGE_TOLERANT
39/*
40 * We support 57 bit real address in pte. Clear everything above 57, and
41 * every thing below PAGE_SHIFT;
42 */
43#define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK))
44/*
45 * set of bits not changed in pmd_modify. Even though we have hash specific bits
46 * in here, on radix we expect them to be zero.
47 */
48#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
49 _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \
50 _PAGE_SOFT_DIRTY)
51/*
52 * user access blocked by key
53 */
54#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY)
55#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ)
56#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \
57 _PAGE_RW | _PAGE_EXEC)
58/*
59 * No page size encoding in the linux PTE
60 */
61#define _PAGE_PSIZE 0
62/*
63 * _PAGE_CHG_MASK masks of bits that are to be preserved across
64 * pgprot changes
65 */
66#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
67 _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
68 _PAGE_SOFT_DIRTY)
69/*
70 * Mask of bits returned by pte_pgprot()
71 */
72#define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \
73 H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \
74 _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \
75 _PAGE_SOFT_DIRTY)
3dfcb315 76/*
2e873519
AK		 77 * We define 2 sets of base prot bits, one for basic pages (ie,
78 * cacheable kernel and user pages) and one for non cacheable
79 * pages. We always set _PAGE_COHERENT when SMP is enabled or
80 * the processor might need it for DMA coherency.
3dfcb315 81 */
2e873519
AK		 82#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
83#define _PAGE_BASE (_PAGE_BASE_NC)
84
85/* Permission masks used to generate the __P and __S table,
86 *
87 * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
88 *
89 * Write permissions imply read permissions for now (we could make write-only
90 * pages on BookE but we don't bother for now). Execute permission control is
91 * possible on platforms that define _PAGE_EXEC
92 *
93 * Note due to the way vm flags are laid out, the bits are XWR
94 */
95#define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED)
96#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW)
97#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC)
98#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ)
99#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
100#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ)
101#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC)
102
103#define __P000 PAGE_NONE
104#define __P001 PAGE_READONLY
105#define __P010 PAGE_COPY
106#define __P011 PAGE_COPY
107#define __P100 PAGE_READONLY_X
108#define __P101 PAGE_READONLY_X
109#define __P110 PAGE_COPY_X
110#define __P111 PAGE_COPY_X
111
112#define __S000 PAGE_NONE
113#define __S001 PAGE_READONLY
114#define __S010 PAGE_SHARED
115#define __S011 PAGE_SHARED
116#define __S100 PAGE_READONLY_X
117#define __S101 PAGE_READONLY_X
118#define __S110 PAGE_SHARED_X
119#define __S111 PAGE_SHARED_X
120
121/* Permission masks used for kernel mappings */
122#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
123#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
124 _PAGE_TOLERANT)
125#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
126 _PAGE_NON_IDEMPOTENT)
127#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
128#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
129#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
130
131/*
132 * Protection used for kernel text. We want the debuggers to be able to
133 * set breakpoints anywhere, so don't write protect the kernel text
134 * on platforms where such control is possible.
135 */
136#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \
137 defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
138#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
139#else
140#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
141#endif
142
143/* Make modules code happy. We don't set RO yet */
144#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
145#define PAGE_AGP (PAGE_KERNEL_NC)
3dfcb315 146
ab537dca 147#include <asm/book3s/64/hash.h>
3dfcb315
AK		 148#include <asm/barrier.h>
149
3dfcb315
AK		 150/*
151 * The second half of the kernel virtual space is used for IO mappings,
152 * it's itself carved into the PIO region (ISA and PHB IO space) and
153 * the ioremap space
154 *
155 * ISA_IO_BASE = KERN_IO_START, 64K reserved area
156 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces
157 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE
158 */
159#define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1))
160#define FULL_IO_SIZE 0x80000000ul
161#define ISA_IO_BASE (KERN_IO_START)
162#define ISA_IO_END (KERN_IO_START + 0x10000ul)
163#define PHB_IO_BASE (ISA_IO_END)
164#define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE)
165#define IOREMAP_BASE (PHB_IO_END)
166#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
167
3dfcb315
AK		 168#define vmemmap ((struct page *)VMEMMAP_BASE)
169
b0412ea9 170/* Advertise special mapping type for AGP */
b0412ea9
AK		 171#define HAVE_PAGE_AGP
172
173/* Advertise support for _PAGE_SPECIAL */
174#define __HAVE_ARCH_PTE_SPECIAL
175
3dfcb315
AK		 176#ifndef __ASSEMBLY__
177
178/*
179 * This is the default implementation of various PTE accessors, it's
180 * used in all cases except Book3S with 64K pages where we have a
181 * concept of sub-pages
182 */
183#ifndef __real_pte
184
3dfcb315
AK		 185#define __real_pte(e,p) ((real_pte_t){(e)})
186#define __rpte_to_pte(r) ((r).pte)
945537df 187#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
3dfcb315
AK		 188
189#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
190 do { \
191 index = 0; \
192 shift = mmu_psize_defs[psize].shift; \
193
194#define pte_iterate_hashed_end() } while(0)
195
196/*
197 * We expect this to be called only for user addresses or kernel virtual
198 * addresses other than the linear mapping.
199 */
200#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
201
202#endif /* __real_pte */
203
13f829a5
AK		 204/*
205 * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update.
206 * We currently remove entries from the hashtable regardless of whether
207 * the entry was young or dirty.
208 *
209 * We should be more intelligent about this but for the moment we override
210 * these functions and force a tlb flush unconditionally
211 * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same
212 * function for both hash and radix.
213 */
214static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
215 unsigned long addr, pte_t *ptep)
216{
217 unsigned long old;
218
219 if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0)
220 return 0;
221 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
222 return (old & _PAGE_ACCESSED) != 0;
223}
224
225#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
226#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
227({ \
228 int __r; \
229 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
230 __r; \
231})
232
233#define __HAVE_ARCH_PTEP_SET_WRPROTECT
234static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
235 pte_t *ptep)
236{
237
238 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
239 return;
240
241 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0);
242}
243
244static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
245 unsigned long addr, pte_t *ptep)
246{
247 if ((pte_val(*ptep) & _PAGE_WRITE) == 0)
248 return;
249
250 pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1);
251}
252
253#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
254static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
255 unsigned long addr, pte_t *ptep)
256{
257 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
258 return __pte(old);
259}
260
261static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
262 pte_t * ptep)
263{
264 pte_update(mm, addr, ptep, ~0UL, 0, 0);
265}
266static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);}
267static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); }
268static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); }
269static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); }
270static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
271
272#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
273static inline bool pte_soft_dirty(pte_t pte)
274{
275 return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
276}
277static inline pte_t pte_mksoft_dirty(pte_t pte)
278{
279 return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
280}
281
282static inline pte_t pte_clear_soft_dirty(pte_t pte)
283{
284 return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
285}
286#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
287
288#ifdef CONFIG_NUMA_BALANCING
289/*
290 * These work without NUMA balancing but the kernel does not care. See the
291 * comment in include/asm-generic/pgtable.h . On powerpc, this will only
292 * work for user pages and always return true for kernel pages.
293 */
294static inline int pte_protnone(pte_t pte)
295{
296 return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) ==
297 (_PAGE_PRESENT | _PAGE_PRIVILEGED);
298}
299#endif /* CONFIG_NUMA_BALANCING */
300
301static inline int pte_present(pte_t pte)
302{
303 return !!(pte_val(pte) & _PAGE_PRESENT);
304}
305/*
306 * Conversion functions: convert a page and protection to a page entry,
307 * and a page entry and page directory to the page they refer to.
308 *
309 * Even if PTEs can be unsigned long long, a PFN is always an unsigned
310 * long for now.
311 */
312static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
313{
314 return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) |
315 pgprot_val(pgprot));
316}
317
318static inline unsigned long pte_pfn(pte_t pte)
319{
320 return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT;
321}
322
323/* Generic modifiers for PTE bits */
324static inline pte_t pte_wrprotect(pte_t pte)
325{
326 return __pte(pte_val(pte) & ~_PAGE_WRITE);
327}
328
329static inline pte_t pte_mkclean(pte_t pte)
330{
331 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
332}
333
334static inline pte_t pte_mkold(pte_t pte)
335{
336 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
337}
338
339static inline pte_t pte_mkwrite(pte_t pte)
340{
341 /*
342 * write implies read, hence set both
343 */
344 return __pte(pte_val(pte) | _PAGE_RW);
345}
346
347static inline pte_t pte_mkdirty(pte_t pte)
348{
349 return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
350}
351
352static inline pte_t pte_mkyoung(pte_t pte)
353{
354 return __pte(pte_val(pte) | _PAGE_ACCESSED);
355}
356
357static inline pte_t pte_mkspecial(pte_t pte)
358{
359 return __pte(pte_val(pte) | _PAGE_SPECIAL);
360}
361
362static inline pte_t pte_mkhuge(pte_t pte)
363{
364 return pte;
365}
366
367static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
368{
369 /* FIXME!! check whether this need to be a conditional */
370 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
371}
372
373#define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)
374
375#define pgprot_noncached pgprot_noncached
376static inline pgprot_t pgprot_noncached(pgprot_t prot)
377{
378 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
379 _PAGE_NON_IDEMPOTENT);
380}
381
382#define pgprot_noncached_wc pgprot_noncached_wc
383static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
384{
385 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
386 _PAGE_TOLERANT);
387}
388
389#define pgprot_cached pgprot_cached
390static inline pgprot_t pgprot_cached(pgprot_t prot)
391{
392 return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));
393}
394
395#define pgprot_writecombine pgprot_writecombine
396static inline pgprot_t pgprot_writecombine(pgprot_t prot)
397{
398 return pgprot_noncached_wc(prot);
399}
400/*
401 * check a pte mapping have cache inhibited property
402 */
403static inline bool pte_ci(pte_t pte)
404{
405 unsigned long pte_v = pte_val(pte);
406
407 if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
408 ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
409 return true;
410 return false;
411}
412
f281b5d5
AK		 413static inline void pmd_set(pmd_t *pmdp, unsigned long val)
414{
415 *pmdp = __pmd(val);
416}
417
418static inline void pmd_clear(pmd_t *pmdp)
419{
420 *pmdp = __pmd(0);
421}
422
3dfcb315 423#define pmd_none(pmd) (!pmd_val(pmd))
3dfcb315 424#define pmd_present(pmd) (!pmd_none(pmd))
3dfcb315 425
f281b5d5
AK		 426static inline void pud_set(pud_t *pudp, unsigned long val)
427{
428 *pudp = __pud(val);
429}
430
431static inline void pud_clear(pud_t *pudp)
432{
433 *pudp = __pud(0);
434}
435
3dfcb315 436#define pud_none(pud) (!pud_val(pud))
3dfcb315 437#define pud_present(pud) (pud_val(pud) != 0)
3dfcb315
AK		 438
439extern struct page *pud_page(pud_t pud);
371352ca 440extern struct page *pmd_page(pmd_t pmd);
3dfcb315
AK		 441static inline pte_t pud_pte(pud_t pud)
442{
443 return __pte(pud_val(pud));
444}
445
446static inline pud_t pte_pud(pte_t pte)
447{
448 return __pud(pte_val(pte));
449}
450#define pud_write(pud) pte_write(pud_pte(pud))
3dfcb315 451#define pgd_write(pgd) pte_write(pgd_pte(pgd))
f281b5d5
AK		 452static inline void pgd_set(pgd_t *pgdp, unsigned long val)
453{
454 *pgdp = __pgd(val);
455}
3dfcb315 456
368ced78
AK		 457static inline void pgd_clear(pgd_t *pgdp)
458{
459 *pgdp = __pgd(0);
460}
461
462#define pgd_none(pgd) (!pgd_val(pgd))
463#define pgd_present(pgd) (!pgd_none(pgd))
464
465static inline pte_t pgd_pte(pgd_t pgd)
466{
467 return __pte(pgd_val(pgd));
468}
469
470static inline pgd_t pte_pgd(pte_t pte)
471{
472 return __pgd(pte_val(pte));
473}
474
475extern struct page *pgd_page(pgd_t pgd);
476
3dfcb315
AK		 477/*
478 * Find an entry in a page-table-directory. We combine the address region
479 * (the high order N bits) and the pgd portion of the address.
480 */
3dfcb315
AK		 481
482#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
483
368ced78
AK		 484#define pud_offset(pgdp, addr) \
485 (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr))
3dfcb315 486#define pmd_offset(pudp,addr) \
371352ca 487 (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr))
3dfcb315 488#define pte_offset_kernel(dir,addr) \
371352ca 489 (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr))
3dfcb315
AK		 490
491#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
492#define pte_unmap(pte) do { } while(0)
493
494/* to find an entry in a kernel page-table-directory */
495/* This now only contains the vmalloc pages */
496#define pgd_offset_k(address) pgd_offset(&init_mm, address)
3dfcb315
AK		 497
498#define pte_ERROR(e) \
499 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
500#define pmd_ERROR(e) \
501 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
368ced78
AK		 502#define pud_ERROR(e) \
503 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
3dfcb315
AK		 504#define pgd_ERROR(e) \
505 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
506
507/* Encode and de-code a swap entry */
508#define MAX_SWAPFILES_CHECK() do { \
509 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \
510 /* \
511 * Don't have overlapping bits with _PAGE_HPTEFLAGS \
512 * We filter HPTEFLAGS on set_pte. \
513 */ \
514 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \
7207f436 515 BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \
3dfcb315
AK		 516 } while (0)
517/*
518 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT;
519 */
520#define SWP_TYPE_BITS 5
521#define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \
522 & ((1UL << SWP_TYPE_BITS) - 1))
96270b1f 523#define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT)
3dfcb315 524#define __swp_entry(type, offset) ((swp_entry_t) { \
f1a9ae03 525 ((type) << _PAGE_BIT_SWAP_TYPE) \
96270b1f 526 | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)})
44734f23
AK		 527/*
528 * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
529 * swap type and offset we get from swap and convert that to pte to find a
530 * matching pte in linux page table.
531 * Clear bits not found in swap entries here.
532 */
533#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE })
534#define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE)
3dfcb315 535
e7bfc462
AK		 536static inline bool pte_user(pte_t pte)
537{
ac29c640 538 return !(pte_val(pte) & _PAGE_PRIVILEGED);
e7bfc462
AK		 539}
540
2f10f1a7 541#ifdef CONFIG_MEM_SOFT_DIRTY
7207f436 542#define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE))
2f10f1a7
HD		 543#else
544#define _PAGE_SWP_SOFT_DIRTY 0UL
545#endif /* CONFIG_MEM_SOFT_DIRTY */
546
547#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
7207f436
LD		 548static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
549{
550 return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
551}
552static inline bool pte_swp_soft_dirty(pte_t pte)
553{
554 return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
555}
556static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
557{
558 return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
559}
7207f436
LD		 560#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
561
ac29c640
AK		 562static inline bool check_pte_access(unsigned long access, unsigned long ptev)
563{
564 /*
565 * This check for _PAGE_RWX and _PAGE_PRESENT bits
566 */
567 if (access & ~ptev)
568 return false;
569 /*
570 * This check for access to privilege space
571 */
572 if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED))
573 return false;
574
575 return true;
576}
577
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AK		 578void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
579void pgtable_cache_init(void);
3dfcb315 580
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AK		 581struct page *realmode_pfn_to_page(unsigned long pfn);
582
3dfcb315 583#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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AK		 584extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
585extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
586extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
587extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
588 pmd_t *pmdp, pmd_t pmd);
589extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
590 pmd_t *pmd);
3dfcb315 591extern int has_transparent_hugepage(void);
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AK		 592#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
593
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AK		 594
595static inline pte_t pmd_pte(pmd_t pmd)
596{
597 return __pte(pmd_val(pmd));
598}
599
600static inline pmd_t pte_pmd(pte_t pte)
601{
602 return __pmd(pte_val(pte));
603}
604
605static inline pte_t *pmdp_ptep(pmd_t *pmd)
606{
607 return (pte_t *)pmd;
608}
609
610#define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd))
611#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
612#define pmd_young(pmd) pte_young(pmd_pte(pmd))
613#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
614#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
615#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
d5d6a443 616#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
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AK		 617#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
618#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
7207f436
LD		 619
620#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
621#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
622#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
623#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
624#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
625
1ca72129
AK		 626#ifdef CONFIG_NUMA_BALANCING
627static inline int pmd_protnone(pmd_t pmd)
628{
629 return pte_protnone(pmd_pte(pmd));
630}
631#endif /* CONFIG_NUMA_BALANCING */
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AK		 632
633#define __HAVE_ARCH_PMD_WRITE
634#define pmd_write(pmd) pte_write(pmd_pte(pmd))
635
636static inline pmd_t pmd_mkhuge(pmd_t pmd)
637{
945537df 638 return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE));
3dfcb315
AK		 639}
640
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AK		 641#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
642extern int pmdp_set_access_flags(struct vm_area_struct *vma,
643 unsigned long address, pmd_t *pmdp,
644 pmd_t entry, int dirty);
645
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AK		 646#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
647extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
648 unsigned long address, pmd_t *pmdp);
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AK		 649
650#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
651extern pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
652 unsigned long addr, pmd_t *pmdp);
653
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AK		 654extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
655 unsigned long address, pmd_t *pmdp);
656#define pmdp_collapse_flush pmdp_collapse_flush
657
658#define __HAVE_ARCH_PGTABLE_DEPOSIT
659extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
660 pgtable_t pgtable);
661#define __HAVE_ARCH_PGTABLE_WITHDRAW
662extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
663
664#define __HAVE_ARCH_PMDP_INVALIDATE
665extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
666 pmd_t *pmdp);
667
c777e2a8
AK		 668#define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE
669extern void pmdp_huge_split_prepare(struct vm_area_struct *vma,
670 unsigned long address, pmd_t *pmdp);
671
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AK		 672#define pmd_move_must_withdraw pmd_move_must_withdraw
673struct spinlock;
674static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
675 struct spinlock *old_pmd_ptl)
676{
677 /*
678 * Archs like ppc64 use pgtable to store per pmd
679 * specific information. So when we switch the pmd,
680 * we should also withdraw and deposit the pgtable
681 */
682 return true;
683}
684#endif /* __ASSEMBLY__ */
685#endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */
Linux 6.x block layer and io_uring tree(s)