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3dfcb315 AK |
1 | #ifndef _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ |
2 | #define _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ | |
2e873519 AK |
3 | |
4 | /* | |
5 | * Common bits between hash and Radix page table | |
6 | */ | |
7 | #define _PAGE_BIT_SWAP_TYPE 0 | |
8 | ||
9 | #define _PAGE_EXEC 0x00001 /* execute permission */ | |
10 | #define _PAGE_WRITE 0x00002 /* write access allowed */ | |
11 | #define _PAGE_READ 0x00004 /* read access allowed */ | |
12 | #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) | |
13 | #define _PAGE_RWX (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) | |
14 | #define _PAGE_PRIVILEGED 0x00008 /* kernel access only */ | |
15 | #define _PAGE_SAO 0x00010 /* Strong access order */ | |
16 | #define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */ | |
17 | #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */ | |
18 | #define _PAGE_DIRTY 0x00080 /* C: page changed */ | |
19 | #define _PAGE_ACCESSED 0x00100 /* R: page referenced */ | |
3dfcb315 | 20 | /* |
2e873519 | 21 | * Software bits |
3dfcb315 | 22 | */ |
69dfbaeb AK |
23 | #define _RPAGE_SW0 0x2000000000000000UL |
24 | #define _RPAGE_SW1 0x00800 | |
25 | #define _RPAGE_SW2 0x00400 | |
26 | #define _RPAGE_SW3 0x00200 | |
2e873519 | 27 | #ifdef CONFIG_MEM_SOFT_DIRTY |
69dfbaeb | 28 | #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ |
2e873519 AK |
29 | #else |
30 | #define _PAGE_SOFT_DIRTY 0x00000 | |
31 | #endif | |
69dfbaeb | 32 | #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ |
2e873519 AK |
33 | |
34 | ||
35 | #define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */ | |
36 | #define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */ | |
37 | /* | |
38 | * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE | |
39 | * Instead of fixing all of them, add an alternate define which | |
40 | * maps CI pte mapping. | |
41 | */ | |
42 | #define _PAGE_NO_CACHE _PAGE_TOLERANT | |
43 | /* | |
44 | * We support 57 bit real address in pte. Clear everything above 57, and | |
45 | * every thing below PAGE_SHIFT; | |
46 | */ | |
47 | #define PTE_RPN_MASK (((1UL << 57) - 1) & (PAGE_MASK)) | |
48 | /* | |
49 | * set of bits not changed in pmd_modify. Even though we have hash specific bits | |
50 | * in here, on radix we expect them to be zero. | |
51 | */ | |
52 | #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
53 | _PAGE_ACCESSED | H_PAGE_THP_HUGE | _PAGE_PTE | \ | |
54 | _PAGE_SOFT_DIRTY) | |
55 | /* | |
56 | * user access blocked by key | |
57 | */ | |
58 | #define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_RW | _PAGE_DIRTY) | |
59 | #define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_READ) | |
60 | #define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | \ | |
61 | _PAGE_RW | _PAGE_EXEC) | |
62 | /* | |
63 | * No page size encoding in the linux PTE | |
64 | */ | |
65 | #define _PAGE_PSIZE 0 | |
66 | /* | |
67 | * _PAGE_CHG_MASK masks of bits that are to be preserved across | |
68 | * pgprot changes | |
69 | */ | |
70 | #define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ | |
71 | _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \ | |
72 | _PAGE_SOFT_DIRTY) | |
73 | /* | |
74 | * Mask of bits returned by pte_pgprot() | |
75 | */ | |
76 | #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \ | |
77 | H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \ | |
78 | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \ | |
79 | _PAGE_SOFT_DIRTY) | |
3dfcb315 | 80 | /* |
2e873519 AK |
81 | * We define 2 sets of base prot bits, one for basic pages (ie, |
82 | * cacheable kernel and user pages) and one for non cacheable | |
83 | * pages. We always set _PAGE_COHERENT when SMP is enabled or | |
84 | * the processor might need it for DMA coherency. | |
3dfcb315 | 85 | */ |
2e873519 AK |
86 | #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE) |
87 | #define _PAGE_BASE (_PAGE_BASE_NC) | |
88 | ||
89 | /* Permission masks used to generate the __P and __S table, | |
90 | * | |
91 | * Note:__pgprot is defined in arch/powerpc/include/asm/page.h | |
92 | * | |
93 | * Write permissions imply read permissions for now (we could make write-only | |
94 | * pages on BookE but we don't bother for now). Execute permission control is | |
95 | * possible on platforms that define _PAGE_EXEC | |
96 | * | |
97 | * Note due to the way vm flags are laid out, the bits are XWR | |
98 | */ | |
99 | #define PAGE_NONE __pgprot(_PAGE_BASE | _PAGE_PRIVILEGED) | |
100 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW) | |
101 | #define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_EXEC) | |
102 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_READ) | |
103 | #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
104 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_READ) | |
105 | #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) | |
106 | ||
107 | #define __P000 PAGE_NONE | |
108 | #define __P001 PAGE_READONLY | |
109 | #define __P010 PAGE_COPY | |
110 | #define __P011 PAGE_COPY | |
111 | #define __P100 PAGE_READONLY_X | |
112 | #define __P101 PAGE_READONLY_X | |
113 | #define __P110 PAGE_COPY_X | |
114 | #define __P111 PAGE_COPY_X | |
115 | ||
116 | #define __S000 PAGE_NONE | |
117 | #define __S001 PAGE_READONLY | |
118 | #define __S010 PAGE_SHARED | |
119 | #define __S011 PAGE_SHARED | |
120 | #define __S100 PAGE_READONLY_X | |
121 | #define __S101 PAGE_READONLY_X | |
122 | #define __S110 PAGE_SHARED_X | |
123 | #define __S111 PAGE_SHARED_X | |
124 | ||
125 | /* Permission masks used for kernel mappings */ | |
126 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) | |
127 | #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
128 | _PAGE_TOLERANT) | |
129 | #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \ | |
130 | _PAGE_NON_IDEMPOTENT) | |
131 | #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) | |
132 | #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) | |
133 | #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) | |
134 | ||
135 | /* | |
136 | * Protection used for kernel text. We want the debuggers to be able to | |
137 | * set breakpoints anywhere, so don't write protect the kernel text | |
138 | * on platforms where such control is possible. | |
139 | */ | |
140 | #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) || \ | |
141 | defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE) | |
142 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_X | |
143 | #else | |
144 | #define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX | |
145 | #endif | |
146 | ||
147 | /* Make modules code happy. We don't set RO yet */ | |
148 | #define PAGE_KERNEL_EXEC PAGE_KERNEL_X | |
149 | #define PAGE_AGP (PAGE_KERNEL_NC) | |
3dfcb315 | 150 | |
dd1842a2 AK |
151 | #ifndef __ASSEMBLY__ |
152 | /* | |
153 | * page table defines | |
154 | */ | |
155 | extern unsigned long __pte_index_size; | |
156 | extern unsigned long __pmd_index_size; | |
157 | extern unsigned long __pud_index_size; | |
158 | extern unsigned long __pgd_index_size; | |
159 | extern unsigned long __pmd_cache_index; | |
160 | #define PTE_INDEX_SIZE __pte_index_size | |
161 | #define PMD_INDEX_SIZE __pmd_index_size | |
162 | #define PUD_INDEX_SIZE __pud_index_size | |
163 | #define PGD_INDEX_SIZE __pgd_index_size | |
164 | #define PMD_CACHE_INDEX __pmd_cache_index | |
165 | /* | |
166 | * Because of use of pte fragments and THP, size of page table | |
167 | * are not always derived out of index size above. | |
168 | */ | |
169 | extern unsigned long __pte_table_size; | |
170 | extern unsigned long __pmd_table_size; | |
171 | extern unsigned long __pud_table_size; | |
172 | extern unsigned long __pgd_table_size; | |
173 | #define PTE_TABLE_SIZE __pte_table_size | |
174 | #define PMD_TABLE_SIZE __pmd_table_size | |
175 | #define PUD_TABLE_SIZE __pud_table_size | |
176 | #define PGD_TABLE_SIZE __pgd_table_size | |
a2f41eb9 AK |
177 | |
178 | extern unsigned long __pmd_val_bits; | |
179 | extern unsigned long __pud_val_bits; | |
180 | extern unsigned long __pgd_val_bits; | |
181 | #define PMD_VAL_BITS __pmd_val_bits | |
182 | #define PUD_VAL_BITS __pud_val_bits | |
183 | #define PGD_VAL_BITS __pgd_val_bits | |
5ed7ecd0 AK |
184 | |
185 | extern unsigned long __pte_frag_nr; | |
186 | #define PTE_FRAG_NR __pte_frag_nr | |
187 | extern unsigned long __pte_frag_size_shift; | |
188 | #define PTE_FRAG_SIZE_SHIFT __pte_frag_size_shift | |
189 | #define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT) | |
dd1842a2 AK |
190 | /* |
191 | * Pgtable size used by swapper, init in asm code | |
dd1842a2 | 192 | */ |
a2f41eb9 | 193 | #define MAX_PGD_TABLE_SIZE (sizeof(pgd_t) << RADIX_PGD_INDEX_SIZE) |
dd1842a2 AK |
194 | |
195 | #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) | |
196 | #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) | |
197 | #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) | |
198 | #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) | |
199 | ||
200 | /* PMD_SHIFT determines what a second-level page table entry can map */ | |
201 | #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) | |
202 | #define PMD_SIZE (1UL << PMD_SHIFT) | |
203 | #define PMD_MASK (~(PMD_SIZE-1)) | |
204 | ||
205 | /* PUD_SHIFT determines what a third-level page table entry can map */ | |
206 | #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) | |
207 | #define PUD_SIZE (1UL << PUD_SHIFT) | |
208 | #define PUD_MASK (~(PUD_SIZE-1)) | |
209 | ||
210 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
211 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) | |
212 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | |
213 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
214 | ||
215 | /* Bits to mask out from a PMD to get to the PTE page */ | |
216 | #define PMD_MASKED_BITS 0xc0000000000000ffUL | |
217 | /* Bits to mask out from a PUD to get to the PMD page */ | |
218 | #define PUD_MASKED_BITS 0xc0000000000000ffUL | |
219 | /* Bits to mask out from a PGD to get to the PUD page */ | |
220 | #define PGD_MASKED_BITS 0xc0000000000000ffUL | |
d6a9996e AK |
221 | |
222 | extern unsigned long __vmalloc_start; | |
223 | extern unsigned long __vmalloc_end; | |
224 | #define VMALLOC_START __vmalloc_start | |
225 | #define VMALLOC_END __vmalloc_end | |
226 | ||
227 | extern unsigned long __kernel_virt_start; | |
228 | extern unsigned long __kernel_virt_size; | |
229 | #define KERN_VIRT_START __kernel_virt_start | |
230 | #define KERN_VIRT_SIZE __kernel_virt_size | |
231 | extern struct page *vmemmap; | |
232 | extern unsigned long ioremap_bot; | |
bfa37087 | 233 | extern unsigned long pci_io_base; |
dd1842a2 | 234 | #endif /* __ASSEMBLY__ */ |
3dfcb315 | 235 | |
ab537dca | 236 | #include <asm/book3s/64/hash.h> |
b0b5e9b1 | 237 | #include <asm/book3s/64/radix.h> |
3dfcb315 | 238 | |
a9252aae AK |
239 | #ifdef CONFIG_PPC_64K_PAGES |
240 | #include <asm/book3s/64/pgtable-64k.h> | |
241 | #else | |
242 | #include <asm/book3s/64/pgtable-4k.h> | |
243 | #endif | |
244 | ||
3dfcb315 | 245 | #include <asm/barrier.h> |
3dfcb315 AK |
246 | /* |
247 | * The second half of the kernel virtual space is used for IO mappings, | |
248 | * it's itself carved into the PIO region (ISA and PHB IO space) and | |
249 | * the ioremap space | |
250 | * | |
251 | * ISA_IO_BASE = KERN_IO_START, 64K reserved area | |
252 | * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces | |
253 | * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE | |
254 | */ | |
255 | #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) | |
256 | #define FULL_IO_SIZE 0x80000000ul | |
257 | #define ISA_IO_BASE (KERN_IO_START) | |
258 | #define ISA_IO_END (KERN_IO_START + 0x10000ul) | |
259 | #define PHB_IO_BASE (ISA_IO_END) | |
260 | #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) | |
261 | #define IOREMAP_BASE (PHB_IO_END) | |
262 | #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) | |
263 | ||
b0412ea9 | 264 | /* Advertise special mapping type for AGP */ |
b0412ea9 AK |
265 | #define HAVE_PAGE_AGP |
266 | ||
267 | /* Advertise support for _PAGE_SPECIAL */ | |
268 | #define __HAVE_ARCH_PTE_SPECIAL | |
269 | ||
3dfcb315 AK |
270 | #ifndef __ASSEMBLY__ |
271 | ||
272 | /* | |
273 | * This is the default implementation of various PTE accessors, it's | |
274 | * used in all cases except Book3S with 64K pages where we have a | |
275 | * concept of sub-pages | |
276 | */ | |
277 | #ifndef __real_pte | |
278 | ||
3dfcb315 AK |
279 | #define __real_pte(e,p) ((real_pte_t){(e)}) |
280 | #define __rpte_to_pte(r) ((r).pte) | |
945537df | 281 | #define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT) |
3dfcb315 AK |
282 | |
283 | #define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \ | |
284 | do { \ | |
285 | index = 0; \ | |
286 | shift = mmu_psize_defs[psize].shift; \ | |
287 | ||
288 | #define pte_iterate_hashed_end() } while(0) | |
289 | ||
290 | /* | |
291 | * We expect this to be called only for user addresses or kernel virtual | |
292 | * addresses other than the linear mapping. | |
293 | */ | |
294 | #define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K | |
295 | ||
296 | #endif /* __real_pte */ | |
297 | ||
ac94ac79 AK |
298 | static inline unsigned long pte_update(struct mm_struct *mm, unsigned long addr, |
299 | pte_t *ptep, unsigned long clr, | |
300 | unsigned long set, int huge) | |
301 | { | |
302 | if (radix_enabled()) | |
303 | return radix__pte_update(mm, addr, ptep, clr, set, huge); | |
304 | return hash__pte_update(mm, addr, ptep, clr, set, huge); | |
305 | } | |
13f829a5 AK |
306 | /* |
307 | * For hash even if we have _PAGE_ACCESSED = 0, we do a pte_update. | |
308 | * We currently remove entries from the hashtable regardless of whether | |
309 | * the entry was young or dirty. | |
310 | * | |
311 | * We should be more intelligent about this but for the moment we override | |
312 | * these functions and force a tlb flush unconditionally | |
313 | * For radix: H_PAGE_HASHPTE should be zero. Hence we can use the same | |
314 | * function for both hash and radix. | |
315 | */ | |
316 | static inline int __ptep_test_and_clear_young(struct mm_struct *mm, | |
317 | unsigned long addr, pte_t *ptep) | |
318 | { | |
319 | unsigned long old; | |
320 | ||
321 | if ((pte_val(*ptep) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
322 | return 0; | |
323 | old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); | |
324 | return (old & _PAGE_ACCESSED) != 0; | |
325 | } | |
326 | ||
327 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
328 | #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ | |
329 | ({ \ | |
330 | int __r; \ | |
331 | __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ | |
332 | __r; \ | |
333 | }) | |
334 | ||
335 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
336 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
337 | pte_t *ptep) | |
338 | { | |
339 | ||
340 | if ((pte_val(*ptep) & _PAGE_WRITE) == 0) | |
341 | return; | |
342 | ||
343 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 0); | |
344 | } | |
345 | ||
346 | static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, | |
347 | unsigned long addr, pte_t *ptep) | |
348 | { | |
349 | if ((pte_val(*ptep) & _PAGE_WRITE) == 0) | |
350 | return; | |
351 | ||
352 | pte_update(mm, addr, ptep, _PAGE_WRITE, 0, 1); | |
353 | } | |
354 | ||
355 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
356 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
357 | unsigned long addr, pte_t *ptep) | |
358 | { | |
359 | unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
360 | return __pte(old); | |
361 | } | |
362 | ||
363 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
364 | pte_t * ptep) | |
365 | { | |
366 | pte_update(mm, addr, ptep, ~0UL, 0, 0); | |
367 | } | |
368 | static inline int pte_write(pte_t pte) { return !!(pte_val(pte) & _PAGE_WRITE);} | |
369 | static inline int pte_dirty(pte_t pte) { return !!(pte_val(pte) & _PAGE_DIRTY); } | |
370 | static inline int pte_young(pte_t pte) { return !!(pte_val(pte) & _PAGE_ACCESSED); } | |
371 | static inline int pte_special(pte_t pte) { return !!(pte_val(pte) & _PAGE_SPECIAL); } | |
372 | static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } | |
373 | ||
374 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
375 | static inline bool pte_soft_dirty(pte_t pte) | |
376 | { | |
377 | return !!(pte_val(pte) & _PAGE_SOFT_DIRTY); | |
378 | } | |
379 | static inline pte_t pte_mksoft_dirty(pte_t pte) | |
380 | { | |
381 | return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY); | |
382 | } | |
383 | ||
384 | static inline pte_t pte_clear_soft_dirty(pte_t pte) | |
385 | { | |
386 | return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY); | |
387 | } | |
388 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
389 | ||
390 | #ifdef CONFIG_NUMA_BALANCING | |
391 | /* | |
392 | * These work without NUMA balancing but the kernel does not care. See the | |
393 | * comment in include/asm-generic/pgtable.h . On powerpc, this will only | |
394 | * work for user pages and always return true for kernel pages. | |
395 | */ | |
396 | static inline int pte_protnone(pte_t pte) | |
397 | { | |
398 | return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PRIVILEGED)) == | |
399 | (_PAGE_PRESENT | _PAGE_PRIVILEGED); | |
400 | } | |
401 | #endif /* CONFIG_NUMA_BALANCING */ | |
402 | ||
403 | static inline int pte_present(pte_t pte) | |
404 | { | |
405 | return !!(pte_val(pte) & _PAGE_PRESENT); | |
406 | } | |
407 | /* | |
408 | * Conversion functions: convert a page and protection to a page entry, | |
409 | * and a page entry and page directory to the page they refer to. | |
410 | * | |
411 | * Even if PTEs can be unsigned long long, a PFN is always an unsigned | |
412 | * long for now. | |
413 | */ | |
414 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) | |
415 | { | |
416 | return __pte((((pte_basic_t)(pfn) << PAGE_SHIFT) & PTE_RPN_MASK) | | |
417 | pgprot_val(pgprot)); | |
418 | } | |
419 | ||
420 | static inline unsigned long pte_pfn(pte_t pte) | |
421 | { | |
422 | return (pte_val(pte) & PTE_RPN_MASK) >> PAGE_SHIFT; | |
423 | } | |
424 | ||
425 | /* Generic modifiers for PTE bits */ | |
426 | static inline pte_t pte_wrprotect(pte_t pte) | |
427 | { | |
428 | return __pte(pte_val(pte) & ~_PAGE_WRITE); | |
429 | } | |
430 | ||
431 | static inline pte_t pte_mkclean(pte_t pte) | |
432 | { | |
433 | return __pte(pte_val(pte) & ~_PAGE_DIRTY); | |
434 | } | |
435 | ||
436 | static inline pte_t pte_mkold(pte_t pte) | |
437 | { | |
438 | return __pte(pte_val(pte) & ~_PAGE_ACCESSED); | |
439 | } | |
440 | ||
441 | static inline pte_t pte_mkwrite(pte_t pte) | |
442 | { | |
443 | /* | |
444 | * write implies read, hence set both | |
445 | */ | |
446 | return __pte(pte_val(pte) | _PAGE_RW); | |
447 | } | |
448 | ||
449 | static inline pte_t pte_mkdirty(pte_t pte) | |
450 | { | |
451 | return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY); | |
452 | } | |
453 | ||
454 | static inline pte_t pte_mkyoung(pte_t pte) | |
455 | { | |
456 | return __pte(pte_val(pte) | _PAGE_ACCESSED); | |
457 | } | |
458 | ||
459 | static inline pte_t pte_mkspecial(pte_t pte) | |
460 | { | |
461 | return __pte(pte_val(pte) | _PAGE_SPECIAL); | |
462 | } | |
463 | ||
464 | static inline pte_t pte_mkhuge(pte_t pte) | |
465 | { | |
466 | return pte; | |
467 | } | |
468 | ||
469 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) | |
470 | { | |
471 | /* FIXME!! check whether this need to be a conditional */ | |
472 | return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); | |
473 | } | |
474 | ||
34fbadd8 AK |
475 | static inline bool pte_user(pte_t pte) |
476 | { | |
477 | return !(pte_val(pte) & _PAGE_PRIVILEGED); | |
478 | } | |
479 | ||
480 | /* Encode and de-code a swap entry */ | |
481 | #define MAX_SWAPFILES_CHECK() do { \ | |
482 | BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ | |
483 | /* \ | |
484 | * Don't have overlapping bits with _PAGE_HPTEFLAGS \ | |
485 | * We filter HPTEFLAGS on set_pte. \ | |
486 | */ \ | |
487 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ | |
488 | BUILD_BUG_ON(_PAGE_HPTEFLAGS & _PAGE_SWP_SOFT_DIRTY); \ | |
489 | } while (0) | |
490 | /* | |
491 | * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; | |
492 | */ | |
493 | #define SWP_TYPE_BITS 5 | |
494 | #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ | |
495 | & ((1UL << SWP_TYPE_BITS) - 1)) | |
496 | #define __swp_offset(x) (((x).val & PTE_RPN_MASK) >> PAGE_SHIFT) | |
497 | #define __swp_entry(type, offset) ((swp_entry_t) { \ | |
498 | ((type) << _PAGE_BIT_SWAP_TYPE) \ | |
499 | | (((offset) << PAGE_SHIFT) & PTE_RPN_MASK)}) | |
500 | /* | |
501 | * swp_entry_t must be independent of pte bits. We build a swp_entry_t from | |
502 | * swap type and offset we get from swap and convert that to pte to find a | |
503 | * matching pte in linux page table. | |
504 | * Clear bits not found in swap entries here. | |
505 | */ | |
506 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) & ~_PAGE_PTE }) | |
507 | #define __swp_entry_to_pte(x) __pte((x).val | _PAGE_PTE) | |
508 | ||
509 | #ifdef CONFIG_MEM_SOFT_DIRTY | |
510 | #define _PAGE_SWP_SOFT_DIRTY (1UL << (SWP_TYPE_BITS + _PAGE_BIT_SWAP_TYPE)) | |
511 | #else | |
512 | #define _PAGE_SWP_SOFT_DIRTY 0UL | |
513 | #endif /* CONFIG_MEM_SOFT_DIRTY */ | |
514 | ||
515 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
516 | static inline pte_t pte_swp_mksoft_dirty(pte_t pte) | |
517 | { | |
518 | return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY); | |
519 | } | |
520 | static inline bool pte_swp_soft_dirty(pte_t pte) | |
521 | { | |
522 | return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY); | |
523 | } | |
524 | static inline pte_t pte_swp_clear_soft_dirty(pte_t pte) | |
525 | { | |
526 | return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY); | |
527 | } | |
528 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
529 | ||
530 | static inline bool check_pte_access(unsigned long access, unsigned long ptev) | |
531 | { | |
532 | /* | |
533 | * This check for _PAGE_RWX and _PAGE_PRESENT bits | |
534 | */ | |
535 | if (access & ~ptev) | |
536 | return false; | |
537 | /* | |
538 | * This check for access to privilege space | |
539 | */ | |
540 | if ((access & _PAGE_PRIVILEGED) != (ptev & _PAGE_PRIVILEGED)) | |
541 | return false; | |
542 | ||
543 | return true; | |
544 | } | |
ac94ac79 AK |
545 | /* |
546 | * Generic functions with hash/radix callbacks | |
547 | */ | |
548 | ||
549 | static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) | |
550 | { | |
551 | if (radix_enabled()) | |
552 | return radix__ptep_set_access_flags(ptep, entry); | |
553 | return hash__ptep_set_access_flags(ptep, entry); | |
554 | } | |
555 | ||
556 | #define __HAVE_ARCH_PTE_SAME | |
557 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
558 | { | |
559 | if (radix_enabled()) | |
560 | return radix__pte_same(pte_a, pte_b); | |
561 | return hash__pte_same(pte_a, pte_b); | |
562 | } | |
563 | ||
564 | static inline int pte_none(pte_t pte) | |
565 | { | |
566 | if (radix_enabled()) | |
567 | return radix__pte_none(pte); | |
568 | return hash__pte_none(pte); | |
569 | } | |
570 | ||
571 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, | |
572 | pte_t *ptep, pte_t pte, int percpu) | |
573 | { | |
574 | if (radix_enabled()) | |
575 | return radix__set_pte_at(mm, addr, ptep, pte, percpu); | |
576 | return hash__set_pte_at(mm, addr, ptep, pte, percpu); | |
577 | } | |
34fbadd8 | 578 | |
13f829a5 AK |
579 | #define _PAGE_CACHE_CTL (_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT) |
580 | ||
581 | #define pgprot_noncached pgprot_noncached | |
582 | static inline pgprot_t pgprot_noncached(pgprot_t prot) | |
583 | { | |
584 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
585 | _PAGE_NON_IDEMPOTENT); | |
586 | } | |
587 | ||
588 | #define pgprot_noncached_wc pgprot_noncached_wc | |
589 | static inline pgprot_t pgprot_noncached_wc(pgprot_t prot) | |
590 | { | |
591 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | | |
592 | _PAGE_TOLERANT); | |
593 | } | |
594 | ||
595 | #define pgprot_cached pgprot_cached | |
596 | static inline pgprot_t pgprot_cached(pgprot_t prot) | |
597 | { | |
598 | return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL)); | |
599 | } | |
600 | ||
601 | #define pgprot_writecombine pgprot_writecombine | |
602 | static inline pgprot_t pgprot_writecombine(pgprot_t prot) | |
603 | { | |
604 | return pgprot_noncached_wc(prot); | |
605 | } | |
606 | /* | |
607 | * check a pte mapping have cache inhibited property | |
608 | */ | |
609 | static inline bool pte_ci(pte_t pte) | |
610 | { | |
611 | unsigned long pte_v = pte_val(pte); | |
612 | ||
613 | if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) || | |
614 | ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)) | |
615 | return true; | |
616 | return false; | |
617 | } | |
618 | ||
f281b5d5 AK |
619 | static inline void pmd_set(pmd_t *pmdp, unsigned long val) |
620 | { | |
621 | *pmdp = __pmd(val); | |
622 | } | |
623 | ||
624 | static inline void pmd_clear(pmd_t *pmdp) | |
625 | { | |
626 | *pmdp = __pmd(0); | |
627 | } | |
628 | ||
3dfcb315 | 629 | #define pmd_none(pmd) (!pmd_val(pmd)) |
3dfcb315 | 630 | #define pmd_present(pmd) (!pmd_none(pmd)) |
3dfcb315 | 631 | |
ac94ac79 AK |
632 | static inline int pmd_bad(pmd_t pmd) |
633 | { | |
634 | if (radix_enabled()) | |
635 | return radix__pmd_bad(pmd); | |
636 | return hash__pmd_bad(pmd); | |
637 | } | |
638 | ||
f281b5d5 AK |
639 | static inline void pud_set(pud_t *pudp, unsigned long val) |
640 | { | |
641 | *pudp = __pud(val); | |
642 | } | |
643 | ||
644 | static inline void pud_clear(pud_t *pudp) | |
645 | { | |
646 | *pudp = __pud(0); | |
647 | } | |
648 | ||
3dfcb315 | 649 | #define pud_none(pud) (!pud_val(pud)) |
3dfcb315 | 650 | #define pud_present(pud) (pud_val(pud) != 0) |
3dfcb315 AK |
651 | |
652 | extern struct page *pud_page(pud_t pud); | |
371352ca | 653 | extern struct page *pmd_page(pmd_t pmd); |
3dfcb315 AK |
654 | static inline pte_t pud_pte(pud_t pud) |
655 | { | |
656 | return __pte(pud_val(pud)); | |
657 | } | |
658 | ||
659 | static inline pud_t pte_pud(pte_t pte) | |
660 | { | |
661 | return __pud(pte_val(pte)); | |
662 | } | |
663 | #define pud_write(pud) pte_write(pud_pte(pud)) | |
ac94ac79 AK |
664 | |
665 | static inline int pud_bad(pud_t pud) | |
666 | { | |
667 | if (radix_enabled()) | |
668 | return radix__pud_bad(pud); | |
669 | return hash__pud_bad(pud); | |
670 | } | |
671 | ||
672 | ||
3dfcb315 | 673 | #define pgd_write(pgd) pte_write(pgd_pte(pgd)) |
f281b5d5 AK |
674 | static inline void pgd_set(pgd_t *pgdp, unsigned long val) |
675 | { | |
676 | *pgdp = __pgd(val); | |
677 | } | |
3dfcb315 | 678 | |
368ced78 AK |
679 | static inline void pgd_clear(pgd_t *pgdp) |
680 | { | |
681 | *pgdp = __pgd(0); | |
682 | } | |
683 | ||
684 | #define pgd_none(pgd) (!pgd_val(pgd)) | |
685 | #define pgd_present(pgd) (!pgd_none(pgd)) | |
686 | ||
687 | static inline pte_t pgd_pte(pgd_t pgd) | |
688 | { | |
689 | return __pte(pgd_val(pgd)); | |
690 | } | |
691 | ||
692 | static inline pgd_t pte_pgd(pte_t pte) | |
693 | { | |
694 | return __pgd(pte_val(pte)); | |
695 | } | |
696 | ||
ac94ac79 AK |
697 | static inline int pgd_bad(pgd_t pgd) |
698 | { | |
699 | if (radix_enabled()) | |
700 | return radix__pgd_bad(pgd); | |
701 | return hash__pgd_bad(pgd); | |
702 | } | |
703 | ||
368ced78 AK |
704 | extern struct page *pgd_page(pgd_t pgd); |
705 | ||
aba480e1 AK |
706 | /* Pointers in the page table tree are physical addresses */ |
707 | #define __pgtable_ptr_val(ptr) __pa(ptr) | |
708 | ||
709 | #define pmd_page_vaddr(pmd) __va(pmd_val(pmd) & ~PMD_MASKED_BITS) | |
710 | #define pud_page_vaddr(pud) __va(pud_val(pud) & ~PUD_MASKED_BITS) | |
711 | #define pgd_page_vaddr(pgd) __va(pgd_val(pgd) & ~PGD_MASKED_BITS) | |
712 | ||
713 | #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) | |
714 | #define pud_index(address) (((address) >> (PUD_SHIFT)) & (PTRS_PER_PUD - 1)) | |
715 | #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1)) | |
716 | #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1)) | |
717 | ||
3dfcb315 AK |
718 | /* |
719 | * Find an entry in a page-table-directory. We combine the address region | |
720 | * (the high order N bits) and the pgd portion of the address. | |
721 | */ | |
3dfcb315 AK |
722 | |
723 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
724 | ||
368ced78 AK |
725 | #define pud_offset(pgdp, addr) \ |
726 | (((pud_t *) pgd_page_vaddr(*(pgdp))) + pud_index(addr)) | |
3dfcb315 | 727 | #define pmd_offset(pudp,addr) \ |
371352ca | 728 | (((pmd_t *) pud_page_vaddr(*(pudp))) + pmd_index(addr)) |
3dfcb315 | 729 | #define pte_offset_kernel(dir,addr) \ |
371352ca | 730 | (((pte_t *) pmd_page_vaddr(*(dir))) + pte_index(addr)) |
3dfcb315 AK |
731 | |
732 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
733 | #define pte_unmap(pte) do { } while(0) | |
734 | ||
735 | /* to find an entry in a kernel page-table-directory */ | |
736 | /* This now only contains the vmalloc pages */ | |
737 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
3dfcb315 AK |
738 | |
739 | #define pte_ERROR(e) \ | |
740 | pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) | |
741 | #define pmd_ERROR(e) \ | |
742 | pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) | |
368ced78 AK |
743 | #define pud_ERROR(e) \ |
744 | pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) | |
3dfcb315 AK |
745 | #define pgd_ERROR(e) \ |
746 | pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | |
747 | ||
3dfcb315 AK |
748 | void pgtable_cache_add(unsigned shift, void (*ctor)(void *)); |
749 | void pgtable_cache_init(void); | |
2f10f1a7 | 750 | |
31a14fae AK |
751 | static inline int map_kernel_page(unsigned long ea, unsigned long pa, |
752 | unsigned long flags) | |
7207f436 | 753 | { |
d9225ad9 AK |
754 | if (radix_enabled()) { |
755 | #if defined(CONFIG_PPC_RADIX_MMU) && defined(DEBUG_VM) | |
756 | unsigned long page_size = 1 << mmu_psize_defs[mmu_io_psize].shift; | |
757 | WARN((page_size != PAGE_SIZE), "I/O page size != PAGE_SIZE"); | |
758 | #endif | |
759 | return radix__map_kernel_page(ea, pa, __pgprot(flags), PAGE_SIZE); | |
760 | } | |
31a14fae | 761 | return hash__map_kernel_page(ea, pa, flags); |
7207f436 | 762 | } |
31a14fae AK |
763 | |
764 | static inline int __meminit vmemmap_create_mapping(unsigned long start, | |
765 | unsigned long page_size, | |
766 | unsigned long phys) | |
7207f436 | 767 | { |
d9225ad9 AK |
768 | if (radix_enabled()) |
769 | return radix__vmemmap_create_mapping(start, page_size, phys); | |
31a14fae | 770 | return hash__vmemmap_create_mapping(start, page_size, phys); |
7207f436 | 771 | } |
31a14fae AK |
772 | |
773 | #ifdef CONFIG_MEMORY_HOTPLUG | |
774 | static inline void vmemmap_remove_mapping(unsigned long start, | |
775 | unsigned long page_size) | |
7207f436 | 776 | { |
d9225ad9 AK |
777 | if (radix_enabled()) |
778 | return radix__vmemmap_remove_mapping(start, page_size); | |
31a14fae | 779 | return hash__vmemmap_remove_mapping(start, page_size); |
7207f436 | 780 | } |
31a14fae | 781 | #endif |
3dfcb315 AK |
782 | struct page *realmode_pfn_to_page(unsigned long pfn); |
783 | ||
3dfcb315 AK |
784 | static inline pte_t pmd_pte(pmd_t pmd) |
785 | { | |
786 | return __pte(pmd_val(pmd)); | |
787 | } | |
788 | ||
789 | static inline pmd_t pte_pmd(pte_t pte) | |
790 | { | |
791 | return __pmd(pte_val(pte)); | |
792 | } | |
793 | ||
794 | static inline pte_t *pmdp_ptep(pmd_t *pmd) | |
795 | { | |
796 | return (pte_t *)pmd; | |
797 | } | |
3dfcb315 AK |
798 | #define pmd_pfn(pmd) pte_pfn(pmd_pte(pmd)) |
799 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) | |
800 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) | |
801 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) | |
802 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
803 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) | |
d5d6a443 | 804 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
3dfcb315 AK |
805 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) |
806 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
7207f436 LD |
807 | |
808 | #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY | |
809 | #define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd)) | |
810 | #define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd))) | |
811 | #define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd))) | |
812 | #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */ | |
813 | ||
1ca72129 AK |
814 | #ifdef CONFIG_NUMA_BALANCING |
815 | static inline int pmd_protnone(pmd_t pmd) | |
816 | { | |
817 | return pte_protnone(pmd_pte(pmd)); | |
818 | } | |
819 | #endif /* CONFIG_NUMA_BALANCING */ | |
3dfcb315 AK |
820 | |
821 | #define __HAVE_ARCH_PMD_WRITE | |
822 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) | |
823 | ||
6a1ea362 AK |
824 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
825 | extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot); | |
826 | extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot); | |
827 | extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot); | |
828 | extern void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
829 | pmd_t *pmdp, pmd_t pmd); | |
830 | extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, | |
831 | pmd_t *pmd); | |
3df33f12 AK |
832 | extern int hash__has_transparent_hugepage(void); |
833 | static inline int has_transparent_hugepage(void) | |
834 | { | |
bde3eb62 AK |
835 | if (radix_enabled()) |
836 | return radix__has_transparent_hugepage(); | |
3df33f12 AK |
837 | return hash__has_transparent_hugepage(); |
838 | } | |
c04a5880 | 839 | #define has_transparent_hugepage has_transparent_hugepage |
6a1ea362 | 840 | |
3df33f12 AK |
841 | static inline unsigned long |
842 | pmd_hugepage_update(struct mm_struct *mm, unsigned long addr, pmd_t *pmdp, | |
843 | unsigned long clr, unsigned long set) | |
3dfcb315 | 844 | { |
bde3eb62 AK |
845 | if (radix_enabled()) |
846 | return radix__pmd_hugepage_update(mm, addr, pmdp, clr, set); | |
3df33f12 AK |
847 | return hash__pmd_hugepage_update(mm, addr, pmdp, clr, set); |
848 | } | |
849 | ||
850 | static inline int pmd_large(pmd_t pmd) | |
851 | { | |
852 | return !!(pmd_val(pmd) & _PAGE_PTE); | |
853 | } | |
854 | ||
855 | static inline pmd_t pmd_mknotpresent(pmd_t pmd) | |
856 | { | |
857 | return __pmd(pmd_val(pmd) & ~_PAGE_PRESENT); | |
858 | } | |
859 | /* | |
860 | * For radix we should always find H_PAGE_HASHPTE zero. Hence | |
861 | * the below will work for radix too | |
862 | */ | |
863 | static inline int __pmdp_test_and_clear_young(struct mm_struct *mm, | |
864 | unsigned long addr, pmd_t *pmdp) | |
865 | { | |
866 | unsigned long old; | |
867 | ||
868 | if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | H_PAGE_HASHPTE)) == 0) | |
869 | return 0; | |
870 | old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED, 0); | |
871 | return ((old & _PAGE_ACCESSED) != 0); | |
872 | } | |
873 | ||
874 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
875 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr, | |
876 | pmd_t *pmdp) | |
877 | { | |
878 | ||
879 | if ((pmd_val(*pmdp) & _PAGE_WRITE) == 0) | |
880 | return; | |
881 | ||
882 | pmd_hugepage_update(mm, addr, pmdp, _PAGE_WRITE, 0); | |
3dfcb315 AK |
883 | } |
884 | ||
ab624762 AK |
885 | static inline int pmd_trans_huge(pmd_t pmd) |
886 | { | |
887 | if (radix_enabled()) | |
888 | return radix__pmd_trans_huge(pmd); | |
889 | return hash__pmd_trans_huge(pmd); | |
890 | } | |
891 | ||
892 | #define __HAVE_ARCH_PMD_SAME | |
893 | static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b) | |
894 | { | |
895 | if (radix_enabled()) | |
896 | return radix__pmd_same(pmd_a, pmd_b); | |
897 | return hash__pmd_same(pmd_a, pmd_b); | |
898 | } | |
899 | ||
3dfcb315 AK |
900 | static inline pmd_t pmd_mkhuge(pmd_t pmd) |
901 | { | |
ab624762 AK |
902 | if (radix_enabled()) |
903 | return radix__pmd_mkhuge(pmd); | |
904 | return hash__pmd_mkhuge(pmd); | |
3dfcb315 AK |
905 | } |
906 | ||
3dfcb315 AK |
907 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS |
908 | extern int pmdp_set_access_flags(struct vm_area_struct *vma, | |
909 | unsigned long address, pmd_t *pmdp, | |
910 | pmd_t entry, int dirty); | |
911 | ||
3dfcb315 AK |
912 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG |
913 | extern int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
914 | unsigned long address, pmd_t *pmdp); | |
3dfcb315 AK |
915 | |
916 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR | |
3df33f12 AK |
917 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, |
918 | unsigned long addr, pmd_t *pmdp) | |
919 | { | |
bde3eb62 AK |
920 | if (radix_enabled()) |
921 | return radix__pmdp_huge_get_and_clear(mm, addr, pmdp); | |
3df33f12 AK |
922 | return hash__pmdp_huge_get_and_clear(mm, addr, pmdp); |
923 | } | |
3dfcb315 | 924 | |
3df33f12 AK |
925 | static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, |
926 | unsigned long address, pmd_t *pmdp) | |
927 | { | |
bde3eb62 AK |
928 | if (radix_enabled()) |
929 | return radix__pmdp_collapse_flush(vma, address, pmdp); | |
3df33f12 AK |
930 | return hash__pmdp_collapse_flush(vma, address, pmdp); |
931 | } | |
3dfcb315 AK |
932 | #define pmdp_collapse_flush pmdp_collapse_flush |
933 | ||
934 | #define __HAVE_ARCH_PGTABLE_DEPOSIT | |
3df33f12 AK |
935 | static inline void pgtable_trans_huge_deposit(struct mm_struct *mm, |
936 | pmd_t *pmdp, pgtable_t pgtable) | |
937 | { | |
bde3eb62 AK |
938 | if (radix_enabled()) |
939 | return radix__pgtable_trans_huge_deposit(mm, pmdp, pgtable); | |
3df33f12 AK |
940 | return hash__pgtable_trans_huge_deposit(mm, pmdp, pgtable); |
941 | } | |
942 | ||
3dfcb315 | 943 | #define __HAVE_ARCH_PGTABLE_WITHDRAW |
3df33f12 AK |
944 | static inline pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, |
945 | pmd_t *pmdp) | |
946 | { | |
bde3eb62 AK |
947 | if (radix_enabled()) |
948 | return radix__pgtable_trans_huge_withdraw(mm, pmdp); | |
3df33f12 AK |
949 | return hash__pgtable_trans_huge_withdraw(mm, pmdp); |
950 | } | |
3dfcb315 AK |
951 | |
952 | #define __HAVE_ARCH_PMDP_INVALIDATE | |
953 | extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, | |
954 | pmd_t *pmdp); | |
955 | ||
c777e2a8 | 956 | #define __HAVE_ARCH_PMDP_HUGE_SPLIT_PREPARE |
3df33f12 AK |
957 | static inline void pmdp_huge_split_prepare(struct vm_area_struct *vma, |
958 | unsigned long address, pmd_t *pmdp) | |
959 | { | |
bde3eb62 AK |
960 | if (radix_enabled()) |
961 | return radix__pmdp_huge_split_prepare(vma, address, pmdp); | |
3df33f12 AK |
962 | return hash__pmdp_huge_split_prepare(vma, address, pmdp); |
963 | } | |
c777e2a8 | 964 | |
3dfcb315 AK |
965 | #define pmd_move_must_withdraw pmd_move_must_withdraw |
966 | struct spinlock; | |
967 | static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl, | |
968 | struct spinlock *old_pmd_ptl) | |
969 | { | |
bde3eb62 AK |
970 | if (radix_enabled()) |
971 | return false; | |
3dfcb315 AK |
972 | /* |
973 | * Archs like ppc64 use pgtable to store per pmd | |
974 | * specific information. So when we switch the pmd, | |
975 | * we should also withdraw and deposit the pgtable | |
976 | */ | |
977 | return true; | |
978 | } | |
6a1ea362 | 979 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
3dfcb315 AK |
980 | #endif /* __ASSEMBLY__ */ |
981 | #endif /* _ASM_POWERPC_BOOK3S_64_PGTABLE_H_ */ |