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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
11a6f6ab AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ |
3 | #define _ASM_POWERPC_BOOK3S_64_MMU_H_ | |
4 | ||
d09780f3 CL |
5 | #include <asm/page.h> |
6 | ||
11a6f6ab AK |
7 | #ifndef __ASSEMBLY__ |
8 | /* | |
9 | * Page size definition | |
10 | * | |
11 | * shift : is the "PAGE_SHIFT" value for that page size | |
12 | * sllp : is a bit mask with the value of SLB L || LP to be or'ed | |
13 | * directly to a slbmte "vsid" value | |
14 | * penc : is the HPTE encoding mask for the "LP" field: | |
15 | * | |
16 | */ | |
17 | struct mmu_psize_def { | |
18 | unsigned int shift; /* number of bits */ | |
19 | int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ | |
20 | unsigned int tlbiel; /* tlbiel supported for that page size */ | |
21 | unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ | |
d6265cb3 | 22 | unsigned long h_rpt_pgsize; /* H_RPT_INVALIDATE page size encoding */ |
2bfd65e4 AK |
23 | union { |
24 | unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ | |
25 | unsigned long ap; /* Ap encoding used by PowerISA 3.0 */ | |
26 | }; | |
11a6f6ab AK |
27 | }; |
28 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
29 | #endif /* __ASSEMBLY__ */ | |
30 | ||
11a6f6ab AK |
31 | /* 64-bit classic hash table MMU */ |
32 | #include <asm/book3s/64/mmu-hash.h> | |
11a6f6ab AK |
33 | |
34 | #ifndef __ASSEMBLY__ | |
e9983344 | 35 | /* |
8ab102d6 | 36 | * ISA 3.0 partition and process table entry format |
e9983344 AK |
37 | */ |
38 | struct prtb_entry { | |
39 | __be64 prtb0; | |
40 | __be64 prtb1; | |
41 | }; | |
42 | extern struct prtb_entry *process_tb; | |
43 | ||
44 | struct patb_entry { | |
45 | __be64 patb0; | |
46 | __be64 patb1; | |
47 | }; | |
48 | extern struct patb_entry *partition_tb; | |
49 | ||
dbcbfee0 | 50 | /* Bits in patb0 field */ |
e9983344 | 51 | #define PATB_HR (1UL << 63) |
70cd4c10 | 52 | #define RPDB_MASK 0x0fffffffffffff00UL |
e9983344 | 53 | #define RPDB_SHIFT (1UL << 8) |
dbcbfee0 PM |
54 | #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */ |
55 | #define RTS1_MASK (3UL << RTS1_SHIFT) | |
56 | #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */ | |
57 | #define RTS2_MASK (7UL << RTS2_SHIFT) | |
58 | #define RPDS_MASK 0x1f /* root page dir. size field */ | |
59 | ||
60 | /* Bits in patb1 field */ | |
61 | #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */ | |
62 | #define PRTS_MASK 0x1f /* process table size field */ | |
70cd4c10 | 63 | #define PRTB_MASK 0x0ffffffffffff000UL |
dbcbfee0 | 64 | |
5402e239 NP |
65 | /* Number of supported LPID bits */ |
66 | extern unsigned int mmu_lpid_bits; | |
67 | ||
a25bd72b BH |
68 | /* Number of supported PID bits */ |
69 | extern unsigned int mmu_pid_bits; | |
70 | ||
71 | /* Base PID to allocate from */ | |
72 | extern unsigned int mmu_base_pid; | |
73 | ||
af9d00e9 AK |
74 | /* |
75 | * memory block size used with radix translation. | |
76 | */ | |
950805f4 | 77 | extern unsigned long __ro_after_init radix_mem_block_size; |
af9d00e9 | 78 | |
a25bd72b BH |
79 | #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4) |
80 | #define PRTB_ENTRIES (1ul << mmu_pid_bits) | |
760573c1 | 81 | |
5402e239 NP |
82 | #define PATB_SIZE_SHIFT (mmu_lpid_bits + 4) |
83 | #define PATB_ENTRIES (1ul << mmu_lpid_bits) | |
11a6f6ab AK |
84 | |
85 | typedef unsigned long mm_context_id_t; | |
86 | struct spinlock; | |
87 | ||
1ab66d1f AP |
88 | /* Maximum possible number of NPUs in a system. */ |
89 | #define NV_MAX_NPUS 8 | |
90 | ||
11a6f6ab | 91 | typedef struct { |
f384796c AK |
92 | union { |
93 | /* | |
94 | * We use id as the PIDR content for radix. On hash we can use | |
95 | * more than one id. The extended ids are used when we start | |
96 | * having address above 512TB. We allocate one extended id | |
97 | * for each 512TB. The new id is then used with the 49 bit | |
98 | * EA to build a new VA. We always use ESID_BITS_1T_MASK bits | |
99 | * from EA and new context ids to build the new VAs. | |
100 | */ | |
101 | mm_context_id_t id; | |
387e220a | 102 | #ifdef CONFIG_PPC_64S_HASH_MMU |
f384796c | 103 | mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE]; |
387e220a | 104 | #endif |
f384796c | 105 | }; |
11a6f6ab | 106 | |
a619e59c BH |
107 | /* Number of bits in the mm_cpumask */ |
108 | atomic_t active_cpus; | |
109 | ||
aff6f8cb BH |
110 | /* Number of users of the external (Nest) MMU */ |
111 | atomic_t copros; | |
112 | ||
c420644c HM |
113 | /* Number of user space windows opened in process mm_context */ |
114 | atomic_t vas_windows; | |
115 | ||
387e220a | 116 | #ifdef CONFIG_PPC_64S_HASH_MMU |
70110186 | 117 | struct hash_mm_context *hash_context; |
387e220a | 118 | #endif |
1ab66d1f | 119 | |
c102f076 | 120 | void __user *vdso; |
1c7ec8a4 AK |
121 | /* |
122 | * pagetable fragment support | |
123 | */ | |
11a6f6ab | 124 | void *pte_frag; |
8a6c697b | 125 | void *pmd_frag; |
11a6f6ab AK |
126 | #ifdef CONFIG_SPAPR_TCE_IOMMU |
127 | struct list_head iommu_group_mem_list; | |
128 | #endif | |
4fb158f6 RP |
129 | |
130 | #ifdef CONFIG_PPC_MEM_KEYS | |
131 | /* | |
132 | * Each bit represents one protection key. | |
133 | * bit set -> key allocated | |
134 | * bit unset -> key available for allocation | |
135 | */ | |
136 | u32 pkey_allocation_map; | |
5586cf61 | 137 | s16 execute_only_pkey; /* key holding execute-only protection */ |
4fb158f6 | 138 | #endif |
11a6f6ab AK |
139 | } mm_context_t; |
140 | ||
387e220a | 141 | #ifdef CONFIG_PPC_64S_HASH_MMU |
60458fba AK |
142 | static inline u16 mm_ctx_user_psize(mm_context_t *ctx) |
143 | { | |
70110186 | 144 | return ctx->hash_context->user_psize; |
60458fba AK |
145 | } |
146 | ||
147 | static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize) | |
148 | { | |
70110186 | 149 | ctx->hash_context->user_psize = user_psize; |
60458fba AK |
150 | } |
151 | ||
152 | static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx) | |
153 | { | |
70110186 | 154 | return ctx->hash_context->low_slices_psize; |
60458fba AK |
155 | } |
156 | ||
157 | static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx) | |
158 | { | |
70110186 | 159 | return ctx->hash_context->high_slices_psize; |
60458fba AK |
160 | } |
161 | ||
162 | static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx) | |
163 | { | |
70110186 | 164 | return ctx->hash_context->slb_addr_limit; |
60458fba AK |
165 | } |
166 | ||
167 | static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit) | |
168 | { | |
70110186 | 169 | ctx->hash_context->slb_addr_limit = limit; |
60458fba AK |
170 | } |
171 | ||
fca5c1e9 CL |
172 | static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize) |
173 | { | |
174 | #ifdef CONFIG_PPC_64K_PAGES | |
175 | if (psize == MMU_PAGE_64K) | |
87746121 | 176 | return &ctx->hash_context->mask_64k; |
fca5c1e9 CL |
177 | #endif |
178 | #ifdef CONFIG_HUGETLB_PAGE | |
179 | if (psize == MMU_PAGE_16M) | |
87746121 | 180 | return &ctx->hash_context->mask_16m; |
fca5c1e9 | 181 | if (psize == MMU_PAGE_16G) |
87746121 | 182 | return &ctx->hash_context->mask_16g; |
fca5c1e9 CL |
183 | #endif |
184 | BUG_ON(psize != MMU_PAGE_4K); | |
185 | ||
87746121 | 186 | return &ctx->hash_context->mask_4k; |
fca5c1e9 CL |
187 | } |
188 | ||
60458fba AK |
189 | #ifdef CONFIG_PPC_SUBPAGE_PROT |
190 | static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx) | |
191 | { | |
ef629cc5 | 192 | return ctx->hash_context->spt; |
60458fba AK |
193 | } |
194 | #endif | |
195 | ||
11a6f6ab AK |
196 | /* |
197 | * The current system page and segment sizes | |
198 | */ | |
11a6f6ab AK |
199 | extern int mmu_virtual_psize; |
200 | extern int mmu_vmalloc_psize; | |
11a6f6ab | 201 | extern int mmu_io_psize; |
387e220a NP |
202 | #else /* CONFIG_PPC_64S_HASH_MMU */ |
203 | #ifdef CONFIG_PPC_64K_PAGES | |
204 | #define mmu_virtual_psize MMU_PAGE_64K | |
205 | #else | |
206 | #define mmu_virtual_psize MMU_PAGE_4K | |
207 | #endif | |
208 | #endif | |
58dbe9b3 | 209 | extern int mmu_linear_psize; |
387e220a | 210 | extern int mmu_vmemmap_psize; |
11a6f6ab | 211 | |
756d08d1 | 212 | /* MMU initialization */ |
1a01dc87 | 213 | void mmu_early_init_devtree(void); |
bacf9cf8 | 214 | void hash__early_init_devtree(void); |
2537b09c | 215 | void radix__early_init_devtree(void); |
227ae625 | 216 | #ifdef CONFIG_PPC_PKEY |
d3cd91fb AK |
217 | void pkey_early_init_devtree(void); |
218 | #else | |
219 | static inline void pkey_early_init_devtree(void) {} | |
220 | #endif | |
221 | ||
756d08d1 | 222 | extern void hash__early_init_mmu(void); |
2bfd65e4 | 223 | extern void radix__early_init_mmu(void); |
9384e552 | 224 | static inline void __init early_init_mmu(void) |
756d08d1 | 225 | { |
2bfd65e4 AK |
226 | if (radix_enabled()) |
227 | return radix__early_init_mmu(); | |
756d08d1 AK |
228 | return hash__early_init_mmu(); |
229 | } | |
230 | extern void hash__early_init_mmu_secondary(void); | |
2bfd65e4 | 231 | extern void radix__early_init_mmu_secondary(void); |
756d08d1 AK |
232 | static inline void early_init_mmu_secondary(void) |
233 | { | |
2bfd65e4 AK |
234 | if (radix_enabled()) |
235 | return radix__early_init_mmu_secondary(); | |
756d08d1 AK |
236 | return hash__early_init_mmu_secondary(); |
237 | } | |
238 | ||
239 | extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
240 | phys_addr_t first_memblock_size); | |
241 | static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base, | |
242 | phys_addr_t first_memblock_size) | |
243 | { | |
103a8542 AK |
244 | /* |
245 | * Hash has more strict restrictions. At this point we don't | |
246 | * know which translations we will pick. Hence go with hash | |
247 | * restrictions. | |
248 | */ | |
387e220a NP |
249 | if (!early_radix_enabled()) |
250 | hash__setup_initial_memory_limit(first_memblock_base, | |
251 | first_memblock_size); | |
756d08d1 | 252 | } |
eea8148c | 253 | |
cc3d2940 | 254 | #ifdef CONFIG_PPC_PSERIES |
e14ff96d | 255 | void __init radix_init_pseries(void); |
cc3d2940 | 256 | #else |
6c6fdbb2 | 257 | static inline void radix_init_pseries(void) { } |
cc3d2940 PM |
258 | #endif |
259 | ||
01b0f0ea NP |
260 | #ifdef CONFIG_HOTPLUG_CPU |
261 | #define arch_clear_mm_cpumask_cpu(cpu, mm) \ | |
262 | do { \ | |
263 | if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { \ | |
264 | atomic_dec(&(mm)->context.active_cpus); \ | |
265 | cpumask_clear_cpu(cpu, mm_cpumask(mm)); \ | |
266 | } \ | |
267 | } while (0) | |
268 | ||
269 | void cleanup_cpu_mmu_context(void); | |
270 | #endif | |
271 | ||
387e220a | 272 | #ifdef CONFIG_PPC_64S_HASH_MMU |
c9f80734 | 273 | static inline int get_user_context(mm_context_t *ctx, unsigned long ea) |
f384796c AK |
274 | { |
275 | int index = ea >> MAX_EA_BITS_PER_CONTEXT; | |
276 | ||
277 | if (likely(index < ARRAY_SIZE(ctx->extended_id))) | |
278 | return ctx->extended_id[index]; | |
279 | ||
280 | /* should never happen */ | |
281 | WARN_ON(1); | |
282 | return 0; | |
283 | } | |
284 | ||
285 | static inline unsigned long get_user_vsid(mm_context_t *ctx, | |
286 | unsigned long ea, int ssize) | |
287 | { | |
c9f80734 | 288 | unsigned long context = get_user_context(ctx, ea); |
f384796c AK |
289 | |
290 | return get_vsid(context, ea, ssize); | |
291 | } | |
387e220a | 292 | #endif |
f384796c | 293 | |
11a6f6ab AK |
294 | #endif /* __ASSEMBLY__ */ |
295 | #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */ |