[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / mmu.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
#define _ASM_POWERPC_BOOK3S_64_MMU_H_

#ifndef __ASSEMBLY__
/*
 * Page size definition
 *
 *    shift : is the "PAGE_SHIFT" value for that page size
 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 *            directly to a slbmte "vsid" value
 *    penc  : is the HPTE encoding mask for the "LP" field:
 *
 */
struct mmu_psize_def {
	unsigned int	shift;	/* number of bits */
	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */
	unsigned int	tlbiel;	/* tlbiel supported for that page size */
	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
	union {
		unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
		unsigned long ap;	/* Ap encoding used by PowerISA 3.0 */
	};
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];

#endif /* __ASSEMBLY__ */

/* 64-bit classic hash table MMU */
#include <asm/book3s/64/mmu-hash.h>

#ifndef __ASSEMBLY__
/*
 * ISA 3.0 partition and process table entry format
 */
struct prtb_entry {
	__be64 prtb0;
	__be64 prtb1;
};
extern struct prtb_entry *process_tb;

struct patb_entry {
	__be64 patb0;
	__be64 patb1;
};
extern struct patb_entry *partition_tb;

/* Bits in patb0 field */
#define PATB_HR		(1UL << 63)
#define RPDB_MASK	0x0fffffffffffff00UL
#define RPDB_SHIFT	(1UL << 8)
#define RTS1_SHIFT	61		/* top 2 bits of radix tree size */
#define RTS1_MASK	(3UL << RTS1_SHIFT)
#define RTS2_SHIFT	5		/* bottom 3 bits of radix tree size */
#define RTS2_MASK	(7UL << RTS2_SHIFT)
#define RPDS_MASK	0x1f		/* root page dir. size field */

/* Bits in patb1 field */
#define PATB_GR		(1UL << 63)	/* guest uses radix; must match HR */
#define PRTS_MASK	0x1f		/* process table size field */
#define PRTB_MASK	0x0ffffffffffff000UL

/* Number of supported PID bits */
extern unsigned int mmu_pid_bits;

/* Base PID to allocate from */
extern unsigned int mmu_base_pid;

#define PRTB_SIZE_SHIFT	(mmu_pid_bits + 4)
#define PRTB_ENTRIES	(1ul << mmu_pid_bits)

/*
 * Power9 currently only support 64K partition table size.
 */
#define PATB_SIZE_SHIFT	16

typedef unsigned long mm_context_id_t;
struct spinlock;

/* Maximum possible number of NPUs in a system. */
#define NV_MAX_NPUS 8

/*
 * One bit per slice. We have lower slices which cover 256MB segments
 * upto 4G range. That gets us 16 low slices. For the rest we track slices
 * in 1TB size.
 */
struct slice_mask {
	u64 low_slices;
	DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
};

typedef struct {
	mm_context_id_t id;
	u16 user_psize;		/* page size index */

	/* Number of bits in the mm_cpumask */
	atomic_t active_cpus;

	/* Number of users of the external (Nest) MMU */
	atomic_t copros;

	/* NPU NMMU context */
	struct npu_context *npu_context;

#ifdef CONFIG_PPC_MM_SLICES
	 /* SLB page size encodings*/
	unsigned char low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
	unsigned long slb_addr_limit;
# ifdef CONFIG_PPC_64K_PAGES
	struct slice_mask mask_64k;
# endif
	struct slice_mask mask_4k;
# ifdef CONFIG_HUGETLB_PAGE
	struct slice_mask mask_16m;
	struct slice_mask mask_16g;
# endif
#else
	u16 sllp;		/* SLB page size encoding */
#endif
	unsigned long vdso_base;
#ifdef CONFIG_PPC_SUBPAGE_PROT
	struct subpage_prot_table spt;
#endif /* CONFIG_PPC_SUBPAGE_PROT */
#ifdef CONFIG_PPC_64K_PAGES
	/* for 4K PTE fragment support */
	void *pte_frag;
#endif
#ifdef CONFIG_SPAPR_TCE_IOMMU
	struct list_head iommu_group_mem_list;
#endif

#ifdef CONFIG_PPC_MEM_KEYS
	/*
	 * Each bit represents one protection key.
	 * bit set   -> key allocated
	 * bit unset -> key available for allocation
	 */
	u32 pkey_allocation_map;
	s16 execute_only_pkey; /* key holding execute-only protection */
#endif
} mm_context_t;

/*
 * The current system page and segment sizes
 */
extern int mmu_linear_psize;
extern int mmu_virtual_psize;
extern int mmu_vmalloc_psize;
extern int mmu_vmemmap_psize;
extern int mmu_io_psize;

/* MMU initialization */
void mmu_early_init_devtree(void);
void hash__early_init_devtree(void);
void radix__early_init_devtree(void);
extern void radix_init_native(void);
extern void hash__early_init_mmu(void);
extern void radix__early_init_mmu(void);
static inline void early_init_mmu(void)
{
	if (radix_enabled())
		return radix__early_init_mmu();
	return hash__early_init_mmu();
}
extern void hash__early_init_mmu_secondary(void);
extern void radix__early_init_mmu_secondary(void);
static inline void early_init_mmu_secondary(void)
{
	if (radix_enabled())
		return radix__early_init_mmu_secondary();
	return hash__early_init_mmu_secondary();
}

extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
					      phys_addr_t first_memblock_size)
{
	if (early_radix_enabled())
		return radix__setup_initial_memory_limit(first_memblock_base,
						   first_memblock_size);
	return hash__setup_initial_memory_limit(first_memblock_base,
					   first_memblock_size);
}

extern int (*register_process_table)(unsigned long base, unsigned long page_size,
				     unsigned long tbl_size);

#ifdef CONFIG_PPC_PSERIES
extern void radix_init_pseries(void);
#else
static inline void radix_init_pseries(void) { };
#endif

#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
11a6f6ab AK	2	#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
	3	#define _ASM_POWERPC_BOOK3S_64_MMU_H_
	4
	5	#ifndef __ASSEMBLY__
	6	/*
	7	* Page size definition
	8	*
	9	* shift : is the "PAGE_SHIFT" value for that page size
	10	* sllp : is a bit mask with the value of SLB L \|\| LP to be or'ed
	11	* directly to a slbmte "vsid" value
	12	* penc : is the HPTE encoding mask for the "LP" field:
	13	*
	14	*/
	15	struct mmu_psize_def {
	16	unsigned int shift; /* number of bits */
	17	int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
	18	unsigned int tlbiel; /* tlbiel supported for that page size */
	19	unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
2bfd65e4 AK	20	union {
	21	unsigned long sllp; /* SLB L\|\|LP (exact mask to use in slbmte) */
	22	unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
	23	};
11a6f6ab AK	24	};
11a6f6ab AK	25	extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
566ca99a	26
11a6f6ab AK	27	#endif /* __ASSEMBLY__ */
11a6f6ab AK	28
11a6f6ab AK	29	/* 64-bit classic hash table MMU */
11a6f6ab AK	30	#include <asm/book3s/64/mmu-hash.h>
11a6f6ab AK	31
11a6f6ab AK	32	#ifndef __ASSEMBLY__
e9983344	33	/*
8ab102d6	34	* ISA 3.0 partition and process table entry format
e9983344 AK	35	*/
	36	struct prtb_entry {
	37	__be64 prtb0;
	38	__be64 prtb1;
	39	};
	40	extern struct prtb_entry *process_tb;
	41
	42	struct patb_entry {
	43	__be64 patb0;
	44	__be64 patb1;
	45	};
	46	extern struct patb_entry *partition_tb;
	47
dbcbfee0	48	/* Bits in patb0 field */
e9983344	49	#define PATB_HR (1UL << 63)
70cd4c10	50	#define RPDB_MASK 0x0fffffffffffff00UL
e9983344	51	#define RPDB_SHIFT (1UL << 8)
dbcbfee0 PM	52	#define RTS1_SHIFT 61 /* top 2 bits of radix tree size */
	53	#define RTS1_MASK (3UL << RTS1_SHIFT)
	54	#define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */
	55	#define RTS2_MASK (7UL << RTS2_SHIFT)
	56	#define RPDS_MASK 0x1f /* root page dir. size field */
	57
	58	/* Bits in patb1 field */
	59	#define PATB_GR (1UL << 63) /* guest uses radix; must match HR */
	60	#define PRTS_MASK 0x1f /* process table size field */
70cd4c10	61	#define PRTB_MASK 0x0ffffffffffff000UL
dbcbfee0	62
a25bd72b BH	63	/* Number of supported PID bits */
	64	extern unsigned int mmu_pid_bits;
	65
	66	/* Base PID to allocate from */
	67	extern unsigned int mmu_base_pid;
	68
	69	#define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
	70	#define PRTB_ENTRIES (1ul << mmu_pid_bits)
760573c1	71
e9983344 AK	72	/*
	73	* Power9 currently only support 64K partition table size.
	74	*/
	75	#define PATB_SIZE_SHIFT 16
11a6f6ab AK	76
	77	typedef unsigned long mm_context_id_t;
	78	struct spinlock;
	79
1ab66d1f AP	80	/* Maximum possible number of NPUs in a system. */
	81	#define NV_MAX_NPUS 8
	82
5709f7cf NP	83	/*
	84	* One bit per slice. We have lower slices which cover 256MB segments
	85	* upto 4G range. That gets us 16 low slices. For the rest we track slices
	86	* in 1TB size.
	87	*/
	88	struct slice_mask {
	89	u64 low_slices;
	90	DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
	91	};
	92
11a6f6ab AK	93	typedef struct {
	94	mm_context_id_t id;
	95	u16 user_psize; /* page size index */
	96
a619e59c BH	97	/* Number of bits in the mm_cpumask */
	98	atomic_t active_cpus;
	99
aff6f8cb BH	100	/* Number of users of the external (Nest) MMU */
	101	atomic_t copros;
	102
1ab66d1f AP	103	/* NPU NMMU context */
	104	struct npu_context *npu_context;
	105
11a6f6ab	106	#ifdef CONFIG_PPC_MM_SLICES
15472423 CL	107	/* SLB page size encodings*/
15472423 CL	108	unsigned char low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
11a6f6ab	109	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
4722476b	110	unsigned long slb_addr_limit;
5709f7cf NP	111	# ifdef CONFIG_PPC_64K_PAGES
	112	struct slice_mask mask_64k;
	113	# endif
	114	struct slice_mask mask_4k;
	115	# ifdef CONFIG_HUGETLB_PAGE
	116	struct slice_mask mask_16m;
	117	struct slice_mask mask_16g;
	118	# endif
11a6f6ab AK	119	#else
	120	u16 sllp; /* SLB page size encoding */
	121	#endif
	122	unsigned long vdso_base;
	123	#ifdef CONFIG_PPC_SUBPAGE_PROT
	124	struct subpage_prot_table spt;
	125	#endif /* CONFIG_PPC_SUBPAGE_PROT */
11a6f6ab AK	126	#ifdef CONFIG_PPC_64K_PAGES
	127	/* for 4K PTE fragment support */
	128	void *pte_frag;
	129	#endif
	130	#ifdef CONFIG_SPAPR_TCE_IOMMU
	131	struct list_head iommu_group_mem_list;
	132	#endif
4fb158f6 RP	133
	134	#ifdef CONFIG_PPC_MEM_KEYS
	135	/*
	136	* Each bit represents one protection key.
	137	* bit set -> key allocated
	138	* bit unset -> key available for allocation
	139	*/
	140	u32 pkey_allocation_map;
5586cf61	141	s16 execute_only_pkey; /* key holding execute-only protection */
4fb158f6	142	#endif
11a6f6ab AK	143	} mm_context_t;
	144
	145	/*
	146	* The current system page and segment sizes
	147	*/
	148	extern int mmu_linear_psize;
	149	extern int mmu_virtual_psize;
	150	extern int mmu_vmalloc_psize;
	151	extern int mmu_vmemmap_psize;
	152	extern int mmu_io_psize;
	153
756d08d1	154	/* MMU initialization */
1a01dc87	155	void mmu_early_init_devtree(void);
bacf9cf8	156	void hash__early_init_devtree(void);
2537b09c	157	void radix__early_init_devtree(void);
2bfd65e4	158	extern void radix_init_native(void);
756d08d1	159	extern void hash__early_init_mmu(void);
2bfd65e4	160	extern void radix__early_init_mmu(void);
756d08d1 AK	161	static inline void early_init_mmu(void)
756d08d1 AK	162	{
2bfd65e4 AK	163	if (radix_enabled())
2bfd65e4 AK	164	return radix__early_init_mmu();
756d08d1 AK	165	return hash__early_init_mmu();
	166	}
	167	extern void hash__early_init_mmu_secondary(void);
2bfd65e4	168	extern void radix__early_init_mmu_secondary(void);
756d08d1 AK	169	static inline void early_init_mmu_secondary(void)
756d08d1 AK	170	{
2bfd65e4 AK	171	if (radix_enabled())
2bfd65e4 AK	172	return radix__early_init_mmu_secondary();
756d08d1 AK	173	return hash__early_init_mmu_secondary();
	174	}
	175
	176	extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
	177	phys_addr_t first_memblock_size);
2bfd65e4 AK	178	extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
2bfd65e4 AK	179	phys_addr_t first_memblock_size);
756d08d1 AK	180	static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	181	phys_addr_t first_memblock_size)
	182	{
b8f1b4f8	183	if (early_radix_enabled())
2bfd65e4 AK	184	return radix__setup_initial_memory_limit(first_memblock_base,
2bfd65e4 AK	185	first_memblock_size);
756d08d1 AK	186	return hash__setup_initial_memory_limit(first_memblock_base,
	187	first_memblock_size);
	188	}
eea8148c ME	189
	190	extern int (*register_process_table)(unsigned long base, unsigned long page_size,
	191	unsigned long tbl_size);
	192
cc3d2940 PM	193	#ifdef CONFIG_PPC_PSERIES
	194	extern void radix_init_pseries(void);
	195	#else
	196	static inline void radix_init_pseries(void) { };
	197	#endif
	198
11a6f6ab AK	199	#endif /* __ASSEMBLY__ */
11a6f6ab AK	200	#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */