[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / mmu.h

#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
#define _ASM_POWERPC_BOOK3S_64_MMU_H_

#ifndef __ASSEMBLY__
/*
 * Page size definition
 *
 *    shift : is the "PAGE_SHIFT" value for that page size
 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 *            directly to a slbmte "vsid" value
 *    penc  : is the HPTE encoding mask for the "LP" field:
 *
 */
struct mmu_psize_def {
	unsigned int	shift;	/* number of bits */
	int		penc[MMU_PAGE_COUNT];	/* HPTE encoding */
	unsigned int	tlbiel;	/* tlbiel supported for that page size */
	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
	union {
		unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
		unsigned long ap;	/* Ap encoding used by PowerISA 3.0 */
	};
};
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];

#define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)

#endif /* __ASSEMBLY__ */

/* 64-bit classic hash table MMU */
#include <asm/book3s/64/mmu-hash.h>

#ifndef __ASSEMBLY__
/*
 * ISA 3.0 partiton and process table entry format
 */
struct prtb_entry {
	__be64 prtb0;
	__be64 prtb1;
};
extern struct prtb_entry *process_tb;

struct patb_entry {
	__be64 patb0;
	__be64 patb1;
};
extern struct patb_entry *partition_tb;

#define PATB_HR		(1UL << 63)
#define PATB_GR		(1UL << 63)
#define RPDB_MASK	0x0ffffffffffff00fUL
#define RPDB_SHIFT	(1UL << 8)
/*
 * Limit process table to PAGE_SIZE table. This
 * also limit the max pid we can support.
 * MAX_USER_CONTEXT * 16 bytes of space.
 */
#define PRTB_SIZE_SHIFT	(CONTEXT_BITS + 4)
/*
 * Power9 currently only support 64K partition table size.
 */
#define PATB_SIZE_SHIFT	16

typedef unsigned long mm_context_id_t;
struct spinlock;

typedef struct {
	mm_context_id_t id;
	u16 user_psize;		/* page size index */

#ifdef CONFIG_PPC_MM_SLICES
	u64 low_slices_psize;	/* SLB page size encodings */
	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
#else
	u16 sllp;		/* SLB page size encoding */
#endif
	unsigned long vdso_base;
#ifdef CONFIG_PPC_SUBPAGE_PROT
	struct subpage_prot_table spt;
#endif /* CONFIG_PPC_SUBPAGE_PROT */
#ifdef CONFIG_PPC_ICSWX
	struct spinlock *cop_lockp; /* guard acop and cop_pid */
	unsigned long acop;	/* mask of enabled coprocessor types */
	unsigned int cop_pid;	/* pid value used with coprocessors */
#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_64K_PAGES
	/* for 4K PTE fragment support */
	void *pte_frag;
#endif
#ifdef CONFIG_SPAPR_TCE_IOMMU
	struct list_head iommu_group_mem_list;
#endif
} mm_context_t;

/*
 * The current system page and segment sizes
 */
extern int mmu_linear_psize;
extern int mmu_virtual_psize;
extern int mmu_vmalloc_psize;
extern int mmu_vmemmap_psize;
extern int mmu_io_psize;

/* MMU initialization */
extern void radix_init_native(void);
extern void hash__early_init_mmu(void);
extern void radix__early_init_mmu(void);
static inline void early_init_mmu(void)
{
	if (radix_enabled())
		return radix__early_init_mmu();
	return hash__early_init_mmu();
}
extern void hash__early_init_mmu_secondary(void);
extern void radix__early_init_mmu_secondary(void);
static inline void early_init_mmu_secondary(void)
{
	if (radix_enabled())
		return radix__early_init_mmu_secondary();
	return hash__early_init_mmu_secondary();
}

extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
					 phys_addr_t first_memblock_size);
static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
					      phys_addr_t first_memblock_size)
{
	if (radix_enabled())
		return radix__setup_initial_memory_limit(first_memblock_base,
						   first_memblock_size);
	return hash__setup_initial_memory_limit(first_memblock_base,
					   first_memblock_size);
}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
Commit	Line	Data
11a6f6ab AK	1	#ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
	2	#define _ASM_POWERPC_BOOK3S_64_MMU_H_
	3
	4	#ifndef __ASSEMBLY__
	5	/*
	6	* Page size definition
	7	*
	8	* shift : is the "PAGE_SHIFT" value for that page size
	9	* sllp : is a bit mask with the value of SLB L \|\| LP to be or'ed
	10	* directly to a slbmte "vsid" value
	11	* penc : is the HPTE encoding mask for the "LP" field:
	12	*
	13	*/
	14	struct mmu_psize_def {
	15	unsigned int shift; /* number of bits */
	16	int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
	17	unsigned int tlbiel; /* tlbiel supported for that page size */
	18	unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
2bfd65e4 AK	19	union {
	20	unsigned long sllp; /* SLB L\|\|LP (exact mask to use in slbmte) */
	21	unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
	22	};
11a6f6ab AK	23	};
11a6f6ab AK	24	extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
566ca99a	25
a8ed87c9 AK	26	#define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)
a8ed87c9 AK	27
11a6f6ab AK	28	#endif /* __ASSEMBLY__ */
11a6f6ab AK	29
11a6f6ab AK	30	/* 64-bit classic hash table MMU */
11a6f6ab AK	31	#include <asm/book3s/64/mmu-hash.h>
11a6f6ab AK	32
11a6f6ab AK	33	#ifndef __ASSEMBLY__
e9983344 AK	34	/*
	35	* ISA 3.0 partiton and process table entry format
	36	*/
	37	struct prtb_entry {
	38	__be64 prtb0;
	39	__be64 prtb1;
	40	};
	41	extern struct prtb_entry *process_tb;
	42
	43	struct patb_entry {
	44	__be64 patb0;
	45	__be64 patb1;
	46	};
	47	extern struct patb_entry *partition_tb;
	48
	49	#define PATB_HR (1UL << 63)
	50	#define PATB_GR (1UL << 63)
	51	#define RPDB_MASK 0x0ffffffffffff00fUL
	52	#define RPDB_SHIFT (1UL << 8)
	53	/*
	54	* Limit process table to PAGE_SIZE table. This
	55	* also limit the max pid we can support.
	56	* MAX_USER_CONTEXT * 16 bytes of space.
	57	*/
	58	#define PRTB_SIZE_SHIFT (CONTEXT_BITS + 4)
	59	/*
	60	* Power9 currently only support 64K partition table size.
	61	*/
	62	#define PATB_SIZE_SHIFT 16
11a6f6ab AK	63
	64	typedef unsigned long mm_context_id_t;
	65	struct spinlock;
	66
	67	typedef struct {
	68	mm_context_id_t id;
	69	u16 user_psize; /* page size index */
	70
	71	#ifdef CONFIG_PPC_MM_SLICES
	72	u64 low_slices_psize; /* SLB page size encodings */
	73	unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
	74	#else
	75	u16 sllp; /* SLB page size encoding */
	76	#endif
	77	unsigned long vdso_base;
	78	#ifdef CONFIG_PPC_SUBPAGE_PROT
	79	struct subpage_prot_table spt;
	80	#endif /* CONFIG_PPC_SUBPAGE_PROT */
	81	#ifdef CONFIG_PPC_ICSWX
	82	struct spinlock cop_lockp; / guard acop and cop_pid */
	83	unsigned long acop; /* mask of enabled coprocessor types */
	84	unsigned int cop_pid; /* pid value used with coprocessors */
	85	#endif /* CONFIG_PPC_ICSWX */
	86	#ifdef CONFIG_PPC_64K_PAGES
	87	/* for 4K PTE fragment support */
	88	void *pte_frag;
	89	#endif
	90	#ifdef CONFIG_SPAPR_TCE_IOMMU
	91	struct list_head iommu_group_mem_list;
	92	#endif
	93	} mm_context_t;
	94
	95	/*
	96	* The current system page and segment sizes
	97	*/
	98	extern int mmu_linear_psize;
	99	extern int mmu_virtual_psize;
	100	extern int mmu_vmalloc_psize;
	101	extern int mmu_vmemmap_psize;
	102	extern int mmu_io_psize;
	103
756d08d1	104	/* MMU initialization */
2bfd65e4	105	extern void radix_init_native(void);
756d08d1	106	extern void hash__early_init_mmu(void);
2bfd65e4	107	extern void radix__early_init_mmu(void);
756d08d1 AK	108	static inline void early_init_mmu(void)
756d08d1 AK	109	{
2bfd65e4 AK	110	if (radix_enabled())
2bfd65e4 AK	111	return radix__early_init_mmu();
756d08d1 AK	112	return hash__early_init_mmu();
	113	}
	114	extern void hash__early_init_mmu_secondary(void);
2bfd65e4	115	extern void radix__early_init_mmu_secondary(void);
756d08d1 AK	116	static inline void early_init_mmu_secondary(void)
756d08d1 AK	117	{
2bfd65e4 AK	118	if (radix_enabled())
2bfd65e4 AK	119	return radix__early_init_mmu_secondary();
756d08d1 AK	120	return hash__early_init_mmu_secondary();
	121	}
	122
	123	extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
	124	phys_addr_t first_memblock_size);
2bfd65e4 AK	125	extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
2bfd65e4 AK	126	phys_addr_t first_memblock_size);
756d08d1 AK	127	static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	128	phys_addr_t first_memblock_size)
	129	{
2bfd65e4 AK	130	if (radix_enabled())
	131	return radix__setup_initial_memory_limit(first_memblock_base,
	132	first_memblock_size);
756d08d1 AK	133	return hash__setup_initial_memory_limit(first_memblock_base,
	134	first_memblock_size);
	135	}
11a6f6ab AK	136	#endif /* __ASSEMBLY__ */
11a6f6ab AK	137	#endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */