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powerpc/mm: Declare some prototypes
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / mmu-hash.h
CommitLineData
2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
11a6f6ab
AK		 2#ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
3#define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
8d2169e8
DG		 4/*
5 * PowerPC64 memory management structures
6 *
7 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
8 * PPC64 rework.
8d2169e8
DG		 9 */
10
8d2169e8 11#include <asm/page.h>
891121e6 12#include <asm/bug.h>
ec0c464c 13#include <asm/asm-const.h>
8d2169e8 14
78f1dbde
AK		 15/*
16 * This is necessary to get the definition of PGTABLE_RANGE which we
17 * need for various slices related matters. Note that this isn't the
18 * complete pgtable.h but only a portion of it.
19 */
3dfcb315 20#include <asm/book3s/64/pgtable.h>
cf9427b8 21#include <asm/bug.h>
92ab45c5 22#include <asm/task_size_64.h>
b92a226e 23#include <asm/cpu_has_feature.h>
78f1dbde 24
8d2169e8
DG		 25/*
26 * SLB
27 */
28
85376e2a 29#define SLB_NUM_BOLTED 2
8d2169e8 30#define SLB_CACHE_ENTRIES 8
46db2f86 31#define SLB_MIN_SIZE 32
8d2169e8
DG		 32
33/* Bits in the SLB ESID word */
34#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
35
36/* Bits in the SLB VSID word */
37#define SLB_VSID_SHIFT 12
e6f81a92 38#define SLB_VSID_SHIFT_256M SLB_VSID_SHIFT
1189be65
PM		 39#define SLB_VSID_SHIFT_1T 24
40#define SLB_VSID_SSIZE_SHIFT 62
8d2169e8
DG		 41#define SLB_VSID_B ASM_CONST(0xc000000000000000)
42#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
43#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
44#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
45#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
46#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
47#define SLB_VSID_L ASM_CONST(0x0000000000000100)
48#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
49#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
50#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
51#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
52#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
53#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
54#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
55
56#define SLB_VSID_KERNEL (SLB_VSID_KP)
57#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
58
59#define SLBIE_C (0x08000000)
1189be65 60#define SLBIE_SSIZE_SHIFT 25
8d2169e8
DG		 61
62/*
63 * Hash table
64 */
65
66#define HPTES_PER_GROUP 8
67
2454c7e9 68#define HPTE_V_SSIZE_SHIFT 62
8d2169e8 69#define HPTE_V_AVPN_SHIFT 7
6b243fcf 70#define HPTE_V_COMMON_BITS ASM_CONST(0x000fffffffffffff)
2454c7e9 71#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
6b243fcf 72#define HPTE_V_AVPN_3_0 ASM_CONST(0x000fffffffffff80)
8d2169e8 73#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
91bbbe22 74#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
8d2169e8
DG		 75#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
76#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
77#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
78#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
79#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
80
50de596d 81/*
6b243fcf 82 * ISA 3.0 has a different HPTE format.
50de596d
AK		 83 */
84#define HPTE_R_3_0_SSIZE_SHIFT 58
6b243fcf 85#define HPTE_R_3_0_SSIZE_MASK (3ull << HPTE_R_3_0_SSIZE_SHIFT)
8d2169e8
DG		 86#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
87#define HPTE_R_TS ASM_CONST(0x4000000000000000)
de56a948 88#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
33699023
AK		 89#define HPTE_R_KEY_BIT4 ASM_CONST(0x2000000000000000)
90#define HPTE_R_KEY_BIT3 ASM_CONST(0x1000000000000000)
8d2169e8 91#define HPTE_R_RPN_SHIFT 12
de56a948 92#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
6b243fcf 93#define HPTE_R_RPN_3_0 ASM_CONST(0x01fffffffffff000)
8d2169e8 94#define HPTE_R_PP ASM_CONST(0x0000000000000003)
8550e2fa 95#define HPTE_R_PPP ASM_CONST(0x8000000000000003)
8d2169e8 96#define HPTE_R_N ASM_CONST(0x0000000000000004)
de56a948
PM		 97#define HPTE_R_G ASM_CONST(0x0000000000000008)
98#define HPTE_R_M ASM_CONST(0x0000000000000010)
99#define HPTE_R_I ASM_CONST(0x0000000000000020)
100#define HPTE_R_W ASM_CONST(0x0000000000000040)
101#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
8d2169e8
DG		 102#define HPTE_R_C ASM_CONST(0x0000000000000080)
103#define HPTE_R_R ASM_CONST(0x0000000000000100)
de56a948 104#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
a6590ca5 105#define HPTE_R_KEY_BIT2 ASM_CONST(0x0000000000000800)
33699023
AK		 106#define HPTE_R_KEY_BIT1 ASM_CONST(0x0000000000000400)
107#define HPTE_R_KEY_BIT0 ASM_CONST(0x0000000000000200)
d182b8fd 108#define HPTE_R_KEY (HPTE_R_KEY_LO | HPTE_R_KEY_HI)
8d2169e8 109
b7abc5c5
SS		 110#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
111#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
112
8d2169e8 113/* Values for PP (assumes Ks=0, Kp=1) */
8d2169e8
DG		 114#define PP_RWXX 0 /* Supervisor read/write, User none */
115#define PP_RWRX 1 /* Supervisor read/write, User read */
116#define PP_RWRW 2 /* Supervisor read/write, User read/write */
117#define PP_RXRX 3 /* Supervisor read, User read */
697d3899 118#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
8d2169e8 119
b4072df4
PM		 120/* Fields for tlbiel instruction in architecture 2.06 */
121#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
122#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
123#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
124#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
125#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
126#define TLBIEL_INVAL_SET_SHIFT 12
127
128#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
45706bb5 129#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
c3ab300e 130#define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
1a472c9d 131#define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
b4072df4 132
8d2169e8
DG		 133#ifndef __ASSEMBLY__
134
7025776e
BH		 135struct mmu_hash_ops {
136 void (*hpte_invalidate)(unsigned long slot,
137 unsigned long vpn,
138 int bpsize, int apsize,
139 int ssize, int local);
140 long (*hpte_updatepp)(unsigned long slot,
141 unsigned long newpp,
142 unsigned long vpn,
143 int bpsize, int apsize,
144 int ssize, unsigned long flags);
145 void (*hpte_updateboltedpp)(unsigned long newpp,
146 unsigned long ea,
147 int psize, int ssize);
148 long (*hpte_insert)(unsigned long hpte_group,
149 unsigned long vpn,
150 unsigned long prpn,
151 unsigned long rflags,
152 unsigned long vflags,
153 int psize, int apsize,
154 int ssize);
155 long (*hpte_remove)(unsigned long hpte_group);
156 int (*hpte_removebolted)(unsigned long ea,
157 int psize, int ssize);
158 void (*flush_hash_range)(unsigned long number, int local);
159 void (*hugepage_invalidate)(unsigned long vsid,
160 unsigned long addr,
161 unsigned char *hpte_slot_array,
162 int psize, int ssize, int local);
dbcf929c 163 int (*resize_hpt)(unsigned long shift);
7025776e
BH		 164 /*
165 * Special for kexec.
166 * To be called in real mode with interrupts disabled. No locks are
167 * taken as such, concurrent access on pre POWER5 hardware could result
168 * in a deadlock.
169 * The linear mapping is destroyed as well.
170 */
171 void (*hpte_clear_all)(void);
172};
173extern struct mmu_hash_ops mmu_hash_ops;
174
8e561e7e 175struct hash_pte {
12f04f2b
AB		 176 __be64 v;
177 __be64 r;
8e561e7e 178};
8d2169e8 179
8e561e7e 180extern struct hash_pte *htab_address;
8d2169e8
DG		 181extern unsigned long htab_size_bytes;
182extern unsigned long htab_hash_mask;
183
cf9427b8
AK		 184
185static inline int shift_to_mmu_psize(unsigned int shift)
186{
187 int psize;
188
189 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
190 if (mmu_psize_defs[psize].shift == shift)
191 return psize;
192 return -1;
193}
194
195static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
196{
197 if (mmu_psize_defs[mmu_psize].shift)
198 return mmu_psize_defs[mmu_psize].shift;
199 BUG();
200}
8d2169e8 201
e3b6b466
SJS		 202static inline unsigned int ap_to_shift(unsigned long ap)
203{
204 int psize;
205
206 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
207 if (mmu_psize_defs[psize].ap == ap)
208 return mmu_psize_defs[psize].shift;
209 }
210
211 return -1;
212}
213
138ee7ee
AK		 214static inline unsigned long get_sllp_encoding(int psize)
215{
216 unsigned long sllp;
217
218 sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) |
219 ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4);
220 return sllp;
221}
222
8d2169e8
DG		 223#endif /* __ASSEMBLY__ */
224
2454c7e9
PM		 225/*
226 * Segment sizes.
227 * These are the values used by hardware in the B field of
228 * SLB entries and the first dword of MMU hashtable entries.
229 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
230 */
231#define MMU_SEGSIZE_256M 0
232#define MMU_SEGSIZE_1T 1
233
5524a27d
AK		 234/*
235 * encode page number shift.
236 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
237 * 12 bits. This enable us to address upto 76 bit va.
238 * For hpt hash from a va we can ignore the page size bits of va and for
239 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
240 * we work in all cases including 4k page size.
241 */
242#define VPN_SHIFT 12
1189be65 243
b1022fbd
AK		 244/*
245 * HPTE Large Page (LP) details
246 */
247#define LP_SHIFT 12
248#define LP_BITS 8
249#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
250
8d2169e8
DG		 251#ifndef __ASSEMBLY__
252
73d16a6e
IM		 253static inline int slb_vsid_shift(int ssize)
254{
255 if (ssize == MMU_SEGSIZE_256M)
256 return SLB_VSID_SHIFT;
257 return SLB_VSID_SHIFT_1T;
258}
259
5524a27d
AK		 260static inline int segment_shift(int ssize)
261{
262 if (ssize == MMU_SEGSIZE_256M)
263 return SID_SHIFT;
264 return SID_SHIFT_1T;
265}
266
0eeede0c
PM		 267/*
268 * This array is indexed by the LP field of the HPTE second dword.
269 * Since this field may contain some RPN bits, some entries are
270 * replicated so that we get the same value irrespective of RPN.
271 * The top 4 bits are the page size index (MMU_PAGE_*) for the
272 * actual page size, the bottom 4 bits are the base page size.
273 */
274extern u8 hpte_page_sizes[1 << LP_BITS];
275
276static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
277 bool is_base_size)
278{
279 unsigned int i, lp;
280
281 if (!(h & HPTE_V_LARGE))
282 return 1ul << 12;
283
284 /* Look at the 8 bit LP value */
285 lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
286 i = hpte_page_sizes[lp];
287 if (!i)
288 return 0;
289 if (!is_base_size)
290 i >>= 4;
291 return 1ul << mmu_psize_defs[i & 0xf].shift;
292}
293
294static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
295{
296 return __hpte_page_size(h, l, 0);
297}
298
299static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
300{
301 return __hpte_page_size(h, l, 1);
302}
303
8d2169e8 304/*
1189be65 305 * The current system page and segment sizes
8d2169e8 306 */
1189be65
PM		 307extern int mmu_kernel_ssize;
308extern int mmu_highuser_ssize;
584f8b71 309extern u16 mmu_slb_size;
572fb578 310extern unsigned long tce_alloc_start, tce_alloc_end;
8d2169e8
DG		 311
312/*
313 * If the processor supports 64k normal pages but not 64k cache
314 * inhibited pages, we have to be prepared to switch processes
315 * to use 4k pages when they create cache-inhibited mappings.
316 * If this is the case, mmu_ci_restrictions will be set to 1.
317 */
318extern int mmu_ci_restrictions;
319
5524a27d
AK		 320/*
321 * This computes the AVPN and B fields of the first dword of a HPTE,
322 * for use when we want to match an existing PTE. The bottom 7 bits
323 * of the returned value are zero.
324 */
325static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
326 int ssize)
327{
328 unsigned long v;
329 /*
330 * The AVA field omits the low-order 23 bits of the 78 bits VA.
331 * These bits are not needed in the PTE, because the
332 * low-order b of these bits are part of the byte offset
333 * into the virtual page and, if b < 23, the high-order
334 * 23-b of these bits are always used in selecting the
335 * PTEGs to be searched
336 */
337 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
338 v <<= HPTE_V_AVPN_SHIFT;
6b243fcf 339 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
5524a27d
AK		 340 return v;
341}
342
6b243fcf
PM		 343/*
344 * ISA v3.0 defines a new HPTE format, which differs from the old
345 * format in having smaller AVPN and ARPN fields, and the B field
346 * in the second dword instead of the first.
347 */
348static inline unsigned long hpte_old_to_new_v(unsigned long v)
349{
350 /* trim AVPN, drop B */
351 return v & HPTE_V_COMMON_BITS;
352}
353
354static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)
355{
356 /* move B field from 1st to 2nd dword, trim ARPN */
357 return (r & ~HPTE_R_3_0_SSIZE_MASK) |
358 (((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
359}
360
361static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)
362{
363 /* insert B field */
364 return (v & HPTE_V_COMMON_BITS) |
365 ((r & HPTE_R_3_0_SSIZE_MASK) <<
366 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));
367}
368
369static inline unsigned long hpte_new_to_old_r(unsigned long r)
370{
371 /* clear out B field */
372 return r & ~HPTE_R_3_0_SSIZE_MASK;
373}
374
a833280b
AK		 375static inline unsigned long hpte_get_old_v(struct hash_pte *hptep)
376{
377 unsigned long hpte_v;
378
379 hpte_v = be64_to_cpu(hptep->v);
380 if (cpu_has_feature(CPU_FTR_ARCH_300))
381 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
382 return hpte_v;
383}
384
8d2169e8
DG		 385/*
386 * This function sets the AVPN and L fields of the HPTE appropriately
b1022fbd 387 * using the base page size and actual page size.
8d2169e8 388 */
b1022fbd
AK		 389static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
390 int actual_psize, int ssize)
8d2169e8 391{
1189be65 392 unsigned long v;
b1022fbd
AK		 393 v = hpte_encode_avpn(vpn, base_psize, ssize);
394 if (actual_psize != MMU_PAGE_4K)
8d2169e8
DG		 395 v |= HPTE_V_LARGE;
396 return v;
397}
398
399/*
400 * This function sets the ARPN, and LP fields of the HPTE appropriately
401 * for the page size. We assume the pa is already "clean" that is properly
402 * aligned for the requested page size
403 */
b1022fbd 404static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
6b243fcf 405 int actual_psize)
8d2169e8 406{
8d2169e8 407 /* A 4K page needs no special encoding */
b1022fbd 408 if (actual_psize == MMU_PAGE_4K)
8d2169e8
DG		 409 return pa & HPTE_R_RPN;
410 else {
b1022fbd
AK		 411 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
412 unsigned int shift = mmu_psize_defs[actual_psize].shift;
413 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
8d2169e8 414 }
8d2169e8
DG		 415}
416
417/*
5524a27d 418 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
8d2169e8 419 */
5524a27d
AK		 420static inline unsigned long hpt_vpn(unsigned long ea,
421 unsigned long vsid, int ssize)
1189be65 422{
5524a27d
AK		 423 unsigned long mask;
424 int s_shift = segment_shift(ssize);
425
426 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
427 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
1189be65 428}
8d2169e8 429
1189be65
PM		 430/*
431 * This hashes a virtual address
432 */
5524a27d
AK		 433static inline unsigned long hpt_hash(unsigned long vpn,
434 unsigned int shift, int ssize)
8d2169e8 435{
59248aec 436 unsigned long mask;
1189be65
PM		 437 unsigned long hash, vsid;
438
5524a27d 439 /* VPN_SHIFT can be atmost 12 */
1189be65 440 if (ssize == MMU_SEGSIZE_256M) {
5524a27d
AK		 441 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
442 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
443 ((vpn & mask) >> (shift - VPN_SHIFT));
1189be65 444 } else {
5524a27d
AK		 445 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
446 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
447 hash = vsid ^ (vsid << 25) ^
448 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
1189be65
PM		 449 }
450 return hash & 0x7fffffffffUL;
8d2169e8
DG		 451}
452
aefa5688
AK		 453#define HPTE_LOCAL_UPDATE 0x1
454#define HPTE_NOHPTE_UPDATE 0x2
d94b827e 455#define HPTE_USE_KERNEL_KEY 0x4
aefa5688 456
8d2169e8
DG		 457extern int __hash_page_4K(unsigned long ea, unsigned long access,
458 unsigned long vsid, pte_t *ptep, unsigned long trap,
aefa5688 459 unsigned long flags, int ssize, int subpage_prot);
8d2169e8
DG		 460extern int __hash_page_64K(unsigned long ea, unsigned long access,
461 unsigned long vsid, pte_t *ptep, unsigned long trap,
aefa5688 462 unsigned long flags, int ssize);
8d2169e8 463struct mm_struct;
0895ecda 464unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
aefa5688
AK		 465extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
466 unsigned long access, unsigned long trap,
467 unsigned long flags);
468extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
469 unsigned long dsisr);
cccaf1a1
CLG		 470void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc);
471int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr, unsigned long msr);
a4fe3ce7 472int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
aefa5688
AK		 473 pte_t *ptep, unsigned long trap, unsigned long flags,
474 int ssize, unsigned int shift, unsigned int mmu_psize);
6d492ecc
AK		 475#ifdef CONFIG_TRANSPARENT_HUGEPAGE
476extern int __hash_page_thp(unsigned long ea, unsigned long access,
477 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
aefa5688 478 unsigned long flags, int ssize, unsigned int psize);
6d492ecc
AK		 479#else
480static inline int __hash_page_thp(unsigned long ea, unsigned long access,
481 unsigned long vsid, pmd_t *pmdp,
aefa5688 482 unsigned long trap, unsigned long flags,
6d492ecc
AK		 483 int ssize, unsigned int psize)
484{
485 BUG();
ff1e7683 486 return -1;
6d492ecc
AK		 487}
488#endif
4b8692c0
BH		 489extern void hash_failure_debug(unsigned long ea, unsigned long access,
490 unsigned long vsid, unsigned long trap,
d8139ebf
AK		 491 int ssize, int psize, int lpsize,
492 unsigned long pte);
8d2169e8 493extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
bc033b63 494 unsigned long pstart, unsigned long prot,
1189be65 495 int psize, int ssize);
f6026df1
AB		 496int htab_remove_mapping(unsigned long vstart, unsigned long vend,
497 int psize, int ssize);
79cc38de 498extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
fa28237c 499extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
8d2169e8 500
425d3314
NP		 501extern void hash__setup_new_exec(void);
502
6364e84e
ME		 503#ifdef CONFIG_PPC_PSERIES
504void hpte_init_pseries(void);
505#else
506static inline void hpte_init_pseries(void) { }
507#endif
508
8d2169e8 509extern void hpte_init_native(void);
8d2169e8 510
c6d15258
MS		 511struct slb_entry {
512 u64 esid;
513 u64 vsid;
514};
515
8d2169e8 516extern void slb_initialize(void);
94ee4272 517void slb_flush_and_restore_bolted(void);
e7e81847
NP		 518void slb_flush_all_realmode(void);
519void __slb_restore_bolted_realmode(void);
520void slb_restore_bolted_realmode(void);
c6d15258
MS		 521void slb_save_contents(struct slb_entry *slb_ptr);
522void slb_dump_contents(struct slb_entry *slb_ptr);
8d2169e8 523
67439b76 524extern void slb_vmalloc_update(void);
46db2f86 525extern void slb_set_size(u16 size);
8d2169e8
DG		 526#endif /* __ASSEMBLY__ */
527
528/*
f033d659 529 * VSID allocation (256MB segment)
8d2169e8 530 *
c60ac569
AK		 531 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
532 * from mmu context id and effective segment id of the address.
8d2169e8 533 *
941711a3 534 * For user processes max context id is limited to MAX_USER_CONTEXT.
4ffe713b
AK		 535 * more details in get_user_context
536 *
537 * For kernel space get_kernel_context
8d2169e8
DG		 538 *
539 * The proto-VSIDs are then scrambled into real VSIDs with the
540 * multiplicative hash:
541 *
542 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
8d2169e8 543 *
f033d659 544 * VSID_MULTIPLIER is prime, so in particular it is
8d2169e8
DG		 545 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
546 * Because the modulus is 2^n-1 we can compute it efficiently without
c60ac569
AK		 547 * a divide or extra multiply (see below). The scramble function gives
548 * robust scattering in the hash table (at least based on some initial
549 * results).
8d2169e8 550 *
941711a3
AK		 551 * We use VSID 0 to indicate an invalid VSID. The means we can't use context id
552 * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which
553 * will produce a VSID of 0.
8d2169e8 554 *
c60ac569
AK		 555 * We also need to avoid the last segment of the last context, because that
556 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
941711a3 557 * because of the modulo operation in vsid scramble.
8d2169e8 558 */
8d2169e8 559
e6f81a92
AK		 560/*
561 * Max Va bits we support as of now is 68 bits. We want 19 bit
562 * context ID.
563 * Restrictions:
564 * GPU has restrictions of not able to access beyond 128TB
565 * (47 bit effective address). We also cannot do more than 20bit PID.
566 * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS
567 * to 16 bits (ie, we can only have 2^16 pids at the same time).
568 */
569#define VA_BITS 68
e39d1a47 570#define CONTEXT_BITS 19
e6f81a92
AK		 571#define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS))
572#define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS))
e39d1a47 573
79270e0a
AK		 574#define ESID_BITS_MASK ((1 << ESID_BITS) - 1)
575#define ESID_BITS_1T_MASK ((1 << ESID_BITS_1T) - 1)
576
4ffe713b
AK		 577/*
578 * Now certain config support MAX_PHYSMEM more than 512TB. Hence we will need
579 * to use more than one context for linear mapping the kernel.
580 * For vmalloc and memmap, we use just one context with 512TB. With 64 byte
581 * struct page size, we need ony 32 TB in memmap for 2PB (51 bits (MAX_PHYSMEM_BITS)).
582 */
b32d5d7e
AK		 583#if (H_MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT)
584#define MAX_KERNEL_CTX_CNT (1UL << (H_MAX_PHYSMEM_BITS - MAX_EA_BITS_PER_CONTEXT))
4ffe713b
AK		 585#else
586#define MAX_KERNEL_CTX_CNT 1
587#endif
588
589#define MAX_VMALLOC_CTX_CNT 1
0034d395
AK		 590#define MAX_IO_CTX_CNT 1
591#define MAX_VMEMMAP_CTX_CNT 1
4ffe713b 592
c60ac569
AK		 593/*
594 * 256MB segment
af81d787 595 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
941711a3
AK		 596 * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts
597 * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each
e6f81a92 598 * context maps 2^49 bytes (512TB).
941711a3
AK		 599 *
600 * We also need to avoid the last segment of the last context, because that
601 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
602 * because of the modulo operation in vsid scramble.
4ffe713b 603 *
c60ac569 604 */
941711a3 605#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2)
5d2e5dd5
AK		 606
607// The + 2 accounts for INVALID_REGION and 1 more to avoid overlap with kernel
4ffe713b 608#define MIN_USER_CONTEXT (MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \
5d2e5dd5
AK		 609 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT + 2)
610
e6f81a92
AK		 611/*
612 * For platforms that support on 65bit VA we limit the context bits
613 */
614#define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2)
615
048ee099
AK		 616/*
617 * This should be computed such that protovosid * vsid_mulitplier
e6f81a92
AK		 618 * doesn't overflow 64 bits. The vsid_mutliplier should also be
619 * co-prime to vsid_modulus. We also need to make sure that number
620 * of bits in multiplied result (dividend) is less than twice the number of
621 * protovsid bits for our modulus optmization to work.
622 *
623 * The below table shows the current values used.
624 * |-------+------------+----------------------+------------+-------------------|
625 * | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS |
626 * |-------+------------+----------------------+------------+-------------------|
627 * | 1T | 24 | 25 | 49 | 50 |
628 * |-------+------------+----------------------+------------+-------------------|
629 * | 256MB | 24 | 37 | 61 | 74 |
630 * |-------+------------+----------------------+------------+-------------------|
631 *
632 * |-------+------------+----------------------+------------+--------------------|
633 * | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS |
634 * |-------+------------+----------------------+------------+--------------------|
635 * | 1T | 24 | 28 | 52 | 56 |
636 * |-------+------------+----------------------+------------+--------------------|
637 * | 256MB | 24 | 40 | 64 | 80 |
638 * |-------+------------+----------------------+------------+--------------------|
639 *
048ee099
AK		 640 */
641#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
e6f81a92
AK		 642#define VSID_BITS_256M (VA_BITS - SID_SHIFT)
643#define VSID_BITS_65_256M (65 - SID_SHIFT)
82228e36
AK		 644/*
645 * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS
646 */
647#define VSID_MULINV_256M ASM_CONST(665548017062)
8d2169e8 648
1189be65 649#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
e6f81a92
AK		 650#define VSID_BITS_1T (VA_BITS - SID_SHIFT_1T)
651#define VSID_BITS_65_1T (65 - SID_SHIFT_1T)
82228e36 652#define VSID_MULINV_1T ASM_CONST(209034062)
8d2169e8 653
82228e36
AK		 654/* 1TB VSID reserved for VRMA */
655#define VRMA_VSID 0x1ffffffUL
af81d787 656#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
8d2169e8 657
78f1dbde 658/* 4 bits per slice and we have one slice per 1TB */
957b778a 659#define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41)
60458fba 660#define LOW_SLICE_ARRAY_SZ (BITS_PER_LONG / BITS_PER_BYTE)
70110186 661#define TASK_SLICE_ARRAY_SZ(x) ((x)->hash_context->slb_addr_limit >> 41)
8d2169e8
DG		 662#ifndef __ASSEMBLY__
663
d28513bc
DG		 664#ifdef CONFIG_PPC_SUBPAGE_PROT
665/*
666 * For the sub-page protection option, we extend the PGD with one of
667 * these. Basically we have a 3-level tree, with the top level being
668 * the protptrs array. To optimize speed and memory consumption when
669 * only addresses < 4GB are being protected, pointers to the first
670 * four pages of sub-page protection words are stored in the low_prot
671 * array.
672 * Each page of sub-page protection words protects 1GB (4 bytes
673 * protects 64k). For the 3-level tree, each page of pointers then
674 * protects 8TB.
675 */
676struct subpage_prot_table {
677 unsigned long maxaddr; /* only addresses < this are protected */
dad6f37c 678 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
d28513bc
DG		 679 unsigned int *low_prot[4];
680};
681
682#define SBP_L1_BITS (PAGE_SHIFT - 2)
683#define SBP_L2_BITS (PAGE_SHIFT - 3)
684#define SBP_L1_COUNT (1 << SBP_L1_BITS)
685#define SBP_L2_COUNT (1 << SBP_L2_BITS)
686#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
687#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
688
689extern void subpage_prot_free(struct mm_struct *mm);
d28513bc
DG		 690#else
691static inline void subpage_prot_free(struct mm_struct *mm) {}
d28513bc
DG		 692#endif /* CONFIG_PPC_SUBPAGE_PROT */
693
70110186
AK		 694/*
695 * One bit per slice. We have lower slices which cover 256MB segments
696 * upto 4G range. That gets us 16 low slices. For the rest we track slices
697 * in 1TB size.
698 */
699struct slice_mask {
700 u64 low_slices;
701 DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
702};
703
704struct hash_mm_context {
705 u16 user_psize; /* page size index */
706
707 /* SLB page size encodings*/
708 unsigned char low_slices_psize[LOW_SLICE_ARRAY_SZ];
709 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
710 unsigned long slb_addr_limit;
711#ifdef CONFIG_PPC_64K_PAGES
712 struct slice_mask mask_64k;
713#endif
714 struct slice_mask mask_4k;
715#ifdef CONFIG_HUGETLB_PAGE
716 struct slice_mask mask_16m;
717 struct slice_mask mask_16g;
718#endif
719
720#ifdef CONFIG_PPC_SUBPAGE_PROT
ef629cc5 721 struct subpage_prot_table *spt;
70110186
AK		 722#endif /* CONFIG_PPC_SUBPAGE_PROT */
723};
724
8d2169e8 725#if 0
1189be65
PM		 726/*
727 * The code below is equivalent to this function for arguments
728 * < 2^VSID_BITS, which is all this should ever be called
729 * with. However gcc is not clever enough to compute the
730 * modulus (2^n-1) without a second multiply.
731 */
34692708 732#define vsid_scramble(protovsid, size) \
1189be65 733 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
8d2169e8 734
e6f81a92 735/* simplified form avoiding mod operation */
1189be65
PM		 736#define vsid_scramble(protovsid, size) \
737 ({ \
738 unsigned long x; \
739 x = (protovsid) * VSID_MULTIPLIER_##size; \
740 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
741 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
742 })
e6f81a92
AK		 743
744#else /* 1 */
745static inline unsigned long vsid_scramble(unsigned long protovsid,
746 unsigned long vsid_multiplier, int vsid_bits)
747{
748 unsigned long vsid;
749 unsigned long vsid_modulus = ((1UL << vsid_bits) - 1);
750 /*
751 * We have same multipler for both 256 and 1T segements now
752 */
753 vsid = protovsid * vsid_multiplier;
754 vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus);
755 return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus;
756}
757
8d2169e8 758#endif /* 1 */
8d2169e8 759
1189be65
PM		 760/* Returns the segment size indicator for a user address */
761static inline int user_segment_size(unsigned long addr)
8d2169e8 762{
1189be65
PM		 763 /* Use 1T segments if possible for addresses >= 1T */
764 if (addr >= (1UL << SID_SHIFT_1T))
765 return mmu_highuser_ssize;
766 return MMU_SEGSIZE_256M;
8d2169e8
DG		 767}
768
1189be65
PM		 769static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
770 int ssize)
771{
e6f81a92
AK		 772 unsigned long va_bits = VA_BITS;
773 unsigned long vsid_bits;
774 unsigned long protovsid;
775
c60ac569
AK		 776 /*
777 * Bad address. We return VSID 0 for that
778 */
0034d395 779 if ((ea & EA_MASK) >= H_PGTABLE_RANGE)
c60ac569
AK		 780 return 0;
781
e6f81a92
AK		 782 if (!mmu_has_feature(MMU_FTR_68_BIT_VA))
783 va_bits = 65;
784
785 if (ssize == MMU_SEGSIZE_256M) {
786 vsid_bits = va_bits - SID_SHIFT;
787 protovsid = (context << ESID_BITS) |
788 ((ea >> SID_SHIFT) & ESID_BITS_MASK);
789 return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits);
790 }
791 /* 1T segment */
792 vsid_bits = va_bits - SID_SHIFT_1T;
793 protovsid = (context << ESID_BITS_1T) |
794 ((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK);
795 return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits);
1189be65
PM		 796}
797
4ffe713b 798/*
10a4a016 799 * For kernel space, we use context ids as
4ffe713b
AK		 800 * below. Range is 512TB per context.
801 *
802 * 0x00001 - [ 0xc000000000000000 - 0xc001ffffffffffff]
803 * 0x00002 - [ 0xc002000000000000 - 0xc003ffffffffffff]
804 * 0x00003 - [ 0xc004000000000000 - 0xc005ffffffffffff]
805 * 0x00004 - [ 0xc006000000000000 - 0xc007ffffffffffff]
4ffe713b 806 *
0034d395
AK		 807 * vmap, IO, vmemap
808 *
809 * 0x00005 - [ 0xc008000000000000 - 0xc009ffffffffffff]
810 * 0x00006 - [ 0xc00a000000000000 - 0xc00bffffffffffff]
811 * 0x00007 - [ 0xc00c000000000000 - 0xc00dffffffffffff]
812 *
4ffe713b
AK		 813 */
814static inline unsigned long get_kernel_context(unsigned long ea)
815{
0034d395 816 unsigned long region_id = get_region_id(ea);
4ffe713b
AK		 817 unsigned long ctx;
818 /*
0034d395
AK		 819 * Depending on Kernel config, kernel region can have one context
820 * or more.
4ffe713b 821 */
5f53d286 822 if (region_id == LINEAR_MAP_REGION_ID) {
4ffe713b
AK		 823 /*
824 * We already verified ea to be not beyond the addr limit.
825 */
0034d395 826 ctx = 1 + ((ea & EA_MASK) >> MAX_EA_BITS_PER_CONTEXT);
4ffe713b 827 } else
1c946c1b 828 ctx = region_id + MAX_KERNEL_CTX_CNT - 1;
4ffe713b
AK		 829 return ctx;
830}
831
c60ac569
AK		 832/*
833 * This is only valid for addresses >= PAGE_OFFSET
c60ac569
AK		 834 */
835static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
836{
837 unsigned long context;
838
85beb1c4
ME		 839 if (!is_kernel_addr(ea))
840 return 0;
841
4ffe713b 842 context = get_kernel_context(ea);
c60ac569
AK		 843 return get_vsid(context, ea, ssize);
844}
5c3c7ede
DG		 845
846unsigned htab_shift_for_mem_size(unsigned long mem_size);
847
3ba150fb
GG		 848enum slb_index {
849 LINEAR_INDEX = 0, /* Kernel linear map (0xc000000000000000) */
850 KSTACK_INDEX = 1, /* Kernel stack map */
851};
8d2169e8 852
3ba150fb
GG		 853#define slb_esid_mask(ssize) \
854 (((ssize) == MMU_SEGSIZE_256M) ? ESID_MASK : ESID_MASK_1T)
855
856static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
857 enum slb_index index)
858{
859 return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
860}
861
862static inline unsigned long __mk_vsid_data(unsigned long vsid, int ssize,
863 unsigned long flags)
864{
865 return (vsid << slb_vsid_shift(ssize)) | flags |
866 ((unsigned long)ssize << SLB_VSID_SSIZE_SHIFT);
867}
868
869static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
870 unsigned long flags)
871{
872 return __mk_vsid_data(get_kernel_vsid(ea, ssize), ssize, flags);
873}
874
875#endif /* __ASSEMBLY__ */
11a6f6ab 876#endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */
Linux 6.x block layer and io_uring tree(s)