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Merge tag 'spi-fix-v4.20-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/brooni...
[linux-2.6-block.git] / arch / powerpc / include / asm / book3s / 64 / mmu-hash.h
CommitLineData
11a6f6ab
AK		 1#ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
2#define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
8d2169e8
DG		 3/*
4 * PowerPC64 memory management structures
5 *
6 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
7 * PPC64 rework.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
8d2169e8 15#include <asm/page.h>
891121e6 16#include <asm/bug.h>
ec0c464c 17#include <asm/asm-const.h>
8d2169e8 18
78f1dbde
AK		 19/*
20 * This is necessary to get the definition of PGTABLE_RANGE which we
21 * need for various slices related matters. Note that this isn't the
22 * complete pgtable.h but only a portion of it.
23 */
3dfcb315 24#include <asm/book3s/64/pgtable.h>
cf9427b8 25#include <asm/bug.h>
dad6f37c 26#include <asm/processor.h>
b92a226e 27#include <asm/cpu_has_feature.h>
78f1dbde 28
8d2169e8
DG		 29/*
30 * SLB
31 */
32
85376e2a 33#define SLB_NUM_BOLTED 2
8d2169e8 34#define SLB_CACHE_ENTRIES 8
46db2f86 35#define SLB_MIN_SIZE 32
8d2169e8
DG		 36
37/* Bits in the SLB ESID word */
38#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
39
40/* Bits in the SLB VSID word */
41#define SLB_VSID_SHIFT 12
e6f81a92 42#define SLB_VSID_SHIFT_256M SLB_VSID_SHIFT
1189be65
PM		 43#define SLB_VSID_SHIFT_1T 24
44#define SLB_VSID_SSIZE_SHIFT 62
8d2169e8
DG		 45#define SLB_VSID_B ASM_CONST(0xc000000000000000)
46#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
47#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
48#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
49#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
50#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
51#define SLB_VSID_L ASM_CONST(0x0000000000000100)
52#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
53#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
54#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
55#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
56#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
57#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
58#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
59
60#define SLB_VSID_KERNEL (SLB_VSID_KP)
61#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
62
63#define SLBIE_C (0x08000000)
1189be65 64#define SLBIE_SSIZE_SHIFT 25
8d2169e8
DG		 65
66/*
67 * Hash table
68 */
69
70#define HPTES_PER_GROUP 8
71
2454c7e9 72#define HPTE_V_SSIZE_SHIFT 62
8d2169e8 73#define HPTE_V_AVPN_SHIFT 7
6b243fcf 74#define HPTE_V_COMMON_BITS ASM_CONST(0x000fffffffffffff)
2454c7e9 75#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
6b243fcf 76#define HPTE_V_AVPN_3_0 ASM_CONST(0x000fffffffffff80)
8d2169e8 77#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
91bbbe22 78#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
8d2169e8
DG		 79#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
80#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
81#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
82#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
83#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
84
50de596d 85/*
6b243fcf 86 * ISA 3.0 has a different HPTE format.
50de596d
AK		 87 */
88#define HPTE_R_3_0_SSIZE_SHIFT 58
6b243fcf 89#define HPTE_R_3_0_SSIZE_MASK (3ull << HPTE_R_3_0_SSIZE_SHIFT)
8d2169e8
DG		 90#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
91#define HPTE_R_TS ASM_CONST(0x4000000000000000)
de56a948 92#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
a6590ca5
RP		 93#define HPTE_R_KEY_BIT0 ASM_CONST(0x2000000000000000)
94#define HPTE_R_KEY_BIT1 ASM_CONST(0x1000000000000000)
8d2169e8 95#define HPTE_R_RPN_SHIFT 12
de56a948 96#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
6b243fcf 97#define HPTE_R_RPN_3_0 ASM_CONST(0x01fffffffffff000)
8d2169e8 98#define HPTE_R_PP ASM_CONST(0x0000000000000003)
8550e2fa 99#define HPTE_R_PPP ASM_CONST(0x8000000000000003)
8d2169e8 100#define HPTE_R_N ASM_CONST(0x0000000000000004)
de56a948
PM		 101#define HPTE_R_G ASM_CONST(0x0000000000000008)
102#define HPTE_R_M ASM_CONST(0x0000000000000010)
103#define HPTE_R_I ASM_CONST(0x0000000000000020)
104#define HPTE_R_W ASM_CONST(0x0000000000000040)
105#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
8d2169e8
DG		 106#define HPTE_R_C ASM_CONST(0x0000000000000080)
107#define HPTE_R_R ASM_CONST(0x0000000000000100)
de56a948 108#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
a6590ca5
RP		 109#define HPTE_R_KEY_BIT2 ASM_CONST(0x0000000000000800)
110#define HPTE_R_KEY_BIT3 ASM_CONST(0x0000000000000400)
111#define HPTE_R_KEY_BIT4 ASM_CONST(0x0000000000000200)
d182b8fd 112#define HPTE_R_KEY (HPTE_R_KEY_LO | HPTE_R_KEY_HI)
8d2169e8 113
b7abc5c5
SS		 114#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
115#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
116
8d2169e8 117/* Values for PP (assumes Ks=0, Kp=1) */
8d2169e8
DG		 118#define PP_RWXX 0 /* Supervisor read/write, User none */
119#define PP_RWRX 1 /* Supervisor read/write, User read */
120#define PP_RWRW 2 /* Supervisor read/write, User read/write */
121#define PP_RXRX 3 /* Supervisor read, User read */
697d3899 122#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
8d2169e8 123
b4072df4
PM		 124/* Fields for tlbiel instruction in architecture 2.06 */
125#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
126#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
127#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
128#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
129#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
130#define TLBIEL_INVAL_SET_SHIFT 12
131
132#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
45706bb5 133#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
c3ab300e 134#define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
1a472c9d 135#define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
b4072df4 136
8d2169e8
DG		 137#ifndef __ASSEMBLY__
138
7025776e
BH		 139struct mmu_hash_ops {
140 void (*hpte_invalidate)(unsigned long slot,
141 unsigned long vpn,
142 int bpsize, int apsize,
143 int ssize, int local);
144 long (*hpte_updatepp)(unsigned long slot,
145 unsigned long newpp,
146 unsigned long vpn,
147 int bpsize, int apsize,
148 int ssize, unsigned long flags);
149 void (*hpte_updateboltedpp)(unsigned long newpp,
150 unsigned long ea,
151 int psize, int ssize);
152 long (*hpte_insert)(unsigned long hpte_group,
153 unsigned long vpn,
154 unsigned long prpn,
155 unsigned long rflags,
156 unsigned long vflags,
157 int psize, int apsize,
158 int ssize);
159 long (*hpte_remove)(unsigned long hpte_group);
160 int (*hpte_removebolted)(unsigned long ea,
161 int psize, int ssize);
162 void (*flush_hash_range)(unsigned long number, int local);
163 void (*hugepage_invalidate)(unsigned long vsid,
164 unsigned long addr,
165 unsigned char *hpte_slot_array,
166 int psize, int ssize, int local);
dbcf929c 167 int (*resize_hpt)(unsigned long shift);
7025776e
BH		 168 /*
169 * Special for kexec.
170 * To be called in real mode with interrupts disabled. No locks are
171 * taken as such, concurrent access on pre POWER5 hardware could result
172 * in a deadlock.
173 * The linear mapping is destroyed as well.
174 */
175 void (*hpte_clear_all)(void);
176};
177extern struct mmu_hash_ops mmu_hash_ops;
178
8e561e7e 179struct hash_pte {
12f04f2b
AB		 180 __be64 v;
181 __be64 r;
8e561e7e 182};
8d2169e8 183
8e561e7e 184extern struct hash_pte *htab_address;
8d2169e8
DG		 185extern unsigned long htab_size_bytes;
186extern unsigned long htab_hash_mask;
187
cf9427b8
AK		 188
189static inline int shift_to_mmu_psize(unsigned int shift)
190{
191 int psize;
192
193 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
194 if (mmu_psize_defs[psize].shift == shift)
195 return psize;
196 return -1;
197}
198
199static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
200{
201 if (mmu_psize_defs[mmu_psize].shift)
202 return mmu_psize_defs[mmu_psize].shift;
203 BUG();
204}
8d2169e8 205
e3b6b466
SJS		 206static inline unsigned int ap_to_shift(unsigned long ap)
207{
208 int psize;
209
210 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
211 if (mmu_psize_defs[psize].ap == ap)
212 return mmu_psize_defs[psize].shift;
213 }
214
215 return -1;
216}
217
138ee7ee
AK		 218static inline unsigned long get_sllp_encoding(int psize)
219{
220 unsigned long sllp;
221
222 sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) |
223 ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4);
224 return sllp;
225}
226
8d2169e8
DG		 227#endif /* __ASSEMBLY__ */
228
2454c7e9
PM		 229/*
230 * Segment sizes.
231 * These are the values used by hardware in the B field of
232 * SLB entries and the first dword of MMU hashtable entries.
233 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
234 */
235#define MMU_SEGSIZE_256M 0
236#define MMU_SEGSIZE_1T 1
237
5524a27d
AK		 238/*
239 * encode page number shift.
240 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
241 * 12 bits. This enable us to address upto 76 bit va.
242 * For hpt hash from a va we can ignore the page size bits of va and for
243 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
244 * we work in all cases including 4k page size.
245 */
246#define VPN_SHIFT 12
1189be65 247
b1022fbd
AK		 248/*
249 * HPTE Large Page (LP) details
250 */
251#define LP_SHIFT 12
252#define LP_BITS 8
253#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
254
8d2169e8
DG		 255#ifndef __ASSEMBLY__
256
73d16a6e
IM		 257static inline int slb_vsid_shift(int ssize)
258{
259 if (ssize == MMU_SEGSIZE_256M)
260 return SLB_VSID_SHIFT;
261 return SLB_VSID_SHIFT_1T;
262}
263
5524a27d
AK		 264static inline int segment_shift(int ssize)
265{
266 if (ssize == MMU_SEGSIZE_256M)
267 return SID_SHIFT;
268 return SID_SHIFT_1T;
269}
270
0eeede0c
PM		 271/*
272 * This array is indexed by the LP field of the HPTE second dword.
273 * Since this field may contain some RPN bits, some entries are
274 * replicated so that we get the same value irrespective of RPN.
275 * The top 4 bits are the page size index (MMU_PAGE_*) for the
276 * actual page size, the bottom 4 bits are the base page size.
277 */
278extern u8 hpte_page_sizes[1 << LP_BITS];
279
280static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
281 bool is_base_size)
282{
283 unsigned int i, lp;
284
285 if (!(h & HPTE_V_LARGE))
286 return 1ul << 12;
287
288 /* Look at the 8 bit LP value */
289 lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
290 i = hpte_page_sizes[lp];
291 if (!i)
292 return 0;
293 if (!is_base_size)
294 i >>= 4;
295 return 1ul << mmu_psize_defs[i & 0xf].shift;
296}
297
298static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
299{
300 return __hpte_page_size(h, l, 0);
301}
302
303static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
304{
305 return __hpte_page_size(h, l, 1);
306}
307
8d2169e8 308/*
1189be65 309 * The current system page and segment sizes
8d2169e8 310 */
1189be65
PM		 311extern int mmu_kernel_ssize;
312extern int mmu_highuser_ssize;
584f8b71 313extern u16 mmu_slb_size;
572fb578 314extern unsigned long tce_alloc_start, tce_alloc_end;
8d2169e8
DG		 315
316/*
317 * If the processor supports 64k normal pages but not 64k cache
318 * inhibited pages, we have to be prepared to switch processes
319 * to use 4k pages when they create cache-inhibited mappings.
320 * If this is the case, mmu_ci_restrictions will be set to 1.
321 */
322extern int mmu_ci_restrictions;
323
5524a27d
AK		 324/*
325 * This computes the AVPN and B fields of the first dword of a HPTE,
326 * for use when we want to match an existing PTE. The bottom 7 bits
327 * of the returned value are zero.
328 */
329static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
330 int ssize)
331{
332 unsigned long v;
333 /*
334 * The AVA field omits the low-order 23 bits of the 78 bits VA.
335 * These bits are not needed in the PTE, because the
336 * low-order b of these bits are part of the byte offset
337 * into the virtual page and, if b < 23, the high-order
338 * 23-b of these bits are always used in selecting the
339 * PTEGs to be searched
340 */
341 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
342 v <<= HPTE_V_AVPN_SHIFT;
6b243fcf 343 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
5524a27d
AK		 344 return v;
345}
346
6b243fcf
PM		 347/*
348 * ISA v3.0 defines a new HPTE format, which differs from the old
349 * format in having smaller AVPN and ARPN fields, and the B field
350 * in the second dword instead of the first.
351 */
352static inline unsigned long hpte_old_to_new_v(unsigned long v)
353{
354 /* trim AVPN, drop B */
355 return v & HPTE_V_COMMON_BITS;
356}
357
358static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)
359{
360 /* move B field from 1st to 2nd dword, trim ARPN */
361 return (r & ~HPTE_R_3_0_SSIZE_MASK) |
362 (((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
363}
364
365static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)
366{
367 /* insert B field */
368 return (v & HPTE_V_COMMON_BITS) |
369 ((r & HPTE_R_3_0_SSIZE_MASK) <<
370 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));
371}
372
373static inline unsigned long hpte_new_to_old_r(unsigned long r)
374{
375 /* clear out B field */
376 return r & ~HPTE_R_3_0_SSIZE_MASK;
377}
378
a833280b
AK		 379static inline unsigned long hpte_get_old_v(struct hash_pte *hptep)
380{
381 unsigned long hpte_v;
382
383 hpte_v = be64_to_cpu(hptep->v);
384 if (cpu_has_feature(CPU_FTR_ARCH_300))
385 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
386 return hpte_v;
387}
388
8d2169e8
DG		 389/*
390 * This function sets the AVPN and L fields of the HPTE appropriately
b1022fbd 391 * using the base page size and actual page size.
8d2169e8 392 */
b1022fbd
AK		 393static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
394 int actual_psize, int ssize)
8d2169e8 395{
1189be65 396 unsigned long v;
b1022fbd
AK		 397 v = hpte_encode_avpn(vpn, base_psize, ssize);
398 if (actual_psize != MMU_PAGE_4K)
8d2169e8
DG		 399 v |= HPTE_V_LARGE;
400 return v;
401}
402
403/*
404 * This function sets the ARPN, and LP fields of the HPTE appropriately
405 * for the page size. We assume the pa is already "clean" that is properly
406 * aligned for the requested page size
407 */
b1022fbd 408static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
6b243fcf 409 int actual_psize)
8d2169e8 410{
8d2169e8 411 /* A 4K page needs no special encoding */
b1022fbd 412 if (actual_psize == MMU_PAGE_4K)
8d2169e8
DG		 413 return pa & HPTE_R_RPN;
414 else {
b1022fbd
AK		 415 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
416 unsigned int shift = mmu_psize_defs[actual_psize].shift;
417 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
8d2169e8 418 }
8d2169e8
DG		 419}
420
421/*
5524a27d 422 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
8d2169e8 423 */
5524a27d
AK		 424static inline unsigned long hpt_vpn(unsigned long ea,
425 unsigned long vsid, int ssize)
1189be65 426{
5524a27d
AK		 427 unsigned long mask;
428 int s_shift = segment_shift(ssize);
429
430 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
431 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
1189be65 432}
8d2169e8 433
1189be65
PM		 434/*
435 * This hashes a virtual address
436 */
5524a27d
AK		 437static inline unsigned long hpt_hash(unsigned long vpn,
438 unsigned int shift, int ssize)
8d2169e8 439{
59248aec 440 unsigned long mask;
1189be65
PM		 441 unsigned long hash, vsid;
442
5524a27d 443 /* VPN_SHIFT can be atmost 12 */
1189be65 444 if (ssize == MMU_SEGSIZE_256M) {
5524a27d
AK		 445 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
446 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
447 ((vpn & mask) >> (shift - VPN_SHIFT));
1189be65 448 } else {
5524a27d
AK		 449 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
450 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
451 hash = vsid ^ (vsid << 25) ^
452 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
1189be65
PM		 453 }
454 return hash & 0x7fffffffffUL;
8d2169e8
DG		 455}
456
aefa5688
AK		 457#define HPTE_LOCAL_UPDATE 0x1
458#define HPTE_NOHPTE_UPDATE 0x2
459
8d2169e8
DG		 460extern int __hash_page_4K(unsigned long ea, unsigned long access,
461 unsigned long vsid, pte_t *ptep, unsigned long trap,
aefa5688 462 unsigned long flags, int ssize, int subpage_prot);
8d2169e8
DG		 463extern int __hash_page_64K(unsigned long ea, unsigned long access,
464 unsigned long vsid, pte_t *ptep, unsigned long trap,
aefa5688 465 unsigned long flags, int ssize);
8d2169e8 466struct mm_struct;
0895ecda 467unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
aefa5688
AK		 468extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
469 unsigned long access, unsigned long trap,
470 unsigned long flags);
471extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
472 unsigned long dsisr);
a4fe3ce7 473int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
aefa5688
AK		 474 pte_t *ptep, unsigned long trap, unsigned long flags,
475 int ssize, unsigned int shift, unsigned int mmu_psize);
6d492ecc
AK		 476#ifdef CONFIG_TRANSPARENT_HUGEPAGE
477extern int __hash_page_thp(unsigned long ea, unsigned long access,
478 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
aefa5688 479 unsigned long flags, int ssize, unsigned int psize);
6d492ecc
AK		 480#else
481static inline int __hash_page_thp(unsigned long ea, unsigned long access,
482 unsigned long vsid, pmd_t *pmdp,
aefa5688 483 unsigned long trap, unsigned long flags,
6d492ecc
AK		 484 int ssize, unsigned int psize)
485{
486 BUG();
ff1e7683 487 return -1;
6d492ecc
AK		 488}
489#endif
4b8692c0
BH		 490extern void hash_failure_debug(unsigned long ea, unsigned long access,
491 unsigned long vsid, unsigned long trap,
d8139ebf
AK		 492 int ssize, int psize, int lpsize,
493 unsigned long pte);
8d2169e8 494extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
bc033b63 495 unsigned long pstart, unsigned long prot,
1189be65 496 int psize, int ssize);
f6026df1
AB		 497int htab_remove_mapping(unsigned long vstart, unsigned long vend,
498 int psize, int ssize);
79cc38de 499extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
fa28237c 500extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
8d2169e8 501
425d3314
NP		 502extern void hash__setup_new_exec(void);
503
6364e84e
ME		 504#ifdef CONFIG_PPC_PSERIES
505void hpte_init_pseries(void);
506#else
507static inline void hpte_init_pseries(void) { }
508#endif
509
8d2169e8 510extern void hpte_init_native(void);
8d2169e8 511
c6d15258
MS		 512struct slb_entry {
513 u64 esid;
514 u64 vsid;
515};
516
8d2169e8 517extern void slb_initialize(void);
94ee4272 518void slb_flush_and_restore_bolted(void);
e7e81847
NP		 519void slb_flush_all_realmode(void);
520void __slb_restore_bolted_realmode(void);
521void slb_restore_bolted_realmode(void);
c6d15258
MS		 522void slb_save_contents(struct slb_entry *slb_ptr);
523void slb_dump_contents(struct slb_entry *slb_ptr);
8d2169e8 524
67439b76 525extern void slb_vmalloc_update(void);
46db2f86 526extern void slb_set_size(u16 size);
8d2169e8
DG		 527#endif /* __ASSEMBLY__ */
528
529/*
f033d659 530 * VSID allocation (256MB segment)
8d2169e8 531 *
c60ac569
AK		 532 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
533 * from mmu context id and effective segment id of the address.
8d2169e8 534 *
941711a3 535 * For user processes max context id is limited to MAX_USER_CONTEXT.
4ffe713b
AK		 536 * more details in get_user_context
537 *
538 * For kernel space get_kernel_context
8d2169e8
DG		 539 *
540 * The proto-VSIDs are then scrambled into real VSIDs with the
541 * multiplicative hash:
542 *
543 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
8d2169e8 544 *
f033d659 545 * VSID_MULTIPLIER is prime, so in particular it is
8d2169e8
DG		 546 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
547 * Because the modulus is 2^n-1 we can compute it efficiently without
c60ac569
AK		 548 * a divide or extra multiply (see below). The scramble function gives
549 * robust scattering in the hash table (at least based on some initial
550 * results).
8d2169e8 551 *
941711a3
AK		 552 * We use VSID 0 to indicate an invalid VSID. The means we can't use context id
553 * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which
554 * will produce a VSID of 0.
8d2169e8 555 *
c60ac569
AK		 556 * We also need to avoid the last segment of the last context, because that
557 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
941711a3 558 * because of the modulo operation in vsid scramble.
8d2169e8 559 */
8d2169e8 560
e6f81a92
AK		 561/*
562 * Max Va bits we support as of now is 68 bits. We want 19 bit
563 * context ID.
564 * Restrictions:
565 * GPU has restrictions of not able to access beyond 128TB
566 * (47 bit effective address). We also cannot do more than 20bit PID.
567 * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS
568 * to 16 bits (ie, we can only have 2^16 pids at the same time).
569 */
570#define VA_BITS 68
e39d1a47 571#define CONTEXT_BITS 19
e6f81a92
AK		 572#define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS))
573#define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS))
e39d1a47 574
79270e0a
AK		 575#define ESID_BITS_MASK ((1 << ESID_BITS) - 1)
576#define ESID_BITS_1T_MASK ((1 << ESID_BITS_1T) - 1)
577
4ffe713b
AK		 578/*
579 * Now certain config support MAX_PHYSMEM more than 512TB. Hence we will need
580 * to use more than one context for linear mapping the kernel.
581 * For vmalloc and memmap, we use just one context with 512TB. With 64 byte
582 * struct page size, we need ony 32 TB in memmap for 2PB (51 bits (MAX_PHYSMEM_BITS)).
583 */
584#if (MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT)
585#define MAX_KERNEL_CTX_CNT (1UL << (MAX_PHYSMEM_BITS - MAX_EA_BITS_PER_CONTEXT))
586#else
587#define MAX_KERNEL_CTX_CNT 1
588#endif
589
590#define MAX_VMALLOC_CTX_CNT 1
591#define MAX_MEMMAP_CTX_CNT 1
592
c60ac569
AK		 593/*
594 * 256MB segment
af81d787 595 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
941711a3
AK		 596 * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts
597 * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each
e6f81a92 598 * context maps 2^49 bytes (512TB).
941711a3
AK		 599 *
600 * We also need to avoid the last segment of the last context, because that
601 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
602 * because of the modulo operation in vsid scramble.
4ffe713b
AK		 603 *
604 * We add one extra context to MIN_USER_CONTEXT so that we can map kernel
605 * context easily. The +1 is to map the unused 0xe region mapping.
c60ac569 606 */
941711a3 607#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2)
4ffe713b
AK		 608#define MIN_USER_CONTEXT (MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \
609 MAX_MEMMAP_CTX_CNT + 2)
c60ac569 610
e6f81a92
AK		 611/*
612 * For platforms that support on 65bit VA we limit the context bits
613 */
614#define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2)
615
048ee099
AK		 616/*
617 * This should be computed such that protovosid * vsid_mulitplier
e6f81a92
AK		 618 * doesn't overflow 64 bits. The vsid_mutliplier should also be
619 * co-prime to vsid_modulus. We also need to make sure that number
620 * of bits in multiplied result (dividend) is less than twice the number of
621 * protovsid bits for our modulus optmization to work.
622 *
623 * The below table shows the current values used.
624 * |-------+------------+----------------------+------------+-------------------|
625 * | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS |
626 * |-------+------------+----------------------+------------+-------------------|
627 * | 1T | 24 | 25 | 49 | 50 |
628 * |-------+------------+----------------------+------------+-------------------|
629 * | 256MB | 24 | 37 | 61 | 74 |
630 * |-------+------------+----------------------+------------+-------------------|
631 *
632 * |-------+------------+----------------------+------------+--------------------|
633 * | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS |
634 * |-------+------------+----------------------+------------+--------------------|
635 * | 1T | 24 | 28 | 52 | 56 |
636 * |-------+------------+----------------------+------------+--------------------|
637 * | 256MB | 24 | 40 | 64 | 80 |
638 * |-------+------------+----------------------+------------+--------------------|
639 *
048ee099
AK		 640 */
641#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
e6f81a92
AK		 642#define VSID_BITS_256M (VA_BITS - SID_SHIFT)
643#define VSID_BITS_65_256M (65 - SID_SHIFT)
82228e36
AK		 644/*
645 * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS
646 */
647#define VSID_MULINV_256M ASM_CONST(665548017062)
8d2169e8 648
1189be65 649#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
e6f81a92
AK		 650#define VSID_BITS_1T (VA_BITS - SID_SHIFT_1T)
651#define VSID_BITS_65_1T (65 - SID_SHIFT_1T)
82228e36 652#define VSID_MULINV_1T ASM_CONST(209034062)
8d2169e8 653
82228e36
AK		 654/* 1TB VSID reserved for VRMA */
655#define VRMA_VSID 0x1ffffffUL
af81d787 656#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
8d2169e8 657
78f1dbde 658/* 4 bits per slice and we have one slice per 1TB */
957b778a 659#define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41)
4722476b 660#define TASK_SLICE_ARRAY_SZ(x) ((x)->context.slb_addr_limit >> 41)
8d2169e8
DG		 661
662#ifndef __ASSEMBLY__
663
d28513bc
DG		 664#ifdef CONFIG_PPC_SUBPAGE_PROT
665/*
666 * For the sub-page protection option, we extend the PGD with one of
667 * these. Basically we have a 3-level tree, with the top level being
668 * the protptrs array. To optimize speed and memory consumption when
669 * only addresses < 4GB are being protected, pointers to the first
670 * four pages of sub-page protection words are stored in the low_prot
671 * array.
672 * Each page of sub-page protection words protects 1GB (4 bytes
673 * protects 64k). For the 3-level tree, each page of pointers then
674 * protects 8TB.
675 */
676struct subpage_prot_table {
677 unsigned long maxaddr; /* only addresses < this are protected */
dad6f37c 678 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
d28513bc
DG		 679 unsigned int *low_prot[4];
680};
681
682#define SBP_L1_BITS (PAGE_SHIFT - 2)
683#define SBP_L2_BITS (PAGE_SHIFT - 3)
684#define SBP_L1_COUNT (1 << SBP_L1_BITS)
685#define SBP_L2_COUNT (1 << SBP_L2_BITS)
686#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
687#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
688
689extern void subpage_prot_free(struct mm_struct *mm);
690extern void subpage_prot_init_new_context(struct mm_struct *mm);
691#else
692static inline void subpage_prot_free(struct mm_struct *mm) {}
693static inline void subpage_prot_init_new_context(struct mm_struct *mm) { }
694#endif /* CONFIG_PPC_SUBPAGE_PROT */
695
8d2169e8 696#if 0
1189be65
PM		 697/*
698 * The code below is equivalent to this function for arguments
699 * < 2^VSID_BITS, which is all this should ever be called
700 * with. However gcc is not clever enough to compute the
701 * modulus (2^n-1) without a second multiply.
702 */
34692708 703#define vsid_scramble(protovsid, size) \
1189be65 704 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
8d2169e8 705
e6f81a92 706/* simplified form avoiding mod operation */
1189be65
PM		 707#define vsid_scramble(protovsid, size) \
708 ({ \
709 unsigned long x; \
710 x = (protovsid) * VSID_MULTIPLIER_##size; \
711 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
712 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
713 })
e6f81a92
AK		 714
715#else /* 1 */
716static inline unsigned long vsid_scramble(unsigned long protovsid,
717 unsigned long vsid_multiplier, int vsid_bits)
718{
719 unsigned long vsid;
720 unsigned long vsid_modulus = ((1UL << vsid_bits) - 1);
721 /*
722 * We have same multipler for both 256 and 1T segements now
723 */
724 vsid = protovsid * vsid_multiplier;
725 vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus);
726 return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus;
727}
728
8d2169e8 729#endif /* 1 */
8d2169e8 730
1189be65
PM		 731/* Returns the segment size indicator for a user address */
732static inline int user_segment_size(unsigned long addr)
8d2169e8 733{
1189be65
PM		 734 /* Use 1T segments if possible for addresses >= 1T */
735 if (addr >= (1UL << SID_SHIFT_1T))
736 return mmu_highuser_ssize;
737 return MMU_SEGSIZE_256M;
8d2169e8
DG		 738}
739
1189be65
PM		 740static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
741 int ssize)
742{
e6f81a92
AK		 743 unsigned long va_bits = VA_BITS;
744 unsigned long vsid_bits;
745 unsigned long protovsid;
746
c60ac569
AK		 747 /*
748 * Bad address. We return VSID 0 for that
749 */
dd1842a2 750 if ((ea & ~REGION_MASK) >= H_PGTABLE_RANGE)
c60ac569
AK		 751 return 0;
752
e6f81a92
AK		 753 if (!mmu_has_feature(MMU_FTR_68_BIT_VA))
754 va_bits = 65;
755
756 if (ssize == MMU_SEGSIZE_256M) {
757 vsid_bits = va_bits - SID_SHIFT;
758 protovsid = (context << ESID_BITS) |
759 ((ea >> SID_SHIFT) & ESID_BITS_MASK);
760 return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits);
761 }
762 /* 1T segment */
763 vsid_bits = va_bits - SID_SHIFT_1T;
764 protovsid = (context << ESID_BITS_1T) |
765 ((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK);
766 return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits);
1189be65
PM		 767}
768
4ffe713b
AK		 769/*
770 * For kernel space, we use context ids as below
771 * below. Range is 512TB per context.
772 *
773 * 0x00001 - [ 0xc000000000000000 - 0xc001ffffffffffff]
774 * 0x00002 - [ 0xc002000000000000 - 0xc003ffffffffffff]
775 * 0x00003 - [ 0xc004000000000000 - 0xc005ffffffffffff]
776 * 0x00004 - [ 0xc006000000000000 - 0xc007ffffffffffff]
777
778 * 0x00005 - [ 0xd000000000000000 - 0xd001ffffffffffff ]
779 * 0x00006 - Not used - Can map 0xe000000000000000 range.
780 * 0x00007 - [ 0xf000000000000000 - 0xf001ffffffffffff ]
781 *
782 * So we can compute the context from the region (top nibble) by
783 * subtracting 11, or 0xc - 1.
784 */
785static inline unsigned long get_kernel_context(unsigned long ea)
786{
787 unsigned long region_id = REGION_ID(ea);
788 unsigned long ctx;
789 /*
790 * For linear mapping we do support multiple context
791 */
792 if (region_id == KERNEL_REGION_ID) {
793 /*
794 * We already verified ea to be not beyond the addr limit.
795 */
796 ctx = 1 + ((ea & ~REGION_MASK) >> MAX_EA_BITS_PER_CONTEXT);
797 } else
798 ctx = (region_id - 0xc) + MAX_KERNEL_CTX_CNT;
799 return ctx;
800}
801
c60ac569
AK		 802/*
803 * This is only valid for addresses >= PAGE_OFFSET
c60ac569
AK		 804 */
805static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
806{
807 unsigned long context;
808
85beb1c4
ME		 809 if (!is_kernel_addr(ea))
810 return 0;
811
4ffe713b 812 context = get_kernel_context(ea);
c60ac569
AK		 813 return get_vsid(context, ea, ssize);
814}
5c3c7ede
DG		 815
816unsigned htab_shift_for_mem_size(unsigned long mem_size);
817
8d2169e8
DG		 818#endif /* __ASSEMBLY__ */
819
11a6f6ab 820#endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */
Linux 6.x block layer and io_uring tree(s)