License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-block.git] / arch / powerpc / include / asm / book3s / 64 / hash.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
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2#ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
3#define _ASM_POWERPC_BOOK3S_64_HASH_H
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4#ifdef __KERNEL__
5
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6/*
7 * Common bits between 4K and 64K pages in a linux-style PTE.
1ec3f937 8 * Additional bits may be defined in pgtable-hash64-*.h
e34aa03c 9 *
e34aa03c 10 */
d2cf0050 11#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
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12#define H_PAGE_F_GIX_SHIFT 56
13#define H_PAGE_BUSY _RPAGE_RSV1 /* software: PTE & hash are busy */
14#define H_PAGE_F_SECOND _RPAGE_RSV2 /* HPTE is in 2ndary HPTEG */
15#define H_PAGE_F_GIX (_RPAGE_RSV3 | _RPAGE_RSV4 | _RPAGE_RPN44)
16#define H_PAGE_HASHPTE _RPAGE_RPN43 /* PTE has associated HPTE */
e34aa03c 17
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18#ifdef CONFIG_PPC_64K_PAGES
19#include <asm/book3s/64/hash-64k.h>
20#else
21#include <asm/book3s/64/hash-4k.h>
22#endif
23
24/*
25 * Size of EA range mapped by our pagetables.
26 */
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27#define H_PGTABLE_EADDR_SIZE (H_PTE_INDEX_SIZE + H_PMD_INDEX_SIZE + \
28 H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
29#define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
371352ca 30
8ad43336 31#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_PPC_64K_PAGES)
dd1842a2 32/*
8ad43336 33 * only with hash 64k we need to use the second half of pmd page table
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34 * to store pointer to deposited pgtable_t
35 */
36#define H_PMD_CACHE_INDEX (H_PMD_INDEX_SIZE + 1)
371352ca 37#else
dd1842a2 38#define H_PMD_CACHE_INDEX H_PMD_INDEX_SIZE
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39#endif
40/*
41 * Define the address range of the kernel non-linear virtual area
42 */
d6a9996e 43#define H_KERN_VIRT_START ASM_CONST(0xD000000000000000)
21a0e8c1 44#define H_KERN_VIRT_SIZE ASM_CONST(0x0000400000000000) /* 64T */
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45
46/*
47 * The vmalloc space starts at the beginning of that region, and
48 * occupies half of it on hash CPUs and a quarter of it on Book3E
49 * (we keep a quarter for the virtual memmap)
50 */
d6a9996e 51#define H_VMALLOC_START H_KERN_VIRT_START
21a0e8c1 52#define H_VMALLOC_SIZE ASM_CONST(0x380000000000) /* 56T */
d6a9996e 53#define H_VMALLOC_END (H_VMALLOC_START + H_VMALLOC_SIZE)
371352ca 54
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55#define H_KERN_IO_START H_VMALLOC_END
56
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57/*
58 * Region IDs
59 */
60#define REGION_SHIFT 60UL
61#define REGION_MASK (0xfUL << REGION_SHIFT)
62#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
63
d6a9996e 64#define VMALLOC_REGION_ID (REGION_ID(H_VMALLOC_START))
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65#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
66#define VMEMMAP_REGION_ID (0xfUL) /* Server only */
67#define USER_REGION_ID (0UL)
68
69/*
70 * Defines the address of the vmemap area, in its own region on
71 * hash table CPUs.
72 */
d6a9996e 73#define H_VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
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74
75#ifdef CONFIG_PPC_MM_SLICES
76#define HAVE_ARCH_UNMAPPED_AREA
77#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
78#endif /* CONFIG_PPC_MM_SLICES */
8d1cf34e 79
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80
81/* PTEIDX nibble */
82#define _PTEIDX_SECONDARY 0x8
83#define _PTEIDX_GROUP_IX 0x7
84
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85#define H_PMD_BAD_BITS (PTE_TABLE_SIZE-1)
86#define H_PUD_BAD_BITS (PMD_TABLE_SIZE-1)
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87
88#ifndef __ASSEMBLY__
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89#define hash__pmd_bad(pmd) (pmd_val(pmd) & H_PMD_BAD_BITS)
90#define hash__pud_bad(pud) (pud_val(pud) & H_PUD_BAD_BITS)
91static inline int hash__pgd_bad(pgd_t pgd)
92{
93 return (pgd_val(pgd) == 0);
94}
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95#ifdef CONFIG_STRICT_KERNEL_RWX
96extern void hash__mark_rodata_ro(void);
029d9252 97extern void hash__mark_initmem_nx(void);
cd65d697 98#endif
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99
100extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
101 pte_t *ptep, unsigned long pte, int huge);
c6a3c495 102extern unsigned long htab_convert_pte_flags(unsigned long pteflags);
371352ca 103/* Atomic PTE updates */
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104static inline unsigned long hash__pte_update(struct mm_struct *mm,
105 unsigned long addr,
106 pte_t *ptep, unsigned long clr,
107 unsigned long set,
108 int huge)
371352ca 109{
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110 __be64 old_be, tmp_be;
111 unsigned long old;
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112
113 __asm__ __volatile__(
114 "1: ldarx %0,0,%3 # pte_update\n\
5dc1ef85 115 and. %1,%0,%6\n\
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116 bne- 1b \n\
117 andc %1,%0,%4 \n\
118 or %1,%1,%7\n\
119 stdcx. %1,0,%3 \n\
120 bne- 1b"
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121 : "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
122 : "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep),
945537df 123 "r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set))
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124 : "cc" );
125 /* huge pages use the old page table lock */
126 if (!huge)
127 assert_pte_locked(mm, addr);
128
5dc1ef85 129 old = be64_to_cpu(old_be);
945537df 130 if (old & H_PAGE_HASHPTE)
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131 hpte_need_flush(mm, addr, ptep, old, huge);
132
133 return old;
134}
135
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136/* Set the dirty and/or accessed bits atomically in a linux PTE, this
137 * function doesn't need to flush the hash entry
138 */
ac94ac79 139static inline void hash__ptep_set_access_flags(pte_t *ptep, pte_t entry)
371352ca 140{
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141 __be64 old, tmp, val, mask;
142
c7d54842 143 mask = cpu_to_be64(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_READ | _PAGE_WRITE |
5dc1ef85 144 _PAGE_EXEC | _PAGE_SOFT_DIRTY);
371352ca 145
5dc1ef85 146 val = pte_raw(entry) & mask;
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147
148 __asm__ __volatile__(
149 "1: ldarx %0,0,%4\n\
5dc1ef85 150 and. %1,%0,%6\n\
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151 bne- 1b \n\
152 or %0,%3,%0\n\
153 stdcx. %0,0,%4\n\
154 bne- 1b"
155 :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
945537df 156 :"r" (val), "r" (ptep), "m" (*ptep), "r" (cpu_to_be64(H_PAGE_BUSY))
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157 :"cc");
158}
159
ac94ac79 160static inline int hash__pte_same(pte_t pte_a, pte_t pte_b)
368ced78 161{
ac94ac79 162 return (((pte_raw(pte_a) ^ pte_raw(pte_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
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163}
164
ac94ac79 165static inline int hash__pte_none(pte_t pte)
ee3caed3 166{
ac94ac79 167 return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0;
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168}
169
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170/* This low level function performs the actual PTE insertion
171 * Setting the PTE depends on the MMU type and other factors. It's
172 * an horrible mess that I'm not going to try to clean up now but
173 * I'm keeping it in one place rather than spread around
174 */
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175static inline void hash__set_pte_at(struct mm_struct *mm, unsigned long addr,
176 pte_t *ptep, pte_t pte, int percpu)
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177{
178 /*
179 * Anything else just stores the PTE normally. That covers all 64-bit
180 * cases, and 32-bit non-hash with 32-bit PTEs.
181 */
182 *ptep = pte;
183}
184
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185#ifdef CONFIG_TRANSPARENT_HUGEPAGE
186extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
187 pmd_t *pmdp, unsigned long old_pmd);
188#else
189static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
190 unsigned long addr, pmd_t *pmdp,
191 unsigned long old_pmd)
192{
193 WARN(1, "%s called with THP disabled\n", __func__);
194}
195#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
196
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197
198extern int hash__map_kernel_page(unsigned long ea, unsigned long pa,
199 unsigned long flags);
200extern int __meminit hash__vmemmap_create_mapping(unsigned long start,
201 unsigned long page_size,
202 unsigned long phys);
203extern void hash__vmemmap_remove_mapping(unsigned long start,
204 unsigned long page_size);
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205
206int hash__create_section_mapping(unsigned long start, unsigned long end);
207int hash__remove_section_mapping(unsigned long start, unsigned long end);
208
371352ca 209#endif /* !__ASSEMBLY__ */
c605782b 210#endif /* __KERNEL__ */
26b6a3d9 211#endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */