Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
ab537dca AK |
2 | #ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H |
3 | #define _ASM_POWERPC_BOOK3S_64_HASH_64K_H | |
4 | ||
eea86aa4 ME |
5 | #define H_PTE_INDEX_SIZE 8 // size: 8B << 8 = 2KB, maps 2^8 x 64KB = 16MB |
6 | #define H_PMD_INDEX_SIZE 10 // size: 8B << 10 = 8KB, maps 2^10 x 16MB = 16GB | |
7 | #define H_PUD_INDEX_SIZE 10 // size: 8B << 10 = 8KB, maps 2^10 x 16GB = 16TB | |
8 | #define H_PGD_INDEX_SIZE 8 // size: 8B << 8 = 2KB, maps 2^8 x 16TB = 4PB | |
9 | ||
ab537dca | 10 | |
f384796c AK |
11 | /* |
12 | * Each context is 512TB size. SLB miss for first context/default context | |
13 | * is handled in the hotpath. | |
14 | */ | |
15 | #define MAX_EA_BITS_PER_CONTEXT 49 | |
16 | ||
f5bd0fdc AK |
17 | /* |
18 | * 64k aligned address free up few of the lower bits of RPN for us | |
19 | * We steal that here. For more deatils look at pte_pfn/pfn_pte() | |
20 | */ | |
32789d38 AK |
21 | #define H_PAGE_COMBO _RPAGE_RPN0 /* this is a combo 4k page */ |
22 | #define H_PAGE_4K_PFN _RPAGE_RPN1 /* PFN is for a single 4k page */ | |
bf9a95f9 | 23 | #define H_PAGE_BUSY _RPAGE_RPN44 /* software: PTE & hash are busy */ |
273b4936 | 24 | #define H_PAGE_HASHPTE _RPAGE_RPN43 /* PTE has associated HPTE */ |
9d2edb18 | 25 | |
1a2f7789 AK |
26 | /* memory key bits. */ |
27 | #define H_PTE_PKEY_BIT0 _RPAGE_RSV1 | |
28 | #define H_PTE_PKEY_BIT1 _RPAGE_RSV2 | |
29 | #define H_PTE_PKEY_BIT2 _RPAGE_RSV3 | |
30 | #define H_PTE_PKEY_BIT3 _RPAGE_RSV4 | |
31 | #define H_PTE_PKEY_BIT4 _RPAGE_RSV5 | |
32 | ||
bf680d51 | 33 | /* |
945537df AK |
34 | * We need to differentiate between explicit huge page and THP huge |
35 | * page, since THP huge page also need to track real subpage details | |
16c2d476 | 36 | */ |
945537df AK |
37 | #define H_PAGE_THP_HUGE H_PAGE_4K_PFN |
38 | ||
3c726f8d | 39 | /* PTE flags to conserve for HPTE identification */ |
bf9a95f9 | 40 | #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | H_PAGE_COMBO) |
62607bc6 AK |
41 | /* |
42 | * We use a 2K PTE page fragment and another 2K for storing | |
43 | * real_pte_t hash index | |
fb4e5dbd AK |
44 | * 8 bytes per each pte entry and another 8 bytes for storing |
45 | * slot details. | |
62607bc6 | 46 | */ |
fb4e5dbd AK |
47 | #define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3 + 1) |
48 | #define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT) | |
62607bc6 | 49 | |
8a6c697b AK |
50 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE) |
51 | #define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3 + 1) | |
52 | #else | |
53 | #define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3) | |
54 | #endif | |
55 | #define H_PMD_FRAG_NR (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT) | |
56 | ||
c605782b | 57 | #ifndef __ASSEMBLY__ |
96270b1f | 58 | #include <asm/errno.h> |
3c726f8d | 59 | |
c605782b BH |
60 | /* |
61 | * With 64K pages on hash table, we have a special PTE format that | |
62 | * uses a second "half" of the page table to encode sub-page information | |
63 | * in order to deal with 64K made of 4K HW pages. Thus we override the | |
64 | * generic accessors and iterators here | |
65 | */ | |
85c1fafd | 66 | #define __real_pte __real_pte |
ff31e105 | 67 | static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset) |
85c1fafd AK |
68 | { |
69 | real_pte_t rpte; | |
506b863c | 70 | unsigned long *hidxp; |
85c1fafd AK |
71 | |
72 | rpte.pte = pte; | |
bf9a95f9 RP |
73 | |
74 | /* | |
75 | * Ensure that we do not read the hidx before we read the PTE. Because | |
76 | * the writer side is expected to finish writing the hidx first followed | |
77 | * by the PTE, by using smp_wmb(). pte_set_hash_slot() ensures that. | |
78 | */ | |
79 | smp_rmb(); | |
80 | ||
ff31e105 | 81 | hidxp = (unsigned long *)(ptep + offset); |
bf9a95f9 | 82 | rpte.hidx = *hidxp; |
85c1fafd AK |
83 | return rpte; |
84 | } | |
85 | ||
7b84947c RP |
86 | /* |
87 | * shift the hidx representation by one-modulo-0xf; i.e hidx 0 is respresented | |
88 | * as 1, 1 as 2,... , and 0xf as 0. This convention lets us represent a | |
89 | * invalid hidx 0xf with a 0x0 bit value. PTEs are anyway zero'd when | |
90 | * allocated. We dont have to zero them gain; thus save on the initialization. | |
91 | */ | |
92 | #define HIDX_UNSHIFT_BY_ONE(x) ((x + 0xfUL) & 0xfUL) /* shift backward by one */ | |
93 | #define HIDX_SHIFT_BY_ONE(x) ((x + 0x1UL) & 0xfUL) /* shift forward by one */ | |
59aa31fd | 94 | #define HIDX_BITS(x, index) (x << (index << 2)) |
bf9a95f9 | 95 | #define BITS_TO_HIDX(x, index) ((x >> (index << 2)) & 0xfUL) |
7b84947c | 96 | #define INVALID_RPTE_HIDX 0x0UL |
59aa31fd | 97 | |
85c1fafd AK |
98 | static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index) |
99 | { | |
7b84947c | 100 | return HIDX_UNSHIFT_BY_ONE(BITS_TO_HIDX(rpte.hidx, index)); |
85c1fafd AK |
101 | } |
102 | ||
59aa31fd RP |
103 | /* |
104 | * Commit the hidx and return PTE bits that needs to be modified. The caller is | |
105 | * expected to modify the PTE bits accordingly and commit the PTE to memory. | |
106 | */ | |
107 | static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte, | |
ff31e105 AK |
108 | unsigned int subpg_index, |
109 | unsigned long hidx, int offset) | |
59aa31fd | 110 | { |
ff31e105 | 111 | unsigned long *hidxp = (unsigned long *)(ptep + offset); |
59aa31fd RP |
112 | |
113 | rpte.hidx &= ~HIDX_BITS(0xfUL, subpg_index); | |
7b84947c | 114 | *hidxp = rpte.hidx | HIDX_BITS(HIDX_SHIFT_BY_ONE(hidx), subpg_index); |
59aa31fd RP |
115 | |
116 | /* | |
117 | * Anyone reading PTE must ensure hidx bits are read after reading the | |
118 | * PTE by using the read-side barrier smp_rmb(). __real_pte() can be | |
119 | * used for that. | |
120 | */ | |
121 | smp_wmb(); | |
122 | ||
123 | /* No PTE bits to be modified, return 0x0UL */ | |
124 | return 0x0UL; | |
85c1fafd AK |
125 | } |
126 | ||
3c726f8d | 127 | #define __rpte_to_pte(r) ((r).pte) |
bf680d51 | 128 | extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index); |
ab537dca AK |
129 | /* |
130 | * Trick: we set __end to va + 64k, which happens works for | |
3c726f8d BH |
131 | * a 16M page as well as we want only one iteration |
132 | */ | |
5524a27d AK |
133 | #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \ |
134 | do { \ | |
135 | unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \ | |
136 | unsigned __split = (psize == MMU_PAGE_4K || \ | |
137 | psize == MMU_PAGE_64K_AP); \ | |
138 | shift = mmu_psize_defs[psize].shift; \ | |
139 | for (index = 0; vpn < __end; index++, \ | |
140 | vpn += (1L << (shift - VPN_SHIFT))) { \ | |
f405b510 | 141 | if (!__split || __rpte_sub_valid(rpte, index)) |
3c726f8d | 142 | |
f405b510 | 143 | #define pte_iterate_hashed_end() } } while(0) |
3c726f8d | 144 | |
16c2d476 | 145 | #define pte_pagesize_index(mm, addr, pte) \ |
945537df | 146 | (((pte) & H_PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K) |
3c726f8d | 147 | |
96270b1f AK |
148 | extern int remap_pfn_range(struct vm_area_struct *, unsigned long addr, |
149 | unsigned long pfn, unsigned long size, pgprot_t); | |
6cc1a0ee AK |
150 | static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long addr, |
151 | unsigned long pfn, pgprot_t prot) | |
96270b1f AK |
152 | { |
153 | if (pfn > (PTE_RPN_MASK >> PAGE_SHIFT)) { | |
154 | WARN(1, "remap_4k_pfn called with wrong pfn value\n"); | |
155 | return -EINVAL; | |
156 | } | |
157 | return remap_pfn_range(vma, addr, pfn, PAGE_SIZE, | |
945537df | 158 | __pgprot(pgprot_val(prot) | H_PAGE_4K_PFN)); |
96270b1f | 159 | } |
721151d0 | 160 | |
dd1842a2 | 161 | #define H_PTE_TABLE_SIZE PTE_FRAG_SIZE |
4a7aa4fe | 162 | #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE) |
dd1842a2 AK |
163 | #define H_PMD_TABLE_SIZE ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \ |
164 | (sizeof(unsigned long) << PMD_INDEX_SIZE)) | |
62607bc6 | 165 | #else |
dd1842a2 | 166 | #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) |
62607bc6 | 167 | #endif |
fae22116 AK |
168 | #ifdef CONFIG_HUGETLB_PAGE |
169 | #define H_PUD_TABLE_SIZE ((sizeof(pud_t) << PUD_INDEX_SIZE) + \ | |
170 | (sizeof(unsigned long) << PUD_INDEX_SIZE)) | |
171 | #else | |
dd1842a2 | 172 | #define H_PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) |
fae22116 | 173 | #endif |
dd1842a2 | 174 | #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) |
ab537dca | 175 | |
e34aa03c | 176 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
e34aa03c AK |
177 | static inline char *get_hpte_slot_array(pmd_t *pmdp) |
178 | { | |
179 | /* | |
180 | * The hpte hindex is stored in the pgtable whose address is in the | |
181 | * second half of the PMD | |
182 | * | |
183 | * Order this load with the test for pmd_trans_huge in the caller | |
184 | */ | |
185 | smp_rmb(); | |
186 | return *(char **)(pmdp + PTRS_PER_PMD); | |
187 | ||
188 | ||
189 | } | |
190 | /* | |
191 | * The linux hugepage PMD now include the pmd entries followed by the address | |
192 | * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits. | |
849f86a6 | 193 | * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per |
e34aa03c AK |
194 | * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and |
195 | * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t. | |
196 | * | |
849f86a6 | 197 | * The top three bits are intentionally left as zero. This memory location |
e34aa03c AK |
198 | * are also used as normal page PTE pointers. So if we have any pointers |
199 | * left around while we collapse a hugepage, we need to make sure | |
200 | * _PAGE_PRESENT bit of that is zero when we look at them | |
201 | */ | |
202 | static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index) | |
203 | { | |
849f86a6 | 204 | return hpte_slot_array[index] & 0x1; |
e34aa03c AK |
205 | } |
206 | ||
207 | static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array, | |
208 | int index) | |
209 | { | |
849f86a6 | 210 | return hpte_slot_array[index] >> 1; |
e34aa03c AK |
211 | } |
212 | ||
213 | static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array, | |
214 | unsigned int index, unsigned int hidx) | |
215 | { | |
849f86a6 | 216 | hpte_slot_array[index] = (hidx << 1) | 0x1; |
e34aa03c AK |
217 | } |
218 | ||
219 | /* | |
220 | * | |
221 | * For core kernel code by design pmd_trans_huge is never run on any hugetlbfs | |
222 | * page. The hugetlbfs page table walking and mangling paths are totally | |
223 | * separated form the core VM paths and they're differentiated by | |
224 | * VM_HUGETLB being set on vm_flags well before any pmd_trans_huge could run. | |
225 | * | |
226 | * pmd_trans_huge() is defined as false at build time if | |
227 | * CONFIG_TRANSPARENT_HUGEPAGE=n to optimize away code blocks at build | |
228 | * time in such case. | |
229 | * | |
230 | * For ppc64 we need to differntiate from explicit hugepages from THP, because | |
231 | * for THP we also track the subpage details at the pmd level. We don't do | |
232 | * that for explicit huge pages. | |
233 | * | |
234 | */ | |
6cc1a0ee | 235 | static inline int hash__pmd_trans_huge(pmd_t pmd) |
e34aa03c | 236 | { |
945537df AK |
237 | return !!((pmd_val(pmd) & (_PAGE_PTE | H_PAGE_THP_HUGE)) == |
238 | (_PAGE_PTE | H_PAGE_THP_HUGE)); | |
e34aa03c AK |
239 | } |
240 | ||
6cc1a0ee | 241 | static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b) |
e34aa03c | 242 | { |
ee3caed3 | 243 | return (((pmd_raw(pmd_a) ^ pmd_raw(pmd_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0); |
e34aa03c AK |
244 | } |
245 | ||
3df33f12 AK |
246 | static inline pmd_t hash__pmd_mkhuge(pmd_t pmd) |
247 | { | |
248 | return __pmd(pmd_val(pmd) | (_PAGE_PTE | H_PAGE_THP_HUGE)); | |
249 | } | |
250 | ||
251 | extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm, | |
252 | unsigned long addr, pmd_t *pmdp, | |
253 | unsigned long clr, unsigned long set); | |
254 | extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma, | |
255 | unsigned long address, pmd_t *pmdp); | |
256 | extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, | |
257 | pgtable_t pgtable); | |
258 | extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); | |
3df33f12 AK |
259 | extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm, |
260 | unsigned long addr, pmd_t *pmdp); | |
261 | extern int hash__has_transparent_hugepage(void); | |
e34aa03c | 262 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
c605782b | 263 | #endif /* __ASSEMBLY__ */ |
ab537dca AK |
264 | |
265 | #endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */ |