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Fix common misspellings
[linux-2.6-block.git] / arch / powerpc / include / asm / bitops.h
CommitLineData
a0e60b20
DG		 1/*
2 * PowerPC atomic bit operations.
3 *
4 * Merged version by David Gibson <david@gibson.dropbear.id.au>.
5 * Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
6 * Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
7 * originally took it from the ppc32 code.
8 *
9 * Within a word, bits are numbered LSB first. Lot's of places make
10 * this assumption by directly testing bits with (val & (1<<nr)).
11 * This can cause confusion for large (> 1 word) bitmaps on a
12 * big-endian system because, unlike little endian, the number of each
13 * bit depends on the word size.
14 *
15 * The bitop functions are defined to work on unsigned longs, so for a
16 * ppc64 system the bits end up numbered:
17 * |63..............0|127............64|191...........128|255...........196|
18 * and on ppc32:
19 * |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
20 *
21 * There are a few little-endian macros used mostly for filesystem
22 * bitmaps, these work on similar bit arrays layouts, but
23 * byte-oriented:
24 * |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
25 *
26 * The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
27 * number field needs to be reversed compared to the big-endian bit
28 * fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
29 *
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License
32 * as published by the Free Software Foundation; either version
33 * 2 of the License, or (at your option) any later version.
34 */
35
36#ifndef _ASM_POWERPC_BITOPS_H
37#define _ASM_POWERPC_BITOPS_H
38
39#ifdef __KERNEL__
40
0624517d
JS		 41#ifndef _LINUX_BITOPS_H
42#error only <linux/bitops.h> can be included directly
43#endif
44
a0e60b20 45#include <linux/compiler.h>
3ddfbcf1 46#include <asm/asm-compat.h>
a0e60b20
DG		 47#include <asm/synch.h>
48
49/*
50 * clear_bit doesn't imply a memory barrier
51 */
52#define smp_mb__before_clear_bit() smp_mb()
53#define smp_mb__after_clear_bit() smp_mb()
54
55#define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
56#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
57#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
58
0d2d3e38
GT		 59/* Macro for generating the ***_bits() functions */
60#define DEFINE_BITOP(fn, op, prefix, postfix) \
61static __inline__ void fn(unsigned long mask, \
62 volatile unsigned long *_p) \
63{ \
64 unsigned long old; \
65 unsigned long *p = (unsigned long *)_p; \
66 __asm__ __volatile__ ( \
67 prefix \
864b9e6f 68"1:" PPC_LLARX(%0,0,%3,0) "\n" \
0d2d3e38
GT		 69 stringify_in_c(op) "%0,%0,%2\n" \
70 PPC405_ERR77(0,%3) \
71 PPC_STLCX "%0,0,%3\n" \
72 "bne- 1b\n" \
73 postfix \
74 : "=&r" (old), "+m" (*p) \
75 : "r" (mask), "r" (p) \
76 : "cc", "memory"); \
77}
78
79DEFINE_BITOP(set_bits, or, "", "")
80DEFINE_BITOP(clear_bits, andc, "", "")
f10e2e5b 81DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER, "")
0d2d3e38
GT		 82DEFINE_BITOP(change_bits, xor, "", "")
83
a0e60b20
DG		 84static __inline__ void set_bit(int nr, volatile unsigned long *addr)
85{
0d2d3e38 86 set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
a0e60b20
DG		 87}
88
89static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
90{
0d2d3e38 91 clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
a0e60b20
DG		 92}
93
66ffb04c
NP		 94static __inline__ void clear_bit_unlock(int nr, volatile unsigned long *addr)
95{
0d2d3e38 96 clear_bits_unlock(BITOP_MASK(nr), addr + BITOP_WORD(nr));
66ffb04c
NP		 97}
98
a0e60b20
DG		 99static __inline__ void change_bit(int nr, volatile unsigned long *addr)
100{
0d2d3e38
GT		 101 change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr));
102}
a0e60b20 103
0d2d3e38
GT		 104/* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
105 * operands. */
864b9e6f
AB		 106#define DEFINE_TESTOP(fn, op, prefix, postfix, eh) \
107static __inline__ unsigned long fn( \
108 unsigned long mask, \
109 volatile unsigned long *_p) \
110{ \
111 unsigned long old, t; \
112 unsigned long *p = (unsigned long *)_p; \
113 __asm__ __volatile__ ( \
114 prefix \
115"1:" PPC_LLARX(%0,0,%3,eh) "\n" \
116 stringify_in_c(op) "%1,%0,%2\n" \
117 PPC405_ERR77(0,%3) \
118 PPC_STLCX "%1,0,%3\n" \
119 "bne- 1b\n" \
120 postfix \
121 : "=&r" (old), "=&r" (t) \
122 : "r" (mask), "r" (p) \
123 : "cc", "memory"); \
124 return (old & mask); \
a0e60b20
DG		 125}
126
f10e2e5b
AB		 127DEFINE_TESTOP(test_and_set_bits, or, PPC_RELEASE_BARRIER,
128 PPC_ACQUIRE_BARRIER, 0)
129DEFINE_TESTOP(test_and_set_bits_lock, or, "",
130 PPC_ACQUIRE_BARRIER, 1)
131DEFINE_TESTOP(test_and_clear_bits, andc, PPC_RELEASE_BARRIER,
132 PPC_ACQUIRE_BARRIER, 0)
133DEFINE_TESTOP(test_and_change_bits, xor, PPC_RELEASE_BARRIER,
134 PPC_ACQUIRE_BARRIER, 0)
0d2d3e38 135
a0e60b20
DG		 136static __inline__ int test_and_set_bit(unsigned long nr,
137 volatile unsigned long *addr)
138{
0d2d3e38 139 return test_and_set_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
a0e60b20
DG		 140}
141
66ffb04c
NP		 142static __inline__ int test_and_set_bit_lock(unsigned long nr,
143 volatile unsigned long *addr)
144{
0d2d3e38
GT		 145 return test_and_set_bits_lock(BITOP_MASK(nr),
146 addr + BITOP_WORD(nr)) != 0;
66ffb04c
NP		 147}
148
a0e60b20
DG		 149static __inline__ int test_and_clear_bit(unsigned long nr,
150 volatile unsigned long *addr)
151{
0d2d3e38 152 return test_and_clear_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
a0e60b20
DG		 153}
154
155static __inline__ int test_and_change_bit(unsigned long nr,
156 volatile unsigned long *addr)
157{
0d2d3e38 158 return test_and_change_bits(BITOP_MASK(nr), addr + BITOP_WORD(nr)) != 0;
a0e60b20
DG		 159}
160
e779b2f9 161#include <asm-generic/bitops/non-atomic.h>
a0e60b20 162
66ffb04c
NP		 163static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
164{
f10e2e5b 165 __asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
66ffb04c
NP		 166 __clear_bit(nr, addr);
167}
168
a0e60b20
DG		 169/*
170 * Return the zero-based bit position (LE, not IBM bit numbering) of
171 * the most significant 1-bit in a double word.
172 */
ef55d53c
DH		 173static __inline__ __attribute__((const))
174int __ilog2(unsigned long x)
a0e60b20
DG		 175{
176 int lz;
177
3ddfbcf1 178 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
a0e60b20
DG		 179 return BITS_PER_LONG - 1 - lz;
180}
181
ef55d53c
DH		 182static inline __attribute__((const))
183int __ilog2_u32(u32 n)
184{
185 int bit;
186 asm ("cntlzw %0,%1" : "=r" (bit) : "r" (n));
187 return 31 - bit;
188}
189
190#ifdef __powerpc64__
191static inline __attribute__((const))
02241696 192int __ilog2_u64(u64 n)
ef55d53c
DH		 193{
194 int bit;
195 asm ("cntlzd %0,%1" : "=r" (bit) : "r" (n));
196 return 63 - bit;
197}
198#endif
199
a0e60b20
DG		 200/*
201 * Determines the bit position of the least significant 0 bit in the
202 * specified double word. The returned bit position will be
203 * zero-based, starting from the right side (63/31 - 0).
204 */
205static __inline__ unsigned long ffz(unsigned long x)
206{
207 /* no zero exists anywhere in the 8 byte area. */
208 if ((x = ~x) == 0)
209 return BITS_PER_LONG;
210
211 /*
25985edc
LDM		 212 * Calculate the bit position of the least significant '1' bit in x
213 * (since x has been changed this will actually be the least significant
a0e60b20
DG		 214 * '0' bit in * the original x). Note: (x & -x) gives us a mask that
215 * is the least significant * (RIGHT-most) 1-bit of the value in x.
216 */
217 return __ilog2(x & -x);
218}
219
220static __inline__ int __ffs(unsigned long x)
221{
222 return __ilog2(x & -x);
223}
224
225/*
226 * ffs: find first bit set. This is defined the same way as
227 * the libc and compiler builtin ffs routines, therefore
228 * differs in spirit from the above ffz (man ffs).
229 */
230static __inline__ int ffs(int x)
231{
232 unsigned long i = (unsigned long)x;
233 return __ilog2(i & -i) + 1;
234}
235
236/*
237 * fls: find last (most-significant) bit set.
238 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
239 */
240static __inline__ int fls(unsigned int x)
241{
242 int lz;
243
244 asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
245 return 32 - lz;
246}
9f264be6 247
56a6b1eb
AH		 248static __inline__ unsigned long __fls(unsigned long x)
249{
250 return __ilog2(x);
251}
252
9f264be6
PM		 253/*
254 * 64-bit can do this using one cntlzd (count leading zeroes doubleword)
255 * instruction; for 32-bit we use the generic version, which does two
256 * 32-bit fls calls.
257 */
258#ifdef __powerpc64__
259static __inline__ int fls64(__u64 x)
260{
261 int lz;
262
263 asm ("cntlzd %0,%1" : "=r" (lz) : "r" (x));
264 return 64 - lz;
265}
266#else
e779b2f9 267#include <asm-generic/bitops/fls64.h>
9f264be6
PM		 268#endif /* __powerpc64__ */
269
64ff3128
AB		 270#ifdef CONFIG_PPC64
271unsigned int __arch_hweight8(unsigned int w);
272unsigned int __arch_hweight16(unsigned int w);
273unsigned int __arch_hweight32(unsigned int w);
274unsigned long __arch_hweight64(__u64 w);
275#include <asm-generic/bitops/const_hweight.h>
276#else
e779b2f9 277#include <asm-generic/bitops/hweight.h>
64ff3128
AB		 278#endif
279
47b9d9bd 280#include <asm-generic/bitops/find.h>
a0e60b20
DG		 281
282/* Little-endian versions */
283
f57d7ff1
AM		 284static __inline__ int test_bit_le(unsigned long nr,
285 __const__ void *addr)
a0e60b20
DG		 286{
287 __const__ unsigned char *tmp = (__const__ unsigned char *) addr;
288 return (tmp[nr >> 3] >> (nr & 7)) & 1;
289}
290
f57d7ff1
AM		 291static inline void __set_bit_le(int nr, void *addr)
292{
293 __set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
294}
295
296static inline void __clear_bit_le(int nr, void *addr)
297{
298 __clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
299}
a0e60b20 300
f57d7ff1
AM		 301static inline int test_and_set_bit_le(int nr, void *addr)
302{
303 return test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
304}
a0e60b20 305
f57d7ff1
AM		 306static inline int test_and_clear_bit_le(int nr, void *addr)
307{
308 return test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
309}
310
311static inline int __test_and_set_bit_le(int nr, void *addr)
312{
313 return __test_and_set_bit(nr ^ BITOP_LE_SWIZZLE, addr);
314}
315
316static inline int __test_and_clear_bit_le(int nr, void *addr)
317{
318 return __test_and_clear_bit(nr ^ BITOP_LE_SWIZZLE, addr);
319}
a0e60b20 320
c4945b9e
AM		 321#define find_first_zero_bit_le(addr, size) \
322 find_next_zero_bit_le((addr), (size), 0)
a56560b3 323unsigned long find_next_zero_bit_le(const void *addr,
a0e60b20
DG		 324 unsigned long size, unsigned long offset);
325
a56560b3 326unsigned long find_next_bit_le(const void *addr,
aa02ad67 327 unsigned long size, unsigned long offset);
a0e60b20
DG		 328/* Bitmap functions for the ext2 filesystem */
329
a0e60b20 330#define ext2_set_bit_atomic(lock, nr, addr) \
f57d7ff1 331 test_and_set_bit_le((nr), (unsigned long*)addr)
a0e60b20 332#define ext2_clear_bit_atomic(lock, nr, addr) \
f57d7ff1 333 test_and_clear_bit_le((nr), (unsigned long*)addr)
a0e60b20 334
e779b2f9 335#include <asm-generic/bitops/sched.h>
a0e60b20
DG		 336
337#endif /* __KERNEL__ */
338
339#endif /* _ASM_POWERPC_BITOPS_H */
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