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317bf653 NC |
1 | /* |
2 | * Copyright (C) 2008 Extreme Engineering Solutions, Inc. | |
3 | * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. | |
4 | * | |
5 | * XPedite5301 PMC/XMC module based on MPC8572E | |
6 | * | |
7 | * This is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
13 | / { | |
14 | model = "xes,xpedite5301"; | |
15 | compatible = "xes,xpedite5301", "xes,MPC8572"; | |
16 | #address-cells = <2>; | |
17 | #size-cells = <2>; | |
18 | form-factor = "PMC/XMC"; | |
19 | boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */ | |
20 | ||
21 | aliases { | |
22 | ethernet0 = &enet0; | |
23 | ethernet1 = &enet1; | |
24 | serial0 = &serial0; | |
25 | serial1 = &serial1; | |
26 | pci1 = &pci1; | |
27 | pci2 = &pci2; | |
28 | }; | |
29 | ||
30 | cpus { | |
31 | #address-cells = <1>; | |
32 | #size-cells = <0>; | |
33 | ||
34 | PowerPC,8572@0 { | |
35 | device_type = "cpu"; | |
36 | reg = <0x0>; | |
37 | d-cache-line-size = <32>; // 32 bytes | |
38 | i-cache-line-size = <32>; // 32 bytes | |
39 | d-cache-size = <0x8000>; // L1, 32K | |
40 | i-cache-size = <0x8000>; // L1, 32K | |
41 | timebase-frequency = <0>; | |
42 | bus-frequency = <0>; | |
43 | clock-frequency = <0>; | |
44 | next-level-cache = <&L2>; | |
45 | }; | |
46 | ||
47 | PowerPC,8572@1 { | |
48 | device_type = "cpu"; | |
49 | reg = <0x1>; | |
50 | d-cache-line-size = <32>; // 32 bytes | |
51 | i-cache-line-size = <32>; // 32 bytes | |
52 | d-cache-size = <0x8000>; // L1, 32K | |
53 | i-cache-size = <0x8000>; // L1, 32K | |
54 | timebase-frequency = <0>; | |
55 | bus-frequency = <0>; | |
56 | clock-frequency = <0>; | |
57 | next-level-cache = <&L2>; | |
58 | }; | |
59 | }; | |
60 | ||
61 | memory { | |
62 | device_type = "memory"; | |
63 | reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot | |
64 | }; | |
65 | ||
66 | localbus@ef005000 { | |
67 | #address-cells = <2>; | |
68 | #size-cells = <1>; | |
69 | compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; | |
70 | reg = <0 0xef005000 0 0x1000>; | |
71 | interrupts = <19 2>; | |
72 | interrupt-parent = <&mpic>; | |
73 | /* Local bus region mappings */ | |
74 | ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ | |
75 | 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ | |
76 | 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ | |
77 | 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ | |
78 | ||
79 | nor-boot@0,0 { | |
80 | compatible = "amd,s29gl01gp", "cfi-flash"; | |
81 | bank-width = <2>; | |
82 | reg = <0 0 0x8000000>; /* 128MB */ | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | partition@0 { | |
86 | label = "Primary user space"; | |
87 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | |
88 | }; | |
89 | partition@6f00000 { | |
90 | label = "Primary kernel"; | |
91 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | |
92 | }; | |
93 | partition@7f00000 { | |
94 | label = "Primary DTB"; | |
95 | reg = <0x7f00000 0x40000>; /* 256 KB */ | |
96 | }; | |
97 | partition@7f40000 { | |
98 | label = "Primary U-Boot environment"; | |
99 | reg = <0x7f40000 0x40000>; /* 256 KB */ | |
100 | }; | |
101 | partition@7f80000 { | |
102 | label = "Primary U-Boot"; | |
103 | reg = <0x7f80000 0x80000>; /* 512 KB */ | |
104 | read-only; | |
105 | }; | |
106 | }; | |
107 | ||
108 | nor-alternate@1,0 { | |
109 | compatible = "amd,s29gl01gp", "cfi-flash"; | |
110 | bank-width = <2>; | |
111 | //reg = <0xf0000000 0x08000000>; /* 128MB */ | |
112 | reg = <1 0 0x8000000>; /* 128MB */ | |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | partition@0 { | |
116 | label = "Secondary user space"; | |
117 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | |
118 | }; | |
119 | partition@6f00000 { | |
120 | label = "Secondary kernel"; | |
121 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | |
122 | }; | |
123 | partition@7f00000 { | |
124 | label = "Secondary DTB"; | |
125 | reg = <0x7f00000 0x40000>; /* 256 KB */ | |
126 | }; | |
127 | partition@7f40000 { | |
128 | label = "Secondary U-Boot environment"; | |
129 | reg = <0x7f40000 0x40000>; /* 256 KB */ | |
130 | }; | |
131 | partition@7f80000 { | |
132 | label = "Secondary U-Boot"; | |
133 | reg = <0x7f80000 0x80000>; /* 512 KB */ | |
134 | read-only; | |
135 | }; | |
136 | }; | |
137 | ||
138 | nand@2,0 { | |
139 | #address-cells = <1>; | |
140 | #size-cells = <1>; | |
141 | /* | |
142 | * Actual part could be ST Micro NAND08GW3B2A (1 GB), | |
143 | * Micron MT29F8G08DAA (2x 512 MB), or Micron | |
144 | * MT29F16G08FAA (2x 1 GB), depending on the build | |
145 | * configuration | |
146 | */ | |
147 | compatible = "fsl,mpc8572-fcm-nand", | |
148 | "fsl,elbc-fcm-nand"; | |
149 | reg = <2 0 0x40000>; | |
150 | /* U-Boot should fix this up if chip size > 1 GB */ | |
151 | partition@0 { | |
152 | label = "NAND Filesystem"; | |
153 | reg = <0 0x40000000>; | |
154 | }; | |
155 | }; | |
156 | ||
157 | }; | |
158 | ||
159 | soc8572@ef000000 { | |
160 | #address-cells = <1>; | |
161 | #size-cells = <1>; | |
162 | device_type = "soc"; | |
163 | compatible = "fsl,mpc8572-immr", "simple-bus"; | |
164 | ranges = <0x0 0 0xef000000 0x100000>; | |
165 | bus-frequency = <0>; // Filled out by uboot. | |
166 | ||
167 | ecm-law@0 { | |
168 | compatible = "fsl,ecm-law"; | |
169 | reg = <0x0 0x1000>; | |
170 | fsl,num-laws = <12>; | |
171 | }; | |
172 | ||
173 | ecm@1000 { | |
174 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | |
175 | reg = <0x1000 0x1000>; | |
176 | interrupts = <17 2>; | |
177 | interrupt-parent = <&mpic>; | |
178 | }; | |
179 | ||
180 | memory-controller@2000 { | |
181 | compatible = "fsl,mpc8572-memory-controller"; | |
182 | reg = <0x2000 0x1000>; | |
183 | interrupt-parent = <&mpic>; | |
184 | interrupts = <18 2>; | |
185 | }; | |
186 | ||
187 | memory-controller@6000 { | |
188 | compatible = "fsl,mpc8572-memory-controller"; | |
189 | reg = <0x6000 0x1000>; | |
190 | interrupt-parent = <&mpic>; | |
191 | interrupts = <18 2>; | |
192 | }; | |
193 | ||
194 | L2: l2-cache-controller@20000 { | |
195 | compatible = "fsl,mpc8572-l2-cache-controller"; | |
196 | reg = <0x20000 0x1000>; | |
197 | cache-line-size = <32>; // 32 bytes | |
198 | cache-size = <0x100000>; // L2, 1M | |
199 | interrupt-parent = <&mpic>; | |
200 | interrupts = <16 2>; | |
201 | }; | |
202 | ||
203 | i2c@3000 { | |
204 | #address-cells = <1>; | |
205 | #size-cells = <0>; | |
206 | cell-index = <0>; | |
207 | compatible = "fsl-i2c"; | |
208 | reg = <0x3000 0x100>; | |
209 | interrupts = <43 2>; | |
210 | interrupt-parent = <&mpic>; | |
211 | dfsrr; | |
212 | ||
213 | temp-sensor@48 { | |
214 | compatible = "dallas,ds1631", "dallas,ds1621"; | |
215 | reg = <0x48>; | |
216 | }; | |
217 | ||
218 | temp-sensor@4c { | |
219 | compatible = "adi,adt7461"; | |
220 | reg = <0x4c>; | |
221 | }; | |
222 | ||
223 | cpu-supervisor@51 { | |
224 | compatible = "dallas,ds4510"; | |
225 | reg = <0x51>; | |
226 | }; | |
227 | ||
228 | eeprom@54 { | |
229 | compatible = "atmel,at24c128b"; | |
230 | reg = <0x54>; | |
231 | }; | |
232 | ||
233 | rtc@68 { | |
234 | compatible = "stm,m41t00", | |
235 | "dallas,ds1338"; | |
236 | reg = <0x68>; | |
237 | }; | |
238 | ||
239 | pcie-switch@70 { | |
240 | compatible = "plx,pex8518"; | |
241 | reg = <0x70>; | |
242 | }; | |
243 | ||
244 | gpio1: gpio@18 { | |
245 | compatible = "nxp,pca9557"; | |
246 | reg = <0x18>; | |
247 | #gpio-cells = <2>; | |
248 | gpio-controller; | |
249 | polarity = <0x00>; | |
250 | }; | |
251 | ||
252 | gpio2: gpio@1c { | |
253 | compatible = "nxp,pca9557"; | |
254 | reg = <0x1c>; | |
255 | #gpio-cells = <2>; | |
256 | gpio-controller; | |
257 | polarity = <0x00>; | |
258 | }; | |
259 | ||
260 | gpio3: gpio@1e { | |
261 | compatible = "nxp,pca9557"; | |
262 | reg = <0x1e>; | |
263 | #gpio-cells = <2>; | |
264 | gpio-controller; | |
265 | polarity = <0x00>; | |
266 | }; | |
267 | ||
268 | gpio4: gpio@1f { | |
269 | compatible = "nxp,pca9557"; | |
270 | reg = <0x1f>; | |
271 | #gpio-cells = <2>; | |
272 | gpio-controller; | |
273 | polarity = <0x00>; | |
274 | }; | |
275 | }; | |
276 | ||
277 | i2c@3100 { | |
278 | #address-cells = <1>; | |
279 | #size-cells = <0>; | |
280 | cell-index = <1>; | |
281 | compatible = "fsl-i2c"; | |
282 | reg = <0x3100 0x100>; | |
283 | interrupts = <43 2>; | |
284 | interrupt-parent = <&mpic>; | |
285 | dfsrr; | |
286 | }; | |
287 | ||
288 | dma@c300 { | |
289 | #address-cells = <1>; | |
290 | #size-cells = <1>; | |
291 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | |
292 | reg = <0xc300 0x4>; | |
293 | ranges = <0x0 0xc100 0x200>; | |
294 | cell-index = <1>; | |
295 | dma-channel@0 { | |
296 | compatible = "fsl,mpc8572-dma-channel", | |
297 | "fsl,eloplus-dma-channel"; | |
298 | reg = <0x0 0x80>; | |
299 | cell-index = <0>; | |
300 | interrupt-parent = <&mpic>; | |
301 | interrupts = <76 2>; | |
302 | }; | |
303 | dma-channel@80 { | |
304 | compatible = "fsl,mpc8572-dma-channel", | |
305 | "fsl,eloplus-dma-channel"; | |
306 | reg = <0x80 0x80>; | |
307 | cell-index = <1>; | |
308 | interrupt-parent = <&mpic>; | |
309 | interrupts = <77 2>; | |
310 | }; | |
311 | dma-channel@100 { | |
312 | compatible = "fsl,mpc8572-dma-channel", | |
313 | "fsl,eloplus-dma-channel"; | |
314 | reg = <0x100 0x80>; | |
315 | cell-index = <2>; | |
316 | interrupt-parent = <&mpic>; | |
317 | interrupts = <78 2>; | |
318 | }; | |
319 | dma-channel@180 { | |
320 | compatible = "fsl,mpc8572-dma-channel", | |
321 | "fsl,eloplus-dma-channel"; | |
322 | reg = <0x180 0x80>; | |
323 | cell-index = <3>; | |
324 | interrupt-parent = <&mpic>; | |
325 | interrupts = <79 2>; | |
326 | }; | |
327 | }; | |
328 | ||
329 | dma@21300 { | |
330 | #address-cells = <1>; | |
331 | #size-cells = <1>; | |
332 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | |
333 | reg = <0x21300 0x4>; | |
334 | ranges = <0x0 0x21100 0x200>; | |
335 | cell-index = <0>; | |
336 | dma-channel@0 { | |
337 | compatible = "fsl,mpc8572-dma-channel", | |
338 | "fsl,eloplus-dma-channel"; | |
339 | reg = <0x0 0x80>; | |
340 | cell-index = <0>; | |
341 | interrupt-parent = <&mpic>; | |
342 | interrupts = <20 2>; | |
343 | }; | |
344 | dma-channel@80 { | |
345 | compatible = "fsl,mpc8572-dma-channel", | |
346 | "fsl,eloplus-dma-channel"; | |
347 | reg = <0x80 0x80>; | |
348 | cell-index = <1>; | |
349 | interrupt-parent = <&mpic>; | |
350 | interrupts = <21 2>; | |
351 | }; | |
352 | dma-channel@100 { | |
353 | compatible = "fsl,mpc8572-dma-channel", | |
354 | "fsl,eloplus-dma-channel"; | |
355 | reg = <0x100 0x80>; | |
356 | cell-index = <2>; | |
357 | interrupt-parent = <&mpic>; | |
358 | interrupts = <22 2>; | |
359 | }; | |
360 | dma-channel@180 { | |
361 | compatible = "fsl,mpc8572-dma-channel", | |
362 | "fsl,eloplus-dma-channel"; | |
363 | reg = <0x180 0x80>; | |
364 | cell-index = <3>; | |
365 | interrupt-parent = <&mpic>; | |
366 | interrupts = <23 2>; | |
367 | }; | |
368 | }; | |
369 | ||
370 | /* eTSEC 1 */ | |
371 | enet0: ethernet@24000 { | |
372 | #address-cells = <1>; | |
373 | #size-cells = <1>; | |
374 | cell-index = <0>; | |
375 | device_type = "network"; | |
376 | model = "eTSEC"; | |
377 | compatible = "gianfar"; | |
378 | reg = <0x24000 0x1000>; | |
379 | ranges = <0x0 0x24000 0x1000>; | |
380 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
381 | interrupts = <29 2 30 2 34 2>; | |
382 | interrupt-parent = <&mpic>; | |
383 | tbi-handle = <&tbi0>; | |
384 | phy-handle = <&phy0>; | |
385 | phy-connection-type = "sgmii"; | |
386 | ||
387 | mdio@520 { | |
388 | #address-cells = <1>; | |
389 | #size-cells = <0>; | |
390 | compatible = "fsl,gianfar-mdio"; | |
391 | reg = <0x520 0x20>; | |
392 | ||
393 | phy0: ethernet-phy@1 { | |
394 | interrupt-parent = <&mpic>; | |
395 | interrupts = <8 1>; | |
396 | reg = <0x1>; | |
397 | }; | |
398 | phy1: ethernet-phy@2 { | |
399 | interrupt-parent = <&mpic>; | |
400 | interrupts = <8 1>; | |
401 | reg = <0x2>; | |
402 | }; | |
403 | tbi0: tbi-phy@11 { | |
404 | reg = <0x11>; | |
405 | device_type = "tbi-phy"; | |
406 | }; | |
407 | }; | |
408 | }; | |
409 | ||
410 | /* eTSEC 2 */ | |
411 | enet1: ethernet@25000 { | |
412 | #address-cells = <1>; | |
413 | #size-cells = <1>; | |
414 | cell-index = <1>; | |
415 | device_type = "network"; | |
416 | model = "eTSEC"; | |
417 | compatible = "gianfar"; | |
418 | reg = <0x25000 0x1000>; | |
419 | ranges = <0x0 0x25000 0x1000>; | |
420 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
421 | interrupts = <35 2 36 2 40 2>; | |
422 | interrupt-parent = <&mpic>; | |
423 | tbi-handle = <&tbi1>; | |
424 | phy-handle = <&phy1>; | |
425 | phy-connection-type = "sgmii"; | |
426 | ||
427 | mdio@520 { | |
428 | #address-cells = <1>; | |
429 | #size-cells = <0>; | |
430 | compatible = "fsl,gianfar-tbi"; | |
431 | reg = <0x520 0x20>; | |
432 | ||
433 | tbi1: tbi-phy@11 { | |
434 | reg = <0x11>; | |
435 | device_type = "tbi-phy"; | |
436 | }; | |
437 | }; | |
438 | }; | |
439 | ||
440 | /* UART0 */ | |
441 | serial0: serial@4500 { | |
442 | cell-index = <0>; | |
443 | device_type = "serial"; | |
f706bed1 | 444 | compatible = "fsl,ns16550", "ns16550"; |
317bf653 NC |
445 | reg = <0x4500 0x100>; |
446 | clock-frequency = <0>; | |
447 | interrupts = <42 2>; | |
448 | interrupt-parent = <&mpic>; | |
449 | }; | |
450 | ||
451 | /* UART1 */ | |
452 | serial1: serial@4600 { | |
453 | cell-index = <1>; | |
454 | device_type = "serial"; | |
f706bed1 | 455 | compatible = "fsl,ns16550", "ns16550"; |
317bf653 NC |
456 | reg = <0x4600 0x100>; |
457 | clock-frequency = <0>; | |
458 | interrupts = <42 2>; | |
459 | interrupt-parent = <&mpic>; | |
460 | }; | |
461 | ||
462 | global-utilities@e0000 { //global utilities block | |
463 | compatible = "fsl,mpc8572-guts"; | |
464 | reg = <0xe0000 0x1000>; | |
465 | fsl,has-rstcr; | |
466 | }; | |
467 | ||
468 | msi@41600 { | |
469 | compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; | |
470 | reg = <0x41600 0x80>; | |
471 | msi-available-ranges = <0 0x100>; | |
472 | interrupts = < | |
473 | 0xe0 0 | |
474 | 0xe1 0 | |
475 | 0xe2 0 | |
476 | 0xe3 0 | |
477 | 0xe4 0 | |
478 | 0xe5 0 | |
479 | 0xe6 0 | |
480 | 0xe7 0>; | |
481 | interrupt-parent = <&mpic>; | |
482 | }; | |
483 | ||
484 | crypto@30000 { | |
485 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", | |
486 | "fsl,sec2.1", "fsl,sec2.0"; | |
487 | reg = <0x30000 0x10000>; | |
488 | interrupts = <45 2 58 2>; | |
489 | interrupt-parent = <&mpic>; | |
490 | fsl,num-channels = <4>; | |
491 | fsl,channel-fifo-len = <24>; | |
492 | fsl,exec-units-mask = <0x9fe>; | |
493 | fsl,descriptor-types-mask = <0x3ab0ebf>; | |
494 | }; | |
495 | ||
496 | mpic: pic@40000 { | |
497 | interrupt-controller; | |
498 | #address-cells = <0>; | |
499 | #interrupt-cells = <2>; | |
500 | reg = <0x40000 0x40000>; | |
501 | compatible = "chrp,open-pic"; | |
502 | device_type = "open-pic"; | |
503 | }; | |
504 | ||
505 | gpio0: gpio@f000 { | |
506 | compatible = "fsl,mpc8572-gpio"; | |
507 | reg = <0xf000 0x1000>; | |
508 | interrupts = <47 2>; | |
509 | interrupt-parent = <&mpic>; | |
510 | #gpio-cells = <2>; | |
511 | gpio-controller; | |
512 | }; | |
513 | ||
514 | gpio-leds { | |
515 | compatible = "gpio-leds"; | |
516 | ||
517 | heartbeat { | |
518 | label = "Heartbeat"; | |
519 | gpios = <&gpio0 4 1>; | |
520 | linux,default-trigger = "heartbeat"; | |
521 | }; | |
522 | ||
523 | yellow { | |
524 | label = "Yellow"; | |
525 | gpios = <&gpio0 5 1>; | |
526 | }; | |
527 | ||
528 | red { | |
529 | label = "Red"; | |
530 | gpios = <&gpio0 6 1>; | |
531 | }; | |
532 | ||
533 | green { | |
534 | label = "Green"; | |
535 | gpios = <&gpio0 7 1>; | |
536 | }; | |
537 | }; | |
538 | ||
539 | /* PME (pattern-matcher) */ | |
540 | pme@10000 { | |
541 | compatible = "fsl,mpc8572-pme", "pme8572"; | |
542 | reg = <0x10000 0x5000>; | |
543 | interrupts = <57 2 64 2 65 2 66 2 67 2>; | |
544 | interrupt-parent = <&mpic>; | |
545 | }; | |
546 | ||
547 | tlu@2f000 { | |
548 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | |
549 | reg = <0x2f000 0x1000>; | |
53567cf3 | 550 | interrupts = <61 2>; |
317bf653 NC |
551 | interrupt-parent = <&mpic>; |
552 | }; | |
553 | ||
554 | tlu@15000 { | |
555 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | |
556 | reg = <0x15000 0x1000>; | |
53567cf3 | 557 | interrupts = <75 2>; |
317bf653 NC |
558 | interrupt-parent = <&mpic>; |
559 | }; | |
560 | }; | |
561 | ||
562 | /* | |
563 | * PCI Express controller 3 @ ef008000 is not used. | |
564 | * This would have been pci0 on other mpc85xx platforms. | |
565 | */ | |
566 | ||
567 | /* PCI Express controller 2, wired to XMC P15 connector */ | |
568 | pci1: pcie@ef009000 { | |
569 | compatible = "fsl,mpc8548-pcie"; | |
570 | device_type = "pci"; | |
571 | #interrupt-cells = <1>; | |
572 | #size-cells = <2>; | |
573 | #address-cells = <3>; | |
574 | reg = <0 0xef009000 0 0x1000>; | |
575 | bus-range = <0 255>; | |
576 | ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 | |
577 | 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; | |
578 | clock-frequency = <33333333>; | |
579 | interrupt-parent = <&mpic>; | |
580 | interrupts = <25 2>; | |
581 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
582 | interrupt-map = < | |
583 | /* IDSEL 0x0 */ | |
584 | 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 | |
585 | 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 | |
586 | 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 | |
587 | 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 | |
588 | >; | |
589 | pcie@0 { | |
590 | reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; | |
591 | #size-cells = <2>; | |
592 | #address-cells = <3>; | |
593 | device_type = "pci"; | |
594 | ranges = <0x2000000 0x0 0xc0000000 | |
595 | 0x2000000 0x0 0xc0000000 | |
596 | 0x0 0x10000000 | |
597 | ||
598 | 0x1000000 0x0 0x0 | |
599 | 0x1000000 0x0 0x0 | |
600 | 0x0 0x100000>; | |
601 | }; | |
602 | }; | |
603 | ||
604 | /* PCI Express controller 1, wired to PEX8112 for PMC interface */ | |
605 | pci2: pcie@ef00a000 { | |
606 | compatible = "fsl,mpc8548-pcie"; | |
607 | device_type = "pci"; | |
608 | #interrupt-cells = <1>; | |
609 | #size-cells = <2>; | |
610 | #address-cells = <3>; | |
611 | reg = <0 0xef00a000 0 0x1000>; | |
612 | bus-range = <0 255>; | |
613 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 | |
614 | 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; | |
615 | clock-frequency = <33333333>; | |
616 | interrupt-parent = <&mpic>; | |
617 | interrupts = <26 2>; | |
618 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
619 | interrupt-map = < | |
620 | /* IDSEL 0x0 */ | |
621 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | |
622 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | |
623 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | |
624 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | |
625 | >; | |
626 | pcie@0 { | |
627 | reg = <0x0 0x0 0x0 0x0 0x0>; | |
628 | #size-cells = <2>; | |
629 | #address-cells = <3>; | |
630 | device_type = "pci"; | |
631 | ranges = <0x2000000 0x0 0x80000000 | |
632 | 0x2000000 0x0 0x80000000 | |
633 | 0x0 0x40000000 | |
634 | ||
635 | 0x1000000 0x0 0x0 | |
636 | 0x1000000 0x0 0x0 | |
637 | 0x0 0x100000>; | |
638 | }; | |
639 | }; | |
640 | }; |