[linux-2.6-block.git] / arch / powerpc / boot / dts / xpedite5200.dts

/*
 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
 * Based on TQM8548 device tree
 *
 * XPedite5200 PrPMC/XMC module based on MPC8548E
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "xes,xpedite5200";
	compatible = "xes,xpedite5200", "xes,MPC8548";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;

		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8548@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;	// L1, 32K
			i-cache-size = <0x8000>;	// L1, 32K
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;	// Filled in by U-Boot
	};

	soc@ef000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xef000000 0x100000>;
		bus-frequency = <0>;
		compatible = "fsl,mpc8548-immr", "simple-bus";

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <12>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8548-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8548-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		/* On-card I2C */
		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			/*
			 * Board GPIO:
			 * 	0: BRD_CFG0 (1: P14 IO present)
			 * 	1: BRD_CFG1 (1: FP ethernet present)
			 * 	2: BRD_CFG2 (1: XMC IO present)
			 * 	3: XMC root complex indicator
			 * 	4: Flash boot device indicator
			 * 	5: Flash write protect enable
			 * 	6: PMC monarch indicator
			 * 	7: PMC EREADY
			 */
			gpio1: gpio@18 {
				compatible = "nxp,pca9556";
				reg = <0x18>;
				#gpio-cells = <2>;
				gpio-controller;
				polarity = <0x00>;
			};

			/* P14 GPIO */
			gpio2: gpio@19 {
				compatible = "nxp,pca9556";
				reg = <0x19>;
				#gpio-cells = <2>;
				gpio-controller;
				polarity = <0x00>;
			};

			eeprom@50 {
				compatible = "atmel,at24c16";
				reg = <0x50>;
			};

			rtc@68 {
				compatible = "st,m41t00",
					     "dallas,ds1338";
				reg = <0x68>;
			};

			dtt@48 {
				compatible = "maxim,max1237";
				reg = <0x34>;
			};
		};

		/* Off-card I2C */
		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8548-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		/* eTSEC1: Front panel port 0 */
		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <8 1>;
					reg = <0x1>;
				};
				phy1: ethernet-phy@2 {
					interrupt-parent = <&mpic>;
					interrupts = <8 1>;
					reg = <0x2>;
				};
				phy2: ethernet-phy@3 {
					interrupt-parent = <&mpic>;
					interrupts = <8 1>;
					reg = <0x3>;
				};
				phy3: ethernet-phy@4 {
					interrupt-parent = <&mpic>;
					interrupts = <8 1>;
					reg = <0x4>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		/* eTSEC2: Front panel port 1 */
		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		/* eTSEC3: Rear panel port 2 */
		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		/* eTSEC4: Rear panel port 3 */
		enet3: ethernet@27000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <3>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			ranges = <0x0 0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi3: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			current-speed = <115200>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			current-speed = <115200>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	// global utilities reg
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};
	};

	localbus@ef005000 {
		compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
			     "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		reg = <0xef005000 0x100>;	// BRx, ORx, etc.
		interrupt-parent = <&mpic>;
		interrupts = <19 2>;

		ranges = <
			0 0x0 0xfc000000 0x04000000	// NOR boot flash
			1 0x0 0xf8000000 0x04000000	// NOR expansion flash
			2 0x0 0xef800000 0x00010000	// NAND CE1
			3 0x0 0xef840000 0x00010000	// NAND CE2
		>;

		nor-boot@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0 0x0 0x4000000>;
			bank-width = <2>;

			partition@0 {
				label = "Primary OS";
				reg = <0x00000000 0x180000>;
			};
			partition@180000 {
				label = "Secondary OS";
				reg = <0x00180000 0x180000>;
			};
			partition@300000 {
				label = "User";
				reg = <0x00300000 0x3c80000>;
			};
			partition@3f80000 {
				label = "Boot firmware";
				reg = <0x03f80000 0x80000>;
			};
		};

		nor-alternate@1,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <1 0x0 0x4000000>;
			bank-width = <2>;

			partition@0 {
				label = "Filesystem";
				reg = <0x00000000 0x3f80000>;
			};
			partition@3f80000 {
				label = "Alternate boot firmware";
				reg = <0x03f80000 0x80000>;
			};
		};

		nand@2,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "xes,address-ctl-nand";
			reg = <2 0x0 0x10000>;
			cle-line = <0x8>;	/* CLE tied to A3 */
			ale-line = <0x10>;	/* ALE tied to A4 */

			/* U-Boot should fix this up */
			partition@0 {
				label = "NAND Filesystem";
				reg = <0 0x40000000>;
			};
		};
	};

	/* PMC interface */
	pci0: pci@ef008000 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
		device_type = "pci";
		reg = <0xef008000 0x1000>;
		clock-frequency = <33333333>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
				/* IDSEL */
				 0xe000 0 0 1 &mpic 2 1
				 0xe000 0 0 2 &mpic 3 1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
			  0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
	};

	/* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
};
Commit	Line	Data
317bf653 NC	1	/*
	2	* Copyright (C) 2009 Extreme Engineering Solutions, Inc.
	3	* Based on TQM8548 device tree
	4	*
	5	* XPedite5200 PrPMC/XMC module based on MPC8548E
	6	*
	7	* This is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	/dts-v1/;
	13
	14	/ {
	15	model = "xes,xpedite5200";
	16	compatible = "xes,xpedite5200", "xes,MPC8548";
	17	#address-cells = <1>;
	18	#size-cells = <1>;
	19
	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	ethernet2 = &enet2;
	24	ethernet3 = &enet3;
	25
	26	serial0 = &serial0;
	27	serial1 = &serial1;
	28	pci0 = &pci0;
	29	};
	30
	31	cpus {
	32	#address-cells = <1>;
	33	#size-cells = <0>;
	34
	35	PowerPC,8548@0 {
	36	device_type = "cpu";
	37	reg = <0>;
	38	d-cache-line-size = <32>; // 32 bytes
	39	i-cache-line-size = <32>; // 32 bytes
	40	d-cache-size = <0x8000>; // L1, 32K
	41	i-cache-size = <0x8000>; // L1, 32K
	42	next-level-cache = <&L2>;
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
	48	reg = <0x0 0x0>; // Filled in by U-Boot
	49	};
	50
	51	soc@ef000000 {
	52	#address-cells = <1>;
	53	#size-cells = <1>;
	54	device_type = "soc";
	55	ranges = <0x0 0xef000000 0x100000>;
	56	bus-frequency = <0>;
	57	compatible = "fsl,mpc8548-immr", "simple-bus";
	58
	59	ecm-law@0 {
	60	compatible = "fsl,ecm-law";
	61	reg = <0x0 0x1000>;
	62	fsl,num-laws = <12>;
	63	};
	64
65	ecm@1000 {
66	compatible = "fsl,mpc8548-ecm", "fsl,ecm";
67	reg = <0x1000 0x1000>;
68	interrupts = <17 2>;
69	interrupt-parent = <&mpic>;
70	};
71
72	memory-controller@2000 {
73	compatible = "fsl,mpc8548-memory-controller";
74	reg = <0x2000 0x1000>;
75	interrupt-parent = <&mpic>;
76	interrupts = <18 2>;
77	};
78
79	L2: l2-cache-controller@20000 {
80	compatible = "fsl,mpc8548-l2-cache-controller";
81	reg = <0x20000 0x1000>;
82	cache-line-size = <32>; // 32 bytes
83	cache-size = <0x80000>; // L2, 512K
84	interrupt-parent = <&mpic>;
85	interrupts = <16 2>;
86	};
87
88	/* On-card I2C */
89	i2c@3000 {
90	#address-cells = <1>;
91	#size-cells = <0>;
92	cell-index = <0>;
93	compatible = "fsl-i2c";
94	reg = <0x3000 0x100>;
95	interrupts = <43 2>;
96	interrupt-parent = <&mpic>;
97	dfsrr;
98
99	/*
100	* Board GPIO:
101	* 0: BRD_CFG0 (1: P14 IO present)
102	* 1: BRD_CFG1 (1: FP ethernet present)
103	* 2: BRD_CFG2 (1: XMC IO present)
104	* 3: XMC root complex indicator
105	* 4: Flash boot device indicator
106	* 5: Flash write protect enable
107	* 6: PMC monarch indicator
108	* 7: PMC EREADY
109	*/
110	gpio1: gpio@18 {
111	compatible = "nxp,pca9556";
112	reg = <0x18>;
113	#gpio-cells = <2>;
114	gpio-controller;
115	polarity = <0x00>;
116	};
117
118	/* P14 GPIO */
119	gpio2: gpio@19 {
120	compatible = "nxp,pca9556";
121	reg = <0x19>;
122	#gpio-cells = <2>;
123	gpio-controller;
124	polarity = <0x00>;
125	};
126
127	eeprom@50 {
128	compatible = "atmel,at24c16";
129	reg = <0x50>;
130	};
131
132	rtc@68 {
5edc2aae	133	compatible = "st,m41t00",
317bf653 NC	134	"dallas,ds1338";
	135	reg = <0x68>;
	136	};
	137
	138	dtt@48 {
	139	compatible = "maxim,max1237";
	140	reg = <0x34>;
	141	};
	142	};
	143
	144	/* Off-card I2C */
	145	i2c@3100 {
	146	#address-cells = <1>;
	147	#size-cells = <0>;
	148	cell-index = <1>;
	149	compatible = "fsl-i2c";
	150	reg = <0x3100 0x100>;
	151	interrupts = <43 2>;
	152	interrupt-parent = <&mpic>;
	153	dfsrr;
	154	};
	155
	156	dma@21300 {
	157	#address-cells = <1>;
	158	#size-cells = <1>;
	159	compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
	160	reg = <0x21300 0x4>;
	161	ranges = <0x0 0x21100 0x200>;
	162	cell-index = <0>;
	163	dma-channel@0 {
	164	compatible = "fsl,mpc8548-dma-channel",
	165	"fsl,eloplus-dma-channel";
	166	reg = <0x0 0x80>;
	167	cell-index = <0>;
	168	interrupt-parent = <&mpic>;
	169	interrupts = <20 2>;
	170	};
	171	dma-channel@80 {
	172	compatible = "fsl,mpc8548-dma-channel",
	173	"fsl,eloplus-dma-channel";
	174	reg = <0x80 0x80>;
	175	cell-index = <1>;
	176	interrupt-parent = <&mpic>;
	177	interrupts = <21 2>;
	178	};
	179	dma-channel@100 {
	180	compatible = "fsl,mpc8548-dma-channel",
	181	"fsl,eloplus-dma-channel";
	182	reg = <0x100 0x80>;
	183	cell-index = <2>;
	184	interrupt-parent = <&mpic>;
	185	interrupts = <22 2>;
	186	};
	187	dma-channel@180 {
	188	compatible = "fsl,mpc8548-dma-channel",
	189	"fsl,eloplus-dma-channel";
	190	reg = <0x180 0x80>;
	191	cell-index = <3>;
	192	interrupt-parent = <&mpic>;
	193	interrupts = <23 2>;
	194	};
	195	};
	196
	197	/* eTSEC1: Front panel port 0 */
198	enet0: ethernet@24000 {
199	#address-cells = <1>;
200	#size-cells = <1>;
201	cell-index = <0>;
202	device_type = "network";
203	model = "eTSEC";
204	compatible = "gianfar";
205	reg = <0x24000 0x1000>;
206	ranges = <0x0 0x24000 0x1000>;
207	local-mac-address = [ 00 00 00 00 00 00 ];
208	interrupts = <29 2 30 2 34 2>;
209	interrupt-parent = <&mpic>;
210	tbi-handle = <&tbi0>;
211	phy-handle = <&phy0>;
212
213	mdio@520 {
214	#address-cells = <1>;
215	#size-cells = <0>;
216	compatible = "fsl,gianfar-mdio";
217	reg = <0x520 0x20>;
218
219	phy0: ethernet-phy@1 {
220	interrupt-parent = <&mpic>;
221	interrupts = <8 1>;
222	reg = <0x1>;
223	};
224	phy1: ethernet-phy@2 {
225	interrupt-parent = <&mpic>;
226	interrupts = <8 1>;
227	reg = <0x2>;
228	};
229	phy2: ethernet-phy@3 {
230	interrupt-parent = <&mpic>;
231	interrupts = <8 1>;
232	reg = <0x3>;
233	};
234	phy3: ethernet-phy@4 {
235	interrupt-parent = <&mpic>;
236	interrupts = <8 1>;
237	reg = <0x4>;
238	};
239	tbi0: tbi-phy@11 {
240	reg = <0x11>;
241	device_type = "tbi-phy";
242	};
243	};
244	};
245
246	/* eTSEC2: Front panel port 1 */
247	enet1: ethernet@25000 {
248	#address-cells = <1>;
249	#size-cells = <1>;
250	cell-index = <1>;
251	device_type = "network";
252	model = "eTSEC";
253	compatible = "gianfar";
254	reg = <0x25000 0x1000>;
255	ranges = <0x0 0x25000 0x1000>;
256	local-mac-address = [ 00 00 00 00 00 00 ];
257	interrupts = <35 2 36 2 40 2>;
258	interrupt-parent = <&mpic>;
259	tbi-handle = <&tbi1>;
260	phy-handle = <&phy1>;
261
262	mdio@520 {
263	#address-cells = <1>;
264	#size-cells = <0>;
265	compatible = "fsl,gianfar-tbi";
266	reg = <0x520 0x20>;
267
268	tbi1: tbi-phy@11 {
269	reg = <0x11>;
270	device_type = "tbi-phy";
271	};
272	};
273	};
274
275	/* eTSEC3: Rear panel port 2 */
276	enet2: ethernet@26000 {
277	#address-cells = <1>;
278	#size-cells = <1>;
279	cell-index = <2>;
280	device_type = "network";
281	model = "eTSEC";
282	compatible = "gianfar";
283	reg = <0x26000 0x1000>;
284	ranges = <0x0 0x26000 0x1000>;
285	local-mac-address = [ 00 00 00 00 00 00 ];
286	interrupts = <31 2 32 2 33 2>;
287	interrupt-parent = <&mpic>;
288	tbi-handle = <&tbi2>;
289	phy-handle = <&phy2>;
290
291	mdio@520 {
292	#address-cells = <1>;
293	#size-cells = <0>;
294	compatible = "fsl,gianfar-tbi";
295	reg = <0x520 0x20>;
296
297	tbi2: tbi-phy@11 {
298	reg = <0x11>;
299	device_type = "tbi-phy";
300	};
301	};
302	};
303
304	/* eTSEC4: Rear panel port 3 */
305	enet3: ethernet@27000 {
306	#address-cells = <1>;
307	#size-cells = <1>;
308	cell-index = <3>;
309	device_type = "network";
310	model = "eTSEC";
311	compatible = "gianfar";
312	reg = <0x27000 0x1000>;
313	ranges = <0x0 0x27000 0x1000>;
314	local-mac-address = [ 00 00 00 00 00 00 ];
315	interrupts = <37 2 38 2 39 2>;
316	interrupt-parent = <&mpic>;
317	tbi-handle = <&tbi3>;
318	phy-handle = <&phy3>;
319
320	mdio@520 {
321	#address-cells = <1>;
322	#size-cells = <0>;
323	compatible = "fsl,gianfar-tbi";
324	reg = <0x520 0x20>;
325
326	tbi3: tbi-phy@11 {
327	reg = <0x11>;
328	device_type = "tbi-phy";
329	};
330	};
331	};
332
333	serial0: serial@4500 {
334	cell-index = <0>;
335	device_type = "serial";
f706bed1	336	compatible = "fsl,ns16550", "ns16550";
317bf653 NC	337	reg = <0x4500 0x100>;
	338	clock-frequency = <0>;
	339	current-speed = <115200>;
	340	interrupts = <42 2>;
	341	interrupt-parent = <&mpic>;
	342	};
	343
	344	serial1: serial@4600 {
	345	cell-index = <1>;
	346	device_type = "serial";
f706bed1	347	compatible = "fsl,ns16550", "ns16550";
317bf653 NC	348	reg = <0x4600 0x100>;
	349	clock-frequency = <0>;
	350	current-speed = <115200>;
	351	interrupts = <42 2>;
	352	interrupt-parent = <&mpic>;
	353	};
	354
	355	global-utilities@e0000 { // global utilities reg
	356	compatible = "fsl,mpc8548-guts";
	357	reg = <0xe0000 0x1000>;
	358	fsl,has-rstcr;
	359	};
	360
	361	mpic: pic@40000 {
	362	interrupt-controller;
	363	#address-cells = <0>;
	364	#interrupt-cells = <2>;
	365	reg = <0x40000 0x40000>;
	366	compatible = "chrp,open-pic";
	367	device_type = "open-pic";
	368	};
	369	};
	370
	371	localbus@ef005000 {
	372	compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
	373	"simple-bus";
	374	#address-cells = <2>;
	375	#size-cells = <1>;
	376	reg = <0xef005000 0x100>; // BRx, ORx, etc.
c0f58950 DES	377	interrupt-parent = <&mpic>;
c0f58950 DES	378	interrupts = <19 2>;
317bf653 NC	379
	380	ranges = <
	381	0 0x0 0xfc000000 0x04000000 // NOR boot flash
	382	1 0x0 0xf8000000 0x04000000 // NOR expansion flash
	383	2 0x0 0xef800000 0x00010000 // NAND CE1
	384	3 0x0 0xef840000 0x00010000 // NAND CE2
	385	>;
	386
	387	nor-boot@0,0 {
	388	#address-cells = <1>;
	389	#size-cells = <1>;
	390	compatible = "cfi-flash";
	391	reg = <0 0x0 0x4000000>;
	392	bank-width = <2>;
	393
	394	partition@0 {
	395	label = "Primary OS";
	396	reg = <0x00000000 0x180000>;
	397	};
	398	partition@180000 {
	399	label = "Secondary OS";
	400	reg = <0x00180000 0x180000>;
	401	};
	402	partition@300000 {
	403	label = "User";
	404	reg = <0x00300000 0x3c80000>;
	405	};
	406	partition@3f80000 {
	407	label = "Boot firmware";
	408	reg = <0x03f80000 0x80000>;
	409	};
	410	};
	411
	412	nor-alternate@1,0 {
	413	#address-cells = <1>;
	414	#size-cells = <1>;
	415	compatible = "cfi-flash";
	416	reg = <1 0x0 0x4000000>;
	417	bank-width = <2>;
	418
	419	partition@0 {
	420	label = "Filesystem";
	421	reg = <0x00000000 0x3f80000>;
	422	};
	423	partition@3f80000 {
	424	label = "Alternate boot firmware";
	425	reg = <0x03f80000 0x80000>;
	426	};
	427	};
	428
	429	nand@2,0 {
	430	#address-cells = <1>;
	431	#size-cells = <1>;
	432	compatible = "xes,address-ctl-nand";
	433	reg = <2 0x0 0x10000>;
	434	cle-line = <0x8>; /* CLE tied to A3 */
	435	ale-line = <0x10>; /* ALE tied to A4 */
	436
	437	/* U-Boot should fix this up */
	438	partition@0 {
	439	label = "NAND Filesystem";
	440	reg = <0 0x40000000>;
	441	};
	442	};
443	};
444
445	/* PMC interface */
446	pci0: pci@ef008000 {
447	#interrupt-cells = <1>;
448	#size-cells = <2>;
449	#address-cells = <3>;
450	compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
451	device_type = "pci";
452	reg = <0xef008000 0x1000>;
453	clock-frequency = <33333333>;
454	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
455	interrupt-map = <
456	/* IDSEL */
457	0xe000 0 0 1 &mpic 2 1
458	0xe000 0 0 2 &mpic 3 1>;
459
460	interrupt-parent = <&mpic>;
461	interrupts = <24 2>;
462	bus-range = <0 0>;
463	ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
464	0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
465	};
466
467	/* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
468	};