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317bf653 NC |
1 | /* |
2 | * Copyright (C) 2008 Extreme Engineering Solutions, Inc. | |
3 | * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. | |
4 | * | |
5 | * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E | |
6 | * | |
7 | * This is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | /dts-v1/; | |
13 | / { | |
14 | model = "xes,xcalibur1501"; | |
15 | compatible = "xes,xcalibur1501", "xes,MPC8572"; | |
16 | #address-cells = <2>; | |
17 | #size-cells = <2>; | |
18 | ||
19 | aliases { | |
20 | ethernet0 = &enet0; | |
21 | ethernet1 = &enet1; | |
22 | ethernet2 = &enet2; | |
23 | ethernet3 = &enet3; | |
24 | serial0 = &serial0; | |
25 | serial1 = &serial1; | |
26 | pci2 = &pci2; | |
27 | }; | |
28 | ||
29 | cpus { | |
30 | #address-cells = <1>; | |
31 | #size-cells = <0>; | |
32 | ||
33 | PowerPC,8572@0 { | |
34 | device_type = "cpu"; | |
35 | reg = <0x0>; | |
36 | d-cache-line-size = <32>; // 32 bytes | |
37 | i-cache-line-size = <32>; // 32 bytes | |
38 | d-cache-size = <0x8000>; // L1, 32K | |
39 | i-cache-size = <0x8000>; // L1, 32K | |
40 | timebase-frequency = <0>; | |
41 | bus-frequency = <0>; | |
42 | clock-frequency = <0>; | |
43 | next-level-cache = <&L2>; | |
44 | }; | |
45 | ||
46 | PowerPC,8572@1 { | |
47 | device_type = "cpu"; | |
48 | reg = <0x1>; | |
49 | d-cache-line-size = <32>; // 32 bytes | |
50 | i-cache-line-size = <32>; // 32 bytes | |
51 | d-cache-size = <0x8000>; // L1, 32K | |
52 | i-cache-size = <0x8000>; // L1, 32K | |
53 | timebase-frequency = <0>; | |
54 | bus-frequency = <0>; | |
55 | clock-frequency = <0>; | |
56 | next-level-cache = <&L2>; | |
57 | }; | |
58 | }; | |
59 | ||
60 | memory { | |
61 | device_type = "memory"; | |
62 | reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot | |
63 | }; | |
64 | ||
65 | localbus@ef005000 { | |
66 | #address-cells = <2>; | |
67 | #size-cells = <1>; | |
68 | compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; | |
69 | reg = <0 0xef005000 0 0x1000>; | |
70 | interrupts = <19 2>; | |
71 | interrupt-parent = <&mpic>; | |
72 | /* Local bus region mappings */ | |
73 | ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */ | |
74 | 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */ | |
75 | 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ | |
76 | 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */ | |
77 | 4 0 0 0xe9000000 0x100000>; /* CS4: USB */ | |
78 | ||
79 | nor-boot@0,0 { | |
80 | compatible = "amd,s29gl01gp", "cfi-flash"; | |
81 | bank-width = <2>; | |
82 | reg = <0 0 0x8000000>; /* 128MB */ | |
83 | #address-cells = <1>; | |
84 | #size-cells = <1>; | |
85 | partition@0 { | |
86 | label = "Primary user space"; | |
87 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | |
88 | }; | |
89 | partition@6f00000 { | |
90 | label = "Primary kernel"; | |
91 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | |
92 | }; | |
93 | partition@7f00000 { | |
94 | label = "Primary DTB"; | |
95 | reg = <0x7f00000 0x40000>; /* 256 KB */ | |
96 | }; | |
97 | partition@7f40000 { | |
98 | label = "Primary U-Boot environment"; | |
99 | reg = <0x7f40000 0x40000>; /* 256 KB */ | |
100 | }; | |
101 | partition@7f80000 { | |
102 | label = "Primary U-Boot"; | |
103 | reg = <0x7f80000 0x80000>; /* 512 KB */ | |
104 | read-only; | |
105 | }; | |
106 | }; | |
107 | ||
108 | nor-alternate@1,0 { | |
109 | compatible = "amd,s29gl01gp", "cfi-flash"; | |
110 | bank-width = <2>; | |
111 | //reg = <0xf0000000 0x08000000>; /* 128MB */ | |
112 | reg = <1 0 0x8000000>; /* 128MB */ | |
113 | #address-cells = <1>; | |
114 | #size-cells = <1>; | |
115 | partition@0 { | |
116 | label = "Secondary user space"; | |
117 | reg = <0x00000000 0x6f00000>; /* 111 MB */ | |
118 | }; | |
119 | partition@6f00000 { | |
120 | label = "Secondary kernel"; | |
121 | reg = <0x6f00000 0x1000000>; /* 16 MB */ | |
122 | }; | |
123 | partition@7f00000 { | |
124 | label = "Secondary DTB"; | |
125 | reg = <0x7f00000 0x40000>; /* 256 KB */ | |
126 | }; | |
127 | partition@7f40000 { | |
128 | label = "Secondary U-Boot environment"; | |
129 | reg = <0x7f40000 0x40000>; /* 256 KB */ | |
130 | }; | |
131 | partition@7f80000 { | |
132 | label = "Secondary U-Boot"; | |
133 | reg = <0x7f80000 0x80000>; /* 512 KB */ | |
134 | read-only; | |
135 | }; | |
136 | }; | |
137 | ||
138 | nand@2,0 { | |
139 | #address-cells = <1>; | |
140 | #size-cells = <1>; | |
141 | /* | |
142 | * Actual part could be ST Micro NAND08GW3B2A (1 GB), | |
143 | * Micron MT29F8G08DAA (2x 512 MB), or Micron | |
144 | * MT29F16G08FAA (2x 1 GB), depending on the build | |
145 | * configuration | |
146 | */ | |
147 | compatible = "fsl,mpc8572-fcm-nand", | |
148 | "fsl,elbc-fcm-nand"; | |
149 | reg = <2 0 0x40000>; | |
150 | /* U-Boot should fix this up if chip size > 1 GB */ | |
151 | partition@0 { | |
152 | label = "NAND Filesystem"; | |
153 | reg = <0 0x40000000>; | |
154 | }; | |
155 | }; | |
156 | ||
157 | usb@4,0 { | |
158 | compatible = "nxp,usb-isp1761"; | |
159 | reg = <4 0 0x100000>; | |
160 | bus-width = <32>; | |
161 | interrupt-parent = <&mpic>; | |
162 | interrupts = <10 1>; | |
163 | }; | |
164 | }; | |
165 | ||
166 | soc8572@ef000000 { | |
167 | #address-cells = <1>; | |
168 | #size-cells = <1>; | |
169 | device_type = "soc"; | |
170 | compatible = "fsl,mpc8572-immr", "simple-bus"; | |
171 | ranges = <0x0 0 0xef000000 0x100000>; | |
172 | bus-frequency = <0>; // Filled out by uboot. | |
173 | ||
174 | ecm-law@0 { | |
175 | compatible = "fsl,ecm-law"; | |
176 | reg = <0x0 0x1000>; | |
177 | fsl,num-laws = <12>; | |
178 | }; | |
179 | ||
180 | ecm@1000 { | |
181 | compatible = "fsl,mpc8572-ecm", "fsl,ecm"; | |
182 | reg = <0x1000 0x1000>; | |
183 | interrupts = <17 2>; | |
184 | interrupt-parent = <&mpic>; | |
185 | }; | |
186 | ||
187 | memory-controller@2000 { | |
188 | compatible = "fsl,mpc8572-memory-controller"; | |
189 | reg = <0x2000 0x1000>; | |
190 | interrupt-parent = <&mpic>; | |
191 | interrupts = <18 2>; | |
192 | }; | |
193 | ||
194 | memory-controller@6000 { | |
195 | compatible = "fsl,mpc8572-memory-controller"; | |
196 | reg = <0x6000 0x1000>; | |
197 | interrupt-parent = <&mpic>; | |
198 | interrupts = <18 2>; | |
199 | }; | |
200 | ||
201 | L2: l2-cache-controller@20000 { | |
202 | compatible = "fsl,mpc8572-l2-cache-controller"; | |
203 | reg = <0x20000 0x1000>; | |
204 | cache-line-size = <32>; // 32 bytes | |
205 | cache-size = <0x100000>; // L2, 1M | |
206 | interrupt-parent = <&mpic>; | |
207 | interrupts = <16 2>; | |
208 | }; | |
209 | ||
210 | i2c@3000 { | |
211 | #address-cells = <1>; | |
212 | #size-cells = <0>; | |
213 | cell-index = <0>; | |
214 | compatible = "fsl-i2c"; | |
215 | reg = <0x3000 0x100>; | |
216 | interrupts = <43 2>; | |
217 | interrupt-parent = <&mpic>; | |
218 | dfsrr; | |
219 | ||
220 | temp-sensor@48 { | |
221 | compatible = "dallas,ds1631", "dallas,ds1621"; | |
222 | reg = <0x48>; | |
223 | }; | |
224 | ||
225 | temp-sensor@4c { | |
226 | compatible = "adi,adt7461"; | |
227 | reg = <0x4c>; | |
228 | }; | |
229 | ||
230 | cpu-supervisor@51 { | |
231 | compatible = "dallas,ds4510"; | |
232 | reg = <0x51>; | |
233 | }; | |
234 | ||
235 | eeprom@54 { | |
236 | compatible = "atmel,at24c128b"; | |
237 | reg = <0x54>; | |
238 | }; | |
239 | ||
240 | rtc@68 { | |
241 | compatible = "stm,m41t00", | |
242 | "dallas,ds1338"; | |
243 | reg = <0x68>; | |
244 | }; | |
245 | ||
246 | pcie-switch@6a { | |
247 | compatible = "plx,pex8648"; | |
248 | reg = <0x6a>; | |
249 | }; | |
250 | ||
251 | /* On-board signals for VID, flash, serial */ | |
252 | gpio1: gpio@18 { | |
253 | compatible = "nxp,pca9557"; | |
254 | reg = <0x18>; | |
255 | #gpio-cells = <2>; | |
256 | gpio-controller; | |
257 | polarity = <0x00>; | |
258 | }; | |
259 | ||
260 | /* PMC0/XMC0 signals */ | |
261 | gpio2: gpio@1c { | |
262 | compatible = "nxp,pca9557"; | |
263 | reg = <0x1c>; | |
264 | #gpio-cells = <2>; | |
265 | gpio-controller; | |
266 | polarity = <0x00>; | |
267 | }; | |
268 | ||
269 | /* PMC1/XMC1 signals */ | |
270 | gpio3: gpio@1d { | |
271 | compatible = "nxp,pca9557"; | |
272 | reg = <0x1d>; | |
273 | #gpio-cells = <2>; | |
274 | gpio-controller; | |
275 | polarity = <0x00>; | |
276 | }; | |
277 | ||
278 | /* CompactPCI signals (sysen, GA[4:0]) */ | |
279 | gpio4: gpio@1e { | |
280 | compatible = "nxp,pca9557"; | |
281 | reg = <0x1e>; | |
282 | #gpio-cells = <2>; | |
283 | gpio-controller; | |
284 | polarity = <0x00>; | |
285 | }; | |
286 | ||
287 | /* CompactPCI J5 GPIO and FAL/DEG/PRST */ | |
288 | gpio5: gpio@1f { | |
289 | compatible = "nxp,pca9557"; | |
290 | reg = <0x1f>; | |
291 | #gpio-cells = <2>; | |
292 | gpio-controller; | |
293 | polarity = <0x00>; | |
294 | }; | |
295 | }; | |
296 | ||
297 | i2c@3100 { | |
298 | #address-cells = <1>; | |
299 | #size-cells = <0>; | |
300 | cell-index = <1>; | |
301 | compatible = "fsl-i2c"; | |
302 | reg = <0x3100 0x100>; | |
303 | interrupts = <43 2>; | |
304 | interrupt-parent = <&mpic>; | |
305 | dfsrr; | |
306 | }; | |
307 | ||
308 | dma@c300 { | |
309 | #address-cells = <1>; | |
310 | #size-cells = <1>; | |
311 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | |
312 | reg = <0xc300 0x4>; | |
313 | ranges = <0x0 0xc100 0x200>; | |
314 | cell-index = <1>; | |
315 | dma-channel@0 { | |
316 | compatible = "fsl,mpc8572-dma-channel", | |
317 | "fsl,eloplus-dma-channel"; | |
318 | reg = <0x0 0x80>; | |
319 | cell-index = <0>; | |
320 | interrupt-parent = <&mpic>; | |
321 | interrupts = <76 2>; | |
322 | }; | |
323 | dma-channel@80 { | |
324 | compatible = "fsl,mpc8572-dma-channel", | |
325 | "fsl,eloplus-dma-channel"; | |
326 | reg = <0x80 0x80>; | |
327 | cell-index = <1>; | |
328 | interrupt-parent = <&mpic>; | |
329 | interrupts = <77 2>; | |
330 | }; | |
331 | dma-channel@100 { | |
332 | compatible = "fsl,mpc8572-dma-channel", | |
333 | "fsl,eloplus-dma-channel"; | |
334 | reg = <0x100 0x80>; | |
335 | cell-index = <2>; | |
336 | interrupt-parent = <&mpic>; | |
337 | interrupts = <78 2>; | |
338 | }; | |
339 | dma-channel@180 { | |
340 | compatible = "fsl,mpc8572-dma-channel", | |
341 | "fsl,eloplus-dma-channel"; | |
342 | reg = <0x180 0x80>; | |
343 | cell-index = <3>; | |
344 | interrupt-parent = <&mpic>; | |
345 | interrupts = <79 2>; | |
346 | }; | |
347 | }; | |
348 | ||
349 | dma@21300 { | |
350 | #address-cells = <1>; | |
351 | #size-cells = <1>; | |
352 | compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; | |
353 | reg = <0x21300 0x4>; | |
354 | ranges = <0x0 0x21100 0x200>; | |
355 | cell-index = <0>; | |
356 | dma-channel@0 { | |
357 | compatible = "fsl,mpc8572-dma-channel", | |
358 | "fsl,eloplus-dma-channel"; | |
359 | reg = <0x0 0x80>; | |
360 | cell-index = <0>; | |
361 | interrupt-parent = <&mpic>; | |
362 | interrupts = <20 2>; | |
363 | }; | |
364 | dma-channel@80 { | |
365 | compatible = "fsl,mpc8572-dma-channel", | |
366 | "fsl,eloplus-dma-channel"; | |
367 | reg = <0x80 0x80>; | |
368 | cell-index = <1>; | |
369 | interrupt-parent = <&mpic>; | |
370 | interrupts = <21 2>; | |
371 | }; | |
372 | dma-channel@100 { | |
373 | compatible = "fsl,mpc8572-dma-channel", | |
374 | "fsl,eloplus-dma-channel"; | |
375 | reg = <0x100 0x80>; | |
376 | cell-index = <2>; | |
377 | interrupt-parent = <&mpic>; | |
378 | interrupts = <22 2>; | |
379 | }; | |
380 | dma-channel@180 { | |
381 | compatible = "fsl,mpc8572-dma-channel", | |
382 | "fsl,eloplus-dma-channel"; | |
383 | reg = <0x180 0x80>; | |
384 | cell-index = <3>; | |
385 | interrupt-parent = <&mpic>; | |
386 | interrupts = <23 2>; | |
387 | }; | |
388 | }; | |
389 | ||
390 | /* eTSEC 1 front panel 0 */ | |
391 | enet0: ethernet@24000 { | |
392 | #address-cells = <1>; | |
393 | #size-cells = <1>; | |
394 | cell-index = <0>; | |
395 | device_type = "network"; | |
396 | model = "eTSEC"; | |
397 | compatible = "gianfar"; | |
398 | reg = <0x24000 0x1000>; | |
399 | ranges = <0x0 0x24000 0x1000>; | |
400 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
401 | interrupts = <29 2 30 2 34 2>; | |
402 | interrupt-parent = <&mpic>; | |
403 | tbi-handle = <&tbi0>; | |
404 | phy-handle = <&phy0>; | |
405 | phy-connection-type = "sgmii"; | |
406 | ||
407 | mdio@520 { | |
408 | #address-cells = <1>; | |
409 | #size-cells = <0>; | |
410 | compatible = "fsl,gianfar-mdio"; | |
411 | reg = <0x520 0x20>; | |
412 | ||
413 | phy0: ethernet-phy@1 { | |
414 | interrupt-parent = <&mpic>; | |
415 | interrupts = <4 1>; | |
416 | reg = <0x1>; | |
417 | }; | |
418 | phy1: ethernet-phy@2 { | |
419 | interrupt-parent = <&mpic>; | |
420 | interrupts = <4 1>; | |
421 | reg = <0x2>; | |
422 | }; | |
423 | phy2: ethernet-phy@3 { | |
424 | interrupt-parent = <&mpic>; | |
425 | interrupts = <5 1>; | |
426 | reg = <0x3>; | |
427 | }; | |
428 | phy3: ethernet-phy@4 { | |
429 | interrupt-parent = <&mpic>; | |
430 | interrupts = <5 1>; | |
431 | reg = <0x4>; | |
432 | }; | |
433 | tbi0: tbi-phy@11 { | |
434 | reg = <0x11>; | |
435 | device_type = "tbi-phy"; | |
436 | }; | |
437 | }; | |
438 | }; | |
439 | ||
440 | /* eTSEC 2 front panel 1 */ | |
441 | enet1: ethernet@25000 { | |
442 | #address-cells = <1>; | |
443 | #size-cells = <1>; | |
444 | cell-index = <1>; | |
445 | device_type = "network"; | |
446 | model = "eTSEC"; | |
447 | compatible = "gianfar"; | |
448 | reg = <0x25000 0x1000>; | |
449 | ranges = <0x0 0x25000 0x1000>; | |
450 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
451 | interrupts = <35 2 36 2 40 2>; | |
452 | interrupt-parent = <&mpic>; | |
453 | tbi-handle = <&tbi1>; | |
454 | phy-handle = <&phy1>; | |
455 | phy-connection-type = "sgmii"; | |
456 | ||
457 | mdio@520 { | |
458 | #address-cells = <1>; | |
459 | #size-cells = <0>; | |
460 | compatible = "fsl,gianfar-tbi"; | |
461 | reg = <0x520 0x20>; | |
462 | ||
463 | tbi1: tbi-phy@11 { | |
464 | reg = <0x11>; | |
465 | device_type = "tbi-phy"; | |
466 | }; | |
467 | }; | |
468 | }; | |
469 | ||
470 | /* eTSEC 3 PICMG2.16 backplane port 0 */ | |
471 | enet2: ethernet@26000 { | |
472 | #address-cells = <1>; | |
473 | #size-cells = <1>; | |
474 | cell-index = <2>; | |
475 | device_type = "network"; | |
476 | model = "eTSEC"; | |
477 | compatible = "gianfar"; | |
478 | reg = <0x26000 0x1000>; | |
479 | ranges = <0x0 0x26000 0x1000>; | |
480 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
481 | interrupts = <31 2 32 2 33 2>; | |
482 | interrupt-parent = <&mpic>; | |
483 | tbi-handle = <&tbi2>; | |
484 | phy-handle = <&phy2>; | |
485 | phy-connection-type = "sgmii"; | |
486 | ||
487 | mdio@520 { | |
488 | #address-cells = <1>; | |
489 | #size-cells = <0>; | |
490 | compatible = "fsl,gianfar-tbi"; | |
491 | reg = <0x520 0x20>; | |
492 | ||
493 | tbi2: tbi-phy@11 { | |
494 | reg = <0x11>; | |
495 | device_type = "tbi-phy"; | |
496 | }; | |
497 | }; | |
498 | }; | |
499 | ||
500 | /* eTSEC 4 PICMG2.16 backplane port 1 */ | |
501 | enet3: ethernet@27000 { | |
502 | #address-cells = <1>; | |
503 | #size-cells = <1>; | |
504 | cell-index = <3>; | |
505 | device_type = "network"; | |
506 | model = "eTSEC"; | |
507 | compatible = "gianfar"; | |
508 | reg = <0x27000 0x1000>; | |
509 | ranges = <0x0 0x27000 0x1000>; | |
510 | local-mac-address = [ 00 00 00 00 00 00 ]; | |
511 | interrupts = <37 2 38 2 39 2>; | |
512 | interrupt-parent = <&mpic>; | |
513 | tbi-handle = <&tbi3>; | |
514 | phy-handle = <&phy3>; | |
515 | phy-connection-type = "sgmii"; | |
516 | ||
517 | mdio@520 { | |
518 | #address-cells = <1>; | |
519 | #size-cells = <0>; | |
520 | compatible = "fsl,gianfar-tbi"; | |
521 | reg = <0x520 0x20>; | |
522 | ||
523 | tbi3: tbi-phy@11 { | |
524 | reg = <0x11>; | |
525 | device_type = "tbi-phy"; | |
526 | }; | |
527 | }; | |
528 | }; | |
529 | ||
530 | /* UART0 */ | |
531 | serial0: serial@4500 { | |
532 | cell-index = <0>; | |
533 | device_type = "serial"; | |
f706bed1 | 534 | compatible = "fsl,ns16550", "ns16550"; |
317bf653 NC |
535 | reg = <0x4500 0x100>; |
536 | clock-frequency = <0>; | |
537 | interrupts = <42 2>; | |
538 | interrupt-parent = <&mpic>; | |
539 | }; | |
540 | ||
541 | /* UART1 */ | |
542 | serial1: serial@4600 { | |
543 | cell-index = <1>; | |
544 | device_type = "serial"; | |
f706bed1 | 545 | compatible = "fsl,ns16550", "ns16550"; |
317bf653 NC |
546 | reg = <0x4600 0x100>; |
547 | clock-frequency = <0>; | |
548 | interrupts = <42 2>; | |
549 | interrupt-parent = <&mpic>; | |
550 | }; | |
551 | ||
552 | global-utilities@e0000 { //global utilities block | |
553 | compatible = "fsl,mpc8572-guts"; | |
554 | reg = <0xe0000 0x1000>; | |
555 | fsl,has-rstcr; | |
556 | }; | |
557 | ||
558 | msi@41600 { | |
559 | compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; | |
560 | reg = <0x41600 0x80>; | |
561 | msi-available-ranges = <0 0x100>; | |
562 | interrupts = < | |
563 | 0xe0 0 | |
564 | 0xe1 0 | |
565 | 0xe2 0 | |
566 | 0xe3 0 | |
567 | 0xe4 0 | |
568 | 0xe5 0 | |
569 | 0xe6 0 | |
570 | 0xe7 0>; | |
571 | interrupt-parent = <&mpic>; | |
572 | }; | |
573 | ||
574 | crypto@30000 { | |
575 | compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", | |
576 | "fsl,sec2.1", "fsl,sec2.0"; | |
577 | reg = <0x30000 0x10000>; | |
578 | interrupts = <45 2 58 2>; | |
579 | interrupt-parent = <&mpic>; | |
580 | fsl,num-channels = <4>; | |
581 | fsl,channel-fifo-len = <24>; | |
582 | fsl,exec-units-mask = <0x9fe>; | |
583 | fsl,descriptor-types-mask = <0x3ab0ebf>; | |
584 | }; | |
585 | ||
586 | mpic: pic@40000 { | |
587 | interrupt-controller; | |
588 | #address-cells = <0>; | |
589 | #interrupt-cells = <2>; | |
590 | reg = <0x40000 0x40000>; | |
591 | compatible = "chrp,open-pic"; | |
592 | device_type = "open-pic"; | |
593 | }; | |
594 | ||
595 | gpio0: gpio@f000 { | |
596 | compatible = "fsl,mpc8572-gpio"; | |
597 | reg = <0xf000 0x1000>; | |
598 | interrupts = <47 2>; | |
599 | interrupt-parent = <&mpic>; | |
600 | #gpio-cells = <2>; | |
601 | gpio-controller; | |
602 | }; | |
603 | ||
604 | gpio-leds { | |
605 | compatible = "gpio-leds"; | |
606 | ||
607 | heartbeat { | |
608 | label = "Heartbeat"; | |
609 | gpios = <&gpio0 4 1>; | |
610 | linux,default-trigger = "heartbeat"; | |
611 | }; | |
612 | ||
613 | yellow { | |
614 | label = "Yellow"; | |
615 | gpios = <&gpio0 5 1>; | |
616 | }; | |
617 | ||
618 | red { | |
619 | label = "Red"; | |
620 | gpios = <&gpio0 6 1>; | |
621 | }; | |
622 | ||
623 | green { | |
624 | label = "Green"; | |
625 | gpios = <&gpio0 7 1>; | |
626 | }; | |
627 | }; | |
628 | ||
629 | /* PME (pattern-matcher) */ | |
630 | pme@10000 { | |
631 | compatible = "fsl,mpc8572-pme", "pme8572"; | |
632 | reg = <0x10000 0x5000>; | |
633 | interrupts = <57 2 64 2 65 2 66 2 67 2>; | |
634 | interrupt-parent = <&mpic>; | |
635 | }; | |
636 | ||
637 | tlu@2f000 { | |
638 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | |
639 | reg = <0x2f000 0x1000>; | |
53567cf3 | 640 | interrupts = <61 2>; |
317bf653 NC |
641 | interrupt-parent = <&mpic>; |
642 | }; | |
643 | ||
644 | tlu@15000 { | |
645 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | |
646 | reg = <0x15000 0x1000>; | |
53567cf3 | 647 | interrupts = <75 2>; |
317bf653 NC |
648 | interrupt-parent = <&mpic>; |
649 | }; | |
650 | }; | |
651 | ||
652 | /* | |
653 | * PCI Express controller 3 @ ef008000 is not used. | |
654 | * This would have been pci0 on other mpc85xx platforms. | |
655 | * | |
656 | * PCI Express controller 2 @ ef009000 is not used. | |
657 | * This would have been pci1 on other mpc85xx platforms. | |
658 | */ | |
659 | ||
660 | /* PCI Express controller 1, wired to PEX8648 PCIe switch */ | |
661 | pci2: pcie@ef00a000 { | |
662 | compatible = "fsl,mpc8548-pcie"; | |
663 | device_type = "pci"; | |
664 | #interrupt-cells = <1>; | |
665 | #size-cells = <2>; | |
666 | #address-cells = <3>; | |
667 | reg = <0 0xef00a000 0 0x1000>; | |
668 | bus-range = <0 255>; | |
669 | ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 | |
670 | 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; | |
671 | clock-frequency = <33333333>; | |
672 | interrupt-parent = <&mpic>; | |
673 | interrupts = <26 2>; | |
674 | interrupt-map-mask = <0xf800 0x0 0x0 0x7>; | |
675 | interrupt-map = < | |
676 | /* IDSEL 0x0 */ | |
677 | 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 | |
678 | 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 | |
679 | 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 | |
680 | 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 | |
681 | >; | |
682 | pcie@0 { | |
683 | reg = <0x0 0x0 0x0 0x0 0x0>; | |
684 | #size-cells = <2>; | |
685 | #address-cells = <3>; | |
686 | device_type = "pci"; | |
687 | ranges = <0x2000000 0x0 0x80000000 | |
688 | 0x2000000 0x0 0x80000000 | |
689 | 0x0 0x40000000 | |
690 | ||
691 | 0x1000000 0x0 0x0 | |
692 | 0x1000000 0x0 0x0 | |
693 | 0x0 0x100000>; | |
694 | }; | |
695 | }; | |
696 | }; |