Commit | Line | Data |
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30d992e3 MB |
1 | /* |
2 | * TQM5200 board Device Tree Source | |
3 | * | |
4 | * Copyright (C) 2007 Semihalf | |
5 | * Marian Balakowicz <m8@semihalf.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | */ | |
12 | ||
a2884f37 GL |
13 | /dts-v1/; |
14 | ||
30d992e3 MB |
15 | / { |
16 | model = "tqc,tqm5200"; | |
17 | compatible = "tqc,tqm5200"; | |
18 | #address-cells = <1>; | |
19 | #size-cells = <1>; | |
b8842451 | 20 | interrupt-parent = <&mpc5200_pic>; |
30d992e3 MB |
21 | |
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | PowerPC,5200@0 { | |
27 | device_type = "cpu"; | |
28 | reg = <0>; | |
a2884f37 GL |
29 | d-cache-line-size = <32>; |
30 | i-cache-line-size = <32>; | |
31 | d-cache-size = <0x4000>; // L1, 16K | |
32 | i-cache-size = <0x4000>; // L1, 16K | |
30d992e3 MB |
33 | timebase-frequency = <0>; // from bootloader |
34 | bus-frequency = <0>; // from bootloader | |
35 | clock-frequency = <0>; // from bootloader | |
36 | }; | |
37 | }; | |
38 | ||
39 | memory { | |
40 | device_type = "memory"; | |
a2884f37 | 41 | reg = <0x00000000 0x04000000>; // 64MB |
30d992e3 MB |
42 | }; |
43 | ||
44 | soc5200@f0000000 { | |
58a5be39 PG |
45 | #address-cells = <1>; |
46 | #size-cells = <1>; | |
24ce6bc4 | 47 | compatible = "fsl,mpc5200-immr"; |
a2884f37 GL |
48 | ranges = <0 0xf0000000 0x0000c000>; |
49 | reg = <0xf0000000 0x00000100>; | |
30d992e3 MB |
50 | bus-frequency = <0>; // from bootloader |
51 | system-frequency = <0>; // from bootloader | |
52 | ||
53 | cdm@200 { | |
24ce6bc4 | 54 | compatible = "fsl,mpc5200-cdm"; |
a2884f37 | 55 | reg = <0x200 0x38>; |
30d992e3 MB |
56 | }; |
57 | ||
24ce6bc4 | 58 | mpc5200_pic: interrupt-controller@500 { |
30d992e3 MB |
59 | // 5200 interrupts are encoded into two levels; |
60 | interrupt-controller; | |
61 | #interrupt-cells = <3>; | |
24ce6bc4 | 62 | compatible = "fsl,mpc5200-pic"; |
a2884f37 | 63 | reg = <0x500 0x80>; |
30d992e3 MB |
64 | }; |
65 | ||
24ce6bc4 | 66 | timer@600 { // General Purpose Timer |
30d992e3 | 67 | compatible = "fsl,mpc5200-gpt"; |
a2884f37 | 68 | reg = <0x600 0x10>; |
30d992e3 | 69 | interrupts = <1 9 0>; |
30d992e3 MB |
70 | fsl,has-wdt; |
71 | }; | |
72 | ||
b0852cb8 WG |
73 | can@900 { |
74 | compatible = "fsl,mpc5200-mscan"; | |
75 | interrupts = <2 17 0>; | |
b0852cb8 WG |
76 | reg = <0x900 0x80>; |
77 | }; | |
78 | ||
79 | can@980 { | |
80 | compatible = "fsl,mpc5200-mscan"; | |
81 | interrupts = <2 18 0>; | |
b0852cb8 WG |
82 | reg = <0x980 0x80>; |
83 | }; | |
84 | ||
b8842451 | 85 | gpio_simple: gpio@b00 { |
24ce6bc4 | 86 | compatible = "fsl,mpc5200-gpio"; |
a2884f37 | 87 | reg = <0xb00 0x40>; |
30d992e3 | 88 | interrupts = <1 7 0>; |
b8842451 GL |
89 | gpio-controller; |
90 | #gpio-cells = <2>; | |
30d992e3 MB |
91 | }; |
92 | ||
93 | usb@1000 { | |
24ce6bc4 | 94 | compatible = "fsl,mpc5200-ohci","ohci-be"; |
a2884f37 | 95 | reg = <0x1000 0xff>; |
30d992e3 | 96 | interrupts = <2 6 0>; |
30d992e3 MB |
97 | }; |
98 | ||
99 | dma-controller@1200 { | |
24ce6bc4 | 100 | compatible = "fsl,mpc5200-bestcomm"; |
a2884f37 | 101 | reg = <0x1200 0x80>; |
30d992e3 MB |
102 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
103 | 3 4 0 3 5 0 3 6 0 3 7 0 | |
a2884f37 GL |
104 | 3 8 0 3 9 0 3 10 0 3 11 0 |
105 | 3 12 0 3 13 0 3 14 0 3 15 0>; | |
30d992e3 MB |
106 | }; |
107 | ||
108 | xlb@1f00 { | |
24ce6bc4 | 109 | compatible = "fsl,mpc5200-xlb"; |
a2884f37 | 110 | reg = <0x1f00 0x100>; |
30d992e3 MB |
111 | }; |
112 | ||
113 | serial@2000 { // PSC1 | |
24ce6bc4 | 114 | compatible = "fsl,mpc5200-psc-uart"; |
a2884f37 | 115 | reg = <0x2000 0x100>; |
30d992e3 | 116 | interrupts = <2 1 0>; |
30d992e3 MB |
117 | }; |
118 | ||
119 | serial@2200 { // PSC2 | |
24ce6bc4 | 120 | compatible = "fsl,mpc5200-psc-uart"; |
a2884f37 | 121 | reg = <0x2200 0x100>; |
30d992e3 | 122 | interrupts = <2 2 0>; |
30d992e3 MB |
123 | }; |
124 | ||
125 | serial@2400 { // PSC3 | |
24ce6bc4 | 126 | compatible = "fsl,mpc5200-psc-uart"; |
a2884f37 | 127 | reg = <0x2400 0x100>; |
30d992e3 | 128 | interrupts = <2 3 0>; |
30d992e3 MB |
129 | }; |
130 | ||
131 | ethernet@3000 { | |
24ce6bc4 | 132 | compatible = "fsl,mpc5200-fec"; |
a2884f37 | 133 | reg = <0x3000 0x400>; |
24ce6bc4 | 134 | local-mac-address = [ 00 00 00 00 00 00 ]; |
30d992e3 | 135 | interrupts = <2 5 0>; |
115e1adc BS |
136 | phy-handle = <&phy0>; |
137 | }; | |
138 | ||
139 | mdio@3000 { | |
140 | #address-cells = <1>; | |
141 | #size-cells = <0>; | |
a2884f37 GL |
142 | compatible = "fsl,mpc5200-mdio"; |
143 | reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts | |
115e1adc | 144 | interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. |
115e1adc BS |
145 | |
146 | phy0: ethernet-phy@0 { | |
115e1adc BS |
147 | reg = <0>; |
148 | }; | |
30d992e3 MB |
149 | }; |
150 | ||
151 | ata@3a00 { | |
24ce6bc4 | 152 | compatible = "fsl,mpc5200-ata"; |
a2884f37 | 153 | reg = <0x3a00 0x100>; |
30d992e3 | 154 | interrupts = <2 7 0>; |
30d992e3 MB |
155 | }; |
156 | ||
157 | i2c@3d40 { | |
115e1adc BS |
158 | #address-cells = <1>; |
159 | #size-cells = <0>; | |
24ce6bc4 | 160 | compatible = "fsl,mpc5200-i2c","fsl-i2c"; |
a2884f37 GL |
161 | reg = <0x3d40 0x40>; |
162 | interrupts = <2 16 0>; | |
115e1adc BS |
163 | |
164 | rtc@68 { | |
115e1adc | 165 | compatible = "dallas,ds1307"; |
a2884f37 | 166 | reg = <0x68>; |
115e1adc | 167 | }; |
30d992e3 MB |
168 | }; |
169 | ||
170 | sram@8000 { | |
24ce6bc4 | 171 | compatible = "fsl,mpc5200-sram"; |
a2884f37 | 172 | reg = <0x8000 0x4000>; |
30d992e3 MB |
173 | }; |
174 | }; | |
175 | ||
b8842451 GL |
176 | localbus { |
177 | compatible = "fsl,mpc5200-lpb","simple-bus"; | |
115e1adc BS |
178 | #address-cells = <2>; |
179 | #size-cells = <1>; | |
a2884f37 | 180 | ranges = <0 0 0xfc000000 0x02000000>; |
115e1adc BS |
181 | |
182 | flash@0,0 { | |
183 | compatible = "cfi-flash"; | |
a2884f37 | 184 | reg = <0 0 0x02000000>; |
115e1adc BS |
185 | bank-width = <4>; |
186 | device-width = <2>; | |
187 | #size-cells = <1>; | |
188 | #address-cells = <1>; | |
189 | }; | |
190 | }; | |
191 | ||
30d992e3 MB |
192 | pci@f0000d00 { |
193 | #interrupt-cells = <1>; | |
194 | #size-cells = <2>; | |
195 | #address-cells = <3>; | |
196 | device_type = "pci"; | |
197 | compatible = "fsl,mpc5200-pci"; | |
a2884f37 GL |
198 | reg = <0xf0000d00 0x100>; |
199 | interrupt-map-mask = <0xf800 0 0 7>; | |
200 | interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 | |
201 | 0xc000 0 0 2 &mpc5200_pic 0 0 3 | |
202 | 0xc000 0 0 3 &mpc5200_pic 0 0 3 | |
203 | 0xc000 0 0 4 &mpc5200_pic 0 0 3>; | |
30d992e3 | 204 | clock-frequency = <0>; // From boot loader |
a2884f37 | 205 | interrupts = <2 8 0 2 9 0 2 10 0>; |
30d992e3 | 206 | bus-range = <0 0>; |
a2884f37 GL |
207 | ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 |
208 | 0x02000000 0 0x90000000 0x90000000 0 0x10000000 | |
209 | 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>; | |
30d992e3 MB |
210 | }; |
211 | }; |