[linux-2.6-block.git] / arch / powerpc / boot / dts / t4240emu.dts

/*
 * T4240 emulator Device Tree Source
 *
 * Copyright 2013 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

/include/ "fsl/e6500_power_isa.dtsi"
/ {
	compatible = "fsl,T4240";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ccsr = &soc;

		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		dma0 = &dma0;
		dma1 = &dma1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: PowerPC,e6500@0 {
			device_type = "cpu";
			reg = <0 1>;
			next-level-cache = <&L2_1>;
		};
		cpu1: PowerPC,e6500@2 {
			device_type = "cpu";
			reg = <2 3>;
			next-level-cache = <&L2_1>;
		};
		cpu2: PowerPC,e6500@4 {
			device_type = "cpu";
			reg = <4 5>;
			next-level-cache = <&L2_1>;
		};
		cpu3: PowerPC,e6500@6 {
			device_type = "cpu";
			reg = <6 7>;
			next-level-cache = <&L2_1>;
		};

		cpu4: PowerPC,e6500@8 {
			device_type = "cpu";
			reg = <8 9>;
			next-level-cache = <&L2_2>;
		};
		cpu5: PowerPC,e6500@10 {
			device_type = "cpu";
			reg = <10 11>;
			next-level-cache = <&L2_2>;
		};
		cpu6: PowerPC,e6500@12 {
			device_type = "cpu";
			reg = <12 13>;
			next-level-cache = <&L2_2>;
		};
		cpu7: PowerPC,e6500@14 {
			device_type = "cpu";
			reg = <14 15>;
			next-level-cache = <&L2_2>;
		};

		cpu8: PowerPC,e6500@16 {
			device_type = "cpu";
			reg = <16 17>;
			next-level-cache = <&L2_3>;
		};
		cpu9: PowerPC,e6500@18 {
			device_type = "cpu";
			reg = <18 19>;
			next-level-cache = <&L2_3>;
		};
		cpu10: PowerPC,e6500@20 {
			device_type = "cpu";
			reg = <20 21>;
			next-level-cache = <&L2_3>;
		};
		cpu11: PowerPC,e6500@22 {
			device_type = "cpu";
			reg = <22 23>;
			next-level-cache = <&L2_3>;
		};
	};
};

/ {
	model = "fsl,T4240QDS";
	compatible = "fsl,T4240EMU", "fsl,T4240QDS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	ifc: localbus@ffe124000 {
		reg = <0xf 0xfe124000 0 0x2000>;
		ranges = <0 0 0xf 0xe8000000 0x08000000
			  2 0 0xf 0xff800000 0x00010000
			  3 0 0xf 0xffdf0000 0x00008000>;

		nor@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x8000000>;

			bank-width = <2>;
			device-width = <1>;
		};

	};

	memory {
		device_type = "memory";
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;

	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	compatible = "fsl,ifc", "simple-bus";
	interrupts = <25 2 0 0>;
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "simple-bus";

	soc-sram-error {
		compatible = "fsl,soc-sram-error";
		interrupts = <16 2 1 29>;
	};

	corenet-law@0 {
		compatible = "fsl,corenet-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <32>;
	};

	ddr1: memory-controller@8000 {
		compatible = "fsl,qoriq-memory-controller-v4.7",
				"fsl,qoriq-memory-controller";
		reg = <0x8000 0x1000>;
		interrupts = <16 2 1 23>;
	};

	ddr2: memory-controller@9000 {
		compatible = "fsl,qoriq-memory-controller-v4.7",
				"fsl,qoriq-memory-controller";
		reg = <0x9000 0x1000>;
		interrupts = <16 2 1 22>;
	};

	ddr3: memory-controller@a000 {
		compatible = "fsl,qoriq-memory-controller-v4.7",
				"fsl,qoriq-memory-controller";
		reg = <0xa000 0x1000>;
		interrupts = <16 2 1 21>;
	};

	cpc: l3-cache-controller@10000 {
		compatible = "fsl,t4240-l3-cache-controller", "cache";
		reg = <0x10000 0x1000
		       0x11000 0x1000
		       0x12000 0x1000>;
		interrupts = <16 2 1 27
			      16 2 1 26
			      16 2 1 25>;
	};

	corenet-cf@18000 {
		compatible = "fsl,corenet-cf";
		reg = <0x18000 0x1000>;
		interrupts = <16 2 1 31>;
		fsl,ccf-num-csdids = <32>;
		fsl,ccf-num-snoopids = <32>;
	};

	iommu@20000 {
		compatible = "fsl,pamu-v1.0", "fsl,pamu";
		reg = <0x20000 0x6000>;
		interrupts = <
			24 2 0 0
			16 2 1 30>;
	};

/include/ "fsl/qoriq-mpic.dtsi"

	guts: global-utilities@e0000 {
		compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
		reg = <0xe0000 0xe00>;
		fsl,has-rstcr;
		fsl,liodn-bits = <12>;
	};

	clockgen: global-utilities@e1000 {
		compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
		reg = <0xe1000 0x1000>;
	};

/include/ "fsl/qoriq-dma-0.dtsi"
/include/ "fsl/qoriq-dma-1.dtsi"

/include/ "fsl/qoriq-i2c-0.dtsi"
/include/ "fsl/qoriq-i2c-1.dtsi"
/include/ "fsl/qoriq-duart-0.dtsi"
/include/ "fsl/qoriq-duart-1.dtsi"

	L2_1: l2-cache-controller@c20000 {
		compatible = "fsl,t4240-l2-cache-controller";
		reg = <0xc20000 0x40000>;
		next-level-cache = <&cpc>;
	};
	L2_2: l2-cache-controller@c60000 {
		compatible = "fsl,t4240-l2-cache-controller";
		reg = <0xc60000 0x40000>;
		next-level-cache = <&cpc>;
	};
	L2_3: l2-cache-controller@ca0000 {
		compatible = "fsl,t4240-l2-cache-controller";
		reg = <0xca0000 0x40000>;
		next-level-cache = <&cpc>;
	};
};
Commit	Line	Data
8f4af7df YS	1	/*
	2	* T4240 emulator Device Tree Source
	3	*
	4	* Copyright 2013 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	/dts-v1/;
	36
	37	/include/ "fsl/e6500_power_isa.dtsi"
	38	/ {
	39	compatible = "fsl,T4240";
	40	#address-cells = <2>;
	41	#size-cells = <2>;
	42	interrupt-parent = <&mpic>;
	43
	44	aliases {
	45	ccsr = &soc;
	46
	47	serial0 = &serial0;
	48	serial1 = &serial1;
	49	serial2 = &serial2;
	50	serial3 = &serial3;
	51	dma0 = &dma0;
	52	dma1 = &dma1;
	53	};
	54
	55	cpus {
	56	#address-cells = <1>;
	57	#size-cells = <0>;
	58
	59	cpu0: PowerPC,e6500@0 {
	60	device_type = "cpu";
	61	reg = <0 1>;
	62	next-level-cache = <&L2_1>;
	63	};
	64	cpu1: PowerPC,e6500@2 {
65	device_type = "cpu";
66	reg = <2 3>;
67	next-level-cache = <&L2_1>;
68	};
69	cpu2: PowerPC,e6500@4 {
70	device_type = "cpu";
71	reg = <4 5>;
72	next-level-cache = <&L2_1>;
73	};
74	cpu3: PowerPC,e6500@6 {
75	device_type = "cpu";
76	reg = <6 7>;
77	next-level-cache = <&L2_1>;
78	};
79
80	cpu4: PowerPC,e6500@8 {
81	device_type = "cpu";
82	reg = <8 9>;
83	next-level-cache = <&L2_2>;
84	};
85	cpu5: PowerPC,e6500@10 {
86	device_type = "cpu";
87	reg = <10 11>;
88	next-level-cache = <&L2_2>;
89	};
90	cpu6: PowerPC,e6500@12 {
91	device_type = "cpu";
92	reg = <12 13>;
93	next-level-cache = <&L2_2>;
94	};
95	cpu7: PowerPC,e6500@14 {
96	device_type = "cpu";
97	reg = <14 15>;
98	next-level-cache = <&L2_2>;
99	};
100
101	cpu8: PowerPC,e6500@16 {
102	device_type = "cpu";
103	reg = <16 17>;
104	next-level-cache = <&L2_3>;
105	};
106	cpu9: PowerPC,e6500@18 {
107	device_type = "cpu";
108	reg = <18 19>;
109	next-level-cache = <&L2_3>;
110	};
111	cpu10: PowerPC,e6500@20 {
112	device_type = "cpu";
113	reg = <20 21>;
114	next-level-cache = <&L2_3>;
115	};
116	cpu11: PowerPC,e6500@22 {
117	device_type = "cpu";
118	reg = <22 23>;
119	next-level-cache = <&L2_3>;
120	};
121	};
122	};
123
124	/ {
125	model = "fsl,T4240QDS";
126	compatible = "fsl,T4240EMU", "fsl,T4240QDS";
127	#address-cells = <2>;
128	#size-cells = <2>;
129	interrupt-parent = <&mpic>;
130
131	ifc: localbus@ffe124000 {
132	reg = <0xf 0xfe124000 0 0x2000>;
133	ranges = <0 0 0xf 0xe8000000 0x08000000
134	2 0 0xf 0xff800000 0x00010000
135	3 0 0xf 0xffdf0000 0x00008000>;
136
137	nor@0,0 {
138	#address-cells = <1>;
139	#size-cells = <1>;
140	compatible = "cfi-flash";
141	reg = <0x0 0x0 0x8000000>;
142
143	bank-width = <2>;
144	device-width = <1>;
145	};
146
147	};
148
149	memory {
150	device_type = "memory";
151	};
152
153	soc: soc@ffe000000 {
154	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
155	reg = <0xf 0xfe000000 0 0x00001000>;
156
157	};
158	};
159
160	&ifc {
161	#address-cells = <2>;
162	#size-cells = <1>;
163	compatible = "fsl,ifc", "simple-bus";
164	interrupts = <25 2 0 0>;
165	};
166
167	&soc {
168	#address-cells = <1>;
169	#size-cells = <1>;
170	device_type = "soc";
171	compatible = "simple-bus";
172
173	soc-sram-error {
174	compatible = "fsl,soc-sram-error";
175	interrupts = <16 2 1 29>;
176	};
177
178	corenet-law@0 {
179	compatible = "fsl,corenet-law";
180	reg = <0x0 0x1000>;
181	fsl,num-laws = <32>;
182	};
183
184	ddr1: memory-controller@8000 {
185	compatible = "fsl,qoriq-memory-controller-v4.7",
186	"fsl,qoriq-memory-controller";
187	reg = <0x8000 0x1000>;
188	interrupts = <16 2 1 23>;
189	};
190
191	ddr2: memory-controller@9000 {
192	compatible = "fsl,qoriq-memory-controller-v4.7",
193	"fsl,qoriq-memory-controller";
194	reg = <0x9000 0x1000>;
195	interrupts = <16 2 1 22>;
196	};
197
198	ddr3: memory-controller@a000 {
199	compatible = "fsl,qoriq-memory-controller-v4.7",
200	"fsl,qoriq-memory-controller";
201	reg = <0xa000 0x1000>;
202	interrupts = <16 2 1 21>;
203	};
204
205	cpc: l3-cache-controller@10000 {
206	compatible = "fsl,t4240-l3-cache-controller", "cache";
207	reg = <0x10000 0x1000
208	0x11000 0x1000
209	0x12000 0x1000>;
210	interrupts = <16 2 1 27
211	16 2 1 26
212	16 2 1 25>;
213	};
214
215	corenet-cf@18000 {
216	compatible = "fsl,corenet-cf";
217	reg = <0x18000 0x1000>;
218	interrupts = <16 2 1 31>;
219	fsl,ccf-num-csdids = <32>;
220	fsl,ccf-num-snoopids = <32>;
221	};
222
223	iommu@20000 {
224	compatible = "fsl,pamu-v1.0", "fsl,pamu";
225	reg = <0x20000 0x6000>;
226	interrupts = <
227	24 2 0 0
228	16 2 1 30>;
229	};
230
231	/include/ "fsl/qoriq-mpic.dtsi"
232
233	guts: global-utilities@e0000 {
234	compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
235	reg = <0xe0000 0xe00>;
236	fsl,has-rstcr;
237	fsl,liodn-bits = <12>;
238	};
239
240	clockgen: global-utilities@e1000 {
241	compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
242	reg = <0xe1000 0x1000>;
243	};
244
245	/include/ "fsl/qoriq-dma-0.dtsi"
246	/include/ "fsl/qoriq-dma-1.dtsi"
247
248	/include/ "fsl/qoriq-i2c-0.dtsi"
249	/include/ "fsl/qoriq-i2c-1.dtsi"
250	/include/ "fsl/qoriq-duart-0.dtsi"
251	/include/ "fsl/qoriq-duart-1.dtsi"
252
253	L2_1: l2-cache-controller@c20000 {
254	compatible = "fsl,t4240-l2-cache-controller";
255	reg = <0xc20000 0x40000>;
256	next-level-cache = <&cpc>;
257	};
258	L2_2: l2-cache-controller@c60000 {
259	compatible = "fsl,t4240-l2-cache-controller";
260	reg = <0xc60000 0x40000>;
261	next-level-cache = <&cpc>;
262	};
263	L2_3: l2-cache-controller@ca0000 {
264	compatible = "fsl,t4240-l2-cache-controller";
265	reg = <0xca0000 0x40000>;
266	next-level-cache = <&cpc>;
267	};
268	};